The SDRAM controller and external SDRAM chip will clock on the same edge
if the frequency and divided frequency are both greater than the minimum DLL lock frequency.
Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges
to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM.
| clkin : IBUFG |
| dllint : CLKDLL |
| generate an internal clock sync'ed to the master clock |
| Generic map: |
| |
| CLKDV_DIVIDE | => CLKDV_DIVIDE |
|
| This instantiation is inside the following construct: |
| | gen_dlls : if IN_PHASE generate |
| | | Generate the DLLs for sync'ing the clocks as long as the clocks
have a frequency high enough for the DLLs to lock |
| int_clk1x_buf : BUFG |
| sync'ed single, doubled and divided clocks for use by internal logic |
| This instantiation is inside the following construct: |
| | gen_dlls : if IN_PHASE generate |
| | | Generate the DLLs for sync'ing the clocks as long as the clocks
have a frequency high enough for the DLLs to lock |
| int_clk2x_buf : BUFG |
| sync'ed single, doubled and divided clocks for use by internal logic |
| This instantiation is inside the following construct: |
| | gen_dlls : if IN_PHASE generate |
| | | Generate the DLLs for sync'ing the clocks as long as the clocks
have a frequency high enough for the DLLs to lock |
| int_clkdv_buf : BUFG |
| sync'ed single, doubled and divided clocks for use by internal logic |
| This instantiation is inside the following construct: |
| | gen_dlls : if IN_PHASE generate |
| | | Generate the DLLs for sync'ing the clocks as long as the clocks
have a frequency high enough for the DLLs to lock |
| SRL16_inst : SRL16 |
| The external DLL is held in a reset state until the internal DLL locks.
Then the external DLL reset is released after a delay set by this shift register.
This keeps the external DLL from locking onto the internal DLL clock signal
until it is stable. |
| Generic map: |
| | |
| This instantiation is inside the following construct: |
| | gen_dlls : if IN_PHASE generate |
| | | Generate the DLLs for sync'ing the clocks as long as the clocks
have a frequency high enough for the DLLs to lock |
| sclkfb_buf : IBUFG |
| generate an external SDRAM clock sync'ed to the master clock |
| This instantiation is inside the following construct: |
| | gen_dlls : if IN_PHASE generate |
| | | Generate the DLLs for sync'ing the clocks as long as the clocks
have a frequency high enough for the DLLs to lock |
| dllext : CLKDLL |
| sclkfb_buf : BUFGMUX port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays |
| This instantiation is inside the following construct: |
| | gen_dlls : if IN_PHASE generate |
| | | Generate the DLLs for sync'ing the clocks as long as the clocks
have a frequency high enough for the DLLs to lock |
| u1 : sdramCntl |
| SDRAM memory controller module |
| Generic map: |
| |
| FREQ | => SDRAM_FREQ |
| IN_PHASE | => IN_PHASE |
| PIPE_EN | => PIPE_EN |
| MAX_NOP | => MAX_NOP |
| MULTIPLE_ACTIVE_ROWS | => MULTIPLE_ACTIVE_ROWS |
| DATA_WIDTH | => DATA_WIDTH |
| NROWS | => NROWS |
| NCOLS | => NCOLS |
| HADDR_WIDTH | => HADDR_WIDTH |
| SADDR_WIDTH | => SADDR_WIDTH |
|
| Binding: work.sdramCntl (arch) |