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Defined in VHDL/mul32.vhd
Author: John E. Kent
Version: 0.2 from 2010-06-17
Implements a 32 bit x 32 bit hardware multiplier register with 64 bit result. Consists of 16 x 8 bit registers. Designed for Spartan 3/3E with 18 x 18 bit multiplier blocks.
| library ieee | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all |
| mul_write ( clk ) | ||||
| mul_read ( addr, mul_reg0, mul_reg1, mul_reg2, mul_reg3, mul_reg4, mul_reg5, mul_reg6, mul_reg7, mul_reg8, mul_reg9, mul_reg10, mul_reg11, mul_reg12, mul_reg13, mul_reg14, mul_reg15 ) | ||||
| Read Multiplier Registers | ||||
| my_mul32 ( mul_reg0, mul_reg1, mul_reg2, mul_reg3, mul_reg4, mul_reg5, mul_reg6, mul_reg7 ) | ||||
| Perform 32 x 32 multiply | ||||