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Architecture rtl of work.my_system09

Defined in System09_base/my_system09.vhd

Author: John E. Kent
Version: 4.0 from 1st February 2008


Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
library unisim
use unisim.vcomponents.all
library work
use work.common.all
use WORK.xsasdram.all

Type declarations

typehold_state_typeis ( hold_release_state, hold_request_state )
typeram_rd_typeis (rd_state0, rd_state1, rd_state2, rd_state3)
typeram_wr_typeis (wr_state0, wr_state1, wr_state2, wr_state3, wr_state4)

Constants

SYS_Clock_Frequency integer := 50000000
PIX_Clock_Frequency integer := 25000000
CPU_Clock_Frequency integer := 25000000
BAUD_Rate integer := 57600
ACIA_Clock_Frequency integer := BAUD_Rate * 16
FREQ natural := 100_000
CLK_DIV real := 2.0
PIPE_EN boolean := false
MAX_NOP natural := 10000
MULTIPLE_ACTIVE_ROWS boolean := false
DATA_WIDTH natural := 16
NROWS natural := 8192
NCOLS natural := 512
HADDR_WIDTH natural := 24
SADDR_WIDTH natural := 13

Component declarations

cpu09
CPU09 CPU core
Default binding: work.cpu09
mon_rom
4K Block RAM Monitor ROM
Default binding: work.mon_rom
flex_ram
8KBytes Block RAM for FLEX9 $C000 - $DFFF
Default binding: work.flex_ram
ACIA_6850
6850 Compatible ACIA / UART
Default binding: work.ACIA_6850
ACIA_Clock
ACIA Clock divider
Default binding: work.acia_clock
keyboard
PS/2 Keyboard
Default binding: work.keyboard
vdu8
Video Display Unit.
Default binding: work.vdu8
timer
Timer module
Default binding: work.timer
trap
Bus Trap logic
Default binding: work.trap
dat_ram
Dynamic Address Translation Registers
Default binding: work.dat_ram
XSASDRAMCntl
Default binding: work.XSASDRAMCntl
BUFG
Clock buffer

Processes

mem_decode ( cpu_clk, cpu_addr, cpu_rw, cpu_vma, dat_addr, rom_data_out, flex_data_out, acia_data_out, keyboard_data_out, vdu_data_out, pb_data_out, timer_data_out, trap_data_out, ram_data_out )
Process to decode memory map
peripheral_bus ( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
16-bit Peripheral Bus, 6809 Big endian, ISA bus little endian. Not sure about IDE interface
peripheral_bus_hold ( cpu_clk, cpu_reset, pb_rdu, pb_wrl, ether_rdy )
Hold Peripheral bus accesses for a few cycles
compact_flash ( ide_cs, cpu_addr )
Compact Flash Control
interrupts ( lock, rst_n, nmi_n, pb_cs, pb_hold, pb_release, ram_cs, ram_hold, ether_irq, acia_irq, keyboard_irq, trap_irq, timer_irq )
Interrupts and other bus control signals
my_led_flasher ( Clk_i, rst_n, CountL )
Flash 7 segment LEDS
my_prescaler ( Clk_i, clk_count )
Generate a 25 MHz Clock from 50 MHz
my_switch_assignments ( SW2_N, SW3_N, rst_n )
Push buttons
my_acia_assignments ( RS232_RXD, RS232_CTS, txd, rts_n )
RS232 signals:
my_ethernet_assignments ( clk_i, cpu_reset, ether_cs )
Pin assignments for ethernet controller
my_slot_assignments ( slot1_cs, slot2_cs)
I/O expansion slot assignments
my_vga_assignments ( vga_red_o, vga_green_o, vga_blue_o )
VGA ouputs
my_sdram_assignments ( cpu_clk, clk_i, cpu_reset, opBegun, rdDone, wrDone, ram_rd_state, ram_wr_state, cpu_addr, dat_addr, cpu_data_out, hDout, ram_cs, cpu_rw, ram_hold )
SDRAM assignments

Instantiations

my_cpu : cpu09
Binding: work.cpu09 (rtl)
my_rom : mon_rom
Binding: work.mon_rom (rtl)
my_flex : flex_ram
Binding: work.flex_ram (rtl)
my_acia : ACIA_6850
Binding: work.ACIA_6850 (rtl)
my_ACIA_Clock : ACIA_Clock
Generic map:
SYS_Clock_Frequency => SYS_Clock_Frequency
ACIA_Clock_Frequency => ACIA_Clock_Frequency
Binding: work.acia_clock (rtl)
my_keyboard : keyboard
PS/2 Keyboard Interface
Generic map:
KBD_Clock_Frequency => CPU_Clock_frequency
Binding: work.keyboard (rtl)
my_vdu : vdu8
Video Display Unit instantiation
Generic map:
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency
VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency
VGA_HOR_CHARS => 80
VGA_VER_CHARS => 25
VGA_PIXELS_PER_CHAR => 8
VGA_LINES_PER_CHAR => 16
VGA_HOR_BACK_PORCH => 40
VGA_HOR_SYNC => 96
VGA_HOR_FRONT_PORCH => 24
VGA_VER_BACK_PORCH => 13
VGA_VER_SYNC => 1
VGA_VER_FRONT_PORCH => 36
Binding: work.vdu8 (RTL)
my_timer : timer
Timer Module
Binding: work.timer (rtl)
my_trap : trap
Bus Trap Interrupt logic
Binding: work.trap (trap_arch)
my_dat : dat_ram
Binding: work.dat_ram (rtl)
u1 : xsaSDRAMCntl
Instantiate the SDRAM controller that connects to the memory tester module and interfaces to the external SDRAM chip.
Generic map:
FREQ => FREQ
PIPE_EN => PIPE_EN
DATA_WIDTH => DATA_WIDTH
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS
NROWS => NROWS
NCOLS => NCOLS
HADDR_WIDTH => HADDR_WIDTH
SADDR_WIDTH => SADDR_WIDTH
Binding: work.XSASDRAMCntl (arch)
cpu_clk_buffer : BUFG
pix_clk_buffer : BUFG

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