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Defined in VHDL/unicpu09.vhd
Author: John E. Kent
Version: 0.2 from 2010-06-16
Implements a single 6809 CPU module with Dynamic Address Translation, CPU Module ID register and 32 bit Hardware Multiplier register.
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_arith.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all |
| cpu09 | ||||
| Default binding: work.cpu09 | ||||
| mmu | ||||
| Memory Management Unit (32 x 16) | ||||
| mon_rom | ||||
| 4KByte Block RAM Monitor ROM | ||||
| Default binding: work.mon_rom | ||||
| dpr_2k | ||||
| Dual Port Cache memory 2K x 8 Bit | ||||
| mul32 | ||||
| 32 bit hardware multiplier | ||||
| Default binding: work.mul32 | ||||
| uni_decode ( cpu_addr, cpu_rw, cpu_vma, cache_hdata_out, dat_cs, dat_addr, cache_hdata_out, mul_data_out, rom_data_out ) | ||||
| Process to decode internal registers | ||||
| my_cpu_cache ( cpu_vma, cpu_rw, cpu_data_out, cpu_addr, dat_addr, cache_haddr, cache_hen, ext_cs ) | ||||
| cpu side cache controller | ||||
| my_mem_cache ( mem_vma, mem_addr, mem_data_in, mem_rw, cache_saddr, cache_sdata_out ) | ||||
| memory side cache controller | ||||
| my_cpu : cpu09 | ||||
| Binding: work.cpu09 (rtl) | ||||
| my_mmu : mmu | ||||
| my_rom : mon_rom | ||||
| Binding: work.mon_rom (rtl) | ||||
| my_dpr_0 : dpr_2k | ||||
| High Address Cache | ||||
| my_dpr_1 : dpr_2k | ||||
| Low Address cache | ||||
| my_dpr_2 : dpr_2k | ||||
| data cache | ||||
| my_mul32 : mul32 | ||||
| Binding: work.mul32 (rtl) | ||||