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Entity work.my_system09

Top level file for 6809 compatible system on a chip

Defined in System09_base/my_system09.vhd

Author: John E. Kent
Version: 4.0 from 1st February 2008


Detailed description

Designed with Xilinx XC3S1000 Spartan 3 FPGA. Implemented With XESS XSA-3S1000 FPGA board.

Note : This configuration can run Flex9 however it only has 32k bytes of user memory and the VDU is monochrome. The design needs to be updated to use the SDRAM on the XSA-3S1000 board. This configuration also lacks a DAT so cannot use the RAM Disk features of SYS09BUG.

Architectures

rtl


Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
library unisim
use unisim.vcomponents.all
library work
use work.common.all
use WORK.xsasdram.all

Ports

CLKA inStd_Logic
SW2_N inStd_logic
SW3_N inStd_logic
ps2_clk inoutStd_logic
PS/2 Keyboard
ps2_dat inoutStd_Logic
PS/2 Keyboard
vga_vsync_n outStd_Logic
CRTC output signals
vga_hsync_n outStd_Logic
CRTC output signals
vga_blue outstd_logic_vector(2 downto 0)
CRTC output signals
vga_green outstd_logic_vector(2 downto 0)
CRTC output signals
vga_red outstd_logic_vector(2 downto 0)
CRTC output signals
RS232_RXD inStd_Logic
RS232 Port
RS232_TXD outStd_Logic
RS232 Port
RS232_CTS inStd_Logic
RS232 Port
RS232_RTS outStd_Logic
RS232 Port
SDRAM_clkfb instd_logic
SDRAM side
SDRAM_clkout outstd_logic
SDRAM side
SDRAM_CKE outstd_logic
SDRAM side
SDRAM_CS_N outstd_logic
SDRAM side
SDRAM_RAS_N outstd_logic
SDRAM side
SDRAM_CAS_N outstd_logic
SDRAM side
SDRAM_WE_N outstd_logic
SDRAM side
SDRAM_BA outstd_logic_vector(1 downto 0)
SDRAM side
SDRAM_A outstd_logic_vector(12 downto 0)
SDRAM side
SDRAM_D inoutstd_logic_vector(15 downto 0)
SDRAM side
SDRAM_DQMH outstd_logic
SDRAM side
SDRAM_DQML outstd_logic
SDRAM side
PB_RD_N outstd_logic
Peripheral I/O bus $E100 - $E1FF
PB_WR_N outstd_logic
Peripheral I/O bus $E100 - $E1FF
PB_A outstd_logic_vector(4 downto 0)
Peripheral I/O bus $E100 - $E1FF
PB_D inoutstd_logic_vector(15 downto 0)
Peripheral I/O bus $E100 - $E1FF
ide_dmack_n outstd_logic
IDE Compact Flash $E100 - $E13F
ide_cs0_n outstd_logic
IDE Compact Flash $E100 - $E13F
ide_cs1_n outstd_logic
IDE Compact Flash $E100 - $E13F
ether_cs_n outstd_logic
Ethernet $E140 - $E17F
ether_aen outstd_logic
Ethernet $E140 - $E17F
ether_bhe_n outstd_logic
Ethernet $E140 - $E17F
ether_clk instd_logic
Ethernet $E140 - $E17F
ether_rdy instd_logic
Ethernet $E140 - $E17F
ether_irq instd_logic
Ethernet $E140 - $E17F
slot1_cs_n outstd_logic
Slot 1 $E180 - $E1BF
slot2_cs_n outstd_logic
Slot 2 $E1C0 - $E1FF
FLASH_CE_N outstd_logic
Disable Flash

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