Home -- Hierarchy -- Packages -- Entities -- Instantiations -- Sources |
Top level file for 6809 compatible system on a chip
Defined in System09_base/my_system09.vhd
Author: John E. Kent
Version: 4.0 from 1st February 2008
Designed with Xilinx XC3S1000 Spartan 3 FPGA. Implemented With XESS XSA-3S1000 FPGA board.
Note : This configuration can run Flex9 however it only has 32k bytes of user memory and the VDU is monochrome. The design needs to be updated to use the SDRAM on the XSA-3S1000 board. This configuration also lacks a DAT so cannot use the RAM Disk features of SYS09BUG.
library ieee | |
use ieee.numeric_std.all | |
use ieee.std_logic_1164.all | |
use IEEE.STD_LOGIC_ARITH.ALL | |
use IEEE.STD_LOGIC_UNSIGNED.ALL | |
library unisim | |
use unisim.vcomponents.all | |
library work | |
use work.common.all | |
use WORK.xsasdram.all |
CLKA | in | Std_Logic | |
SW2_N | in | Std_logic | |
SW3_N | in | Std_logic | |
ps2_clk | inout | Std_logic | |
PS/2 Keyboard | |||
ps2_dat | inout | Std_Logic | |
PS/2 Keyboard | |||
vga_vsync_n | out | Std_Logic | |
CRTC output signals | |||
vga_hsync_n | out | Std_Logic | |
CRTC output signals | |||
vga_blue | out | std_logic_vector(2 downto 0) | |
CRTC output signals | |||
vga_green | out | std_logic_vector(2 downto 0) | |
CRTC output signals | |||
vga_red | out | std_logic_vector(2 downto 0) | |
CRTC output signals | |||
RS232_RXD | in | Std_Logic | |
RS232 Port | |||
RS232_TXD | out | Std_Logic | |
RS232 Port | |||
RS232_CTS | in | Std_Logic | |
RS232 Port | |||
RS232_RTS | out | Std_Logic | |
RS232 Port | |||
SDRAM_clkfb | in | std_logic | |
SDRAM side | |||
SDRAM_clkout | out | std_logic | |
SDRAM side | |||
SDRAM_CKE | out | std_logic | |
SDRAM side | |||
SDRAM_CS_N | out | std_logic | |
SDRAM side | |||
SDRAM_RAS_N | out | std_logic | |
SDRAM side | |||
SDRAM_CAS_N | out | std_logic | |
SDRAM side | |||
SDRAM_WE_N | out | std_logic | |
SDRAM side | |||
SDRAM_BA | out | std_logic_vector(1 downto 0) | |
SDRAM side | |||
SDRAM_A | out | std_logic_vector(12 downto 0) | |
SDRAM side | |||
SDRAM_D | inout | std_logic_vector(15 downto 0) | |
SDRAM side | |||
SDRAM_DQMH | out | std_logic | |
SDRAM side | |||
SDRAM_DQML | out | std_logic | |
SDRAM side | |||
PB_RD_N | out | std_logic | |
Peripheral I/O bus $E100 - $E1FF | |||
PB_WR_N | out | std_logic | |
Peripheral I/O bus $E100 - $E1FF | |||
PB_A | out | std_logic_vector(4 downto 0) | |
Peripheral I/O bus $E100 - $E1FF | |||
PB_D | inout | std_logic_vector(15 downto 0) | |
Peripheral I/O bus $E100 - $E1FF | |||
ide_dmack_n | out | std_logic | |
IDE Compact Flash $E100 - $E13F | |||
ide_cs0_n | out | std_logic | |
IDE Compact Flash $E100 - $E13F | |||
ide_cs1_n | out | std_logic | |
IDE Compact Flash $E100 - $E13F | |||
ether_cs_n | out | std_logic | |
Ethernet $E140 - $E17F | |||
ether_aen | out | std_logic | |
Ethernet $E140 - $E17F | |||
ether_bhe_n | out | std_logic | |
Ethernet $E140 - $E17F | |||
ether_clk | in | std_logic | |
Ethernet $E140 - $E17F | |||
ether_rdy | in | std_logic | |
Ethernet $E140 - $E17F | |||
ether_irq | in | std_logic | |
Ethernet $E140 - $E17F | |||
slot1_cs_n | out | std_logic | |
Slot 1 $E180 - $E1BF | |||
slot2_cs_n | out | std_logic | |
Slot 2 $E1C0 - $E1FF | |||
FLASH_CE_N | out | std_logic | |
Disable Flash |