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Entity work.sdramCntl

SDRAM controller

Defined in System09_base/sdramcntl.vhd

Author: Dave Vanden Bou
Version: 1.4.0 from 05/17/2005

Architectures

arch

Instantiated in...

work.XSASDRAMCntl (arch)

Libraries and global use clauses

library IEEE
use IEEE.numeric_std.all
use IEEE.std_logic_1164.all
use IEEE.std_logic_unsigned.all
library UNISIM
use WORK.common.all

Generics

FREQ natural := 100_000
IN_PHASE boolean := true
PIPE_EN boolean := false
MAX_NOP natural := 10000
MULTIPLE_ACTIVE_ROWS boolean := false
DATA_WIDTH natural := 16
NROWS natural := 8192
NCOLS natural := 512
HADDR_WIDTH natural := 24
SADDR_WIDTH natural := 13

Ports

clk instd_logic
host side
lock instd_logic
host side
rst instd_logic
host side
rd instd_logic
host side
wr instd_logic
host side
earlyOpBegun outstd_logic
host side
opBegun outstd_logic
host side
rdPending outstd_logic
host side
done outstd_logic
host side
rdDone outstd_logic
host side
hAddr instd_logic_vector(HADDR_WIDTH-1 downto 0)
host side
hDIn instd_logic_vector(DATA_WIDTH-1 downto 0)
host side
hDOut outstd_logic_vector(DATA_WIDTH-1 downto 0)
host side
status outstd_logic_vector(3 downto 0)
host side
cke outstd_logic
SDRAM side
ce_n outstd_logic
SDRAM side
ras_n outstd_logic
SDRAM side
cas_n outstd_logic
SDRAM side
we_n outstd_logic
SDRAM side
ba outstd_logic_vector(1 downto 0)
SDRAM side
sAddr outstd_logic_vector(SADDR_WIDTH-1 downto 0)
SDRAM side
sDIn instd_logic_vector(DATA_WIDTH-1 downto 0)
SDRAM side
sDOut outstd_logic_vector(DATA_WIDTH-1 downto 0)
SDRAM side
sDOutEn outstd_logic
SDRAM side
dqmh outstd_logic
SDRAM side
dqml outstd_logic
SDRAM side

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