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Entity work.spi_master

Synthesizable Serial Peripheral Interface Master

Defined in VHDL/spi-master.vhd

Authors: Hans Huebner and John E. Kent
Version: 0.2 from 16 June 2010

Architectures

rtl


Libraries and global use clauses

library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all

Ports

clk instd_logic
CPU Interface Signals
reset instd_logic
CPU Interface Signals
cs instd_logic
CPU Interface Signals
rw instd_logic
CPU Interface Signals
addr instd_logic_vector(1 downto 0)
CPU Interface Signals
data_in instd_logic_vector(7 downto 0)
CPU Interface Signals
data_out outstd_logic_vector(7 downto 0)
CPU Interface Signals
irq outstd_logic
CPU Interface Signals
spi_miso instd_logic
SPI Interface Signals
spi_mosi outstd_logic
SPI Interface Signals
spi_clk outstd_logic
SPI Interface Signals
spi_cs_n outstd_logic_vector(7 downto 0)
SPI Interface Signals

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