# Compiled by Volker Schatz 2015 # Made available under the ODbL: http://opendatacommons.org/licenses/odbl/ --- - category: Arithmetic core created: Apr 9, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - abdelakher name: 100 status: Empty updated: Apr 10, 2013 wishbone-compliant: 0 - category: Communication controller created: Jan 18, 2012 description: "===== \n Description =====\n\nVerilog implementation of IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS) type 1000BASE-X (1000baseLX and/or 1000baseSX)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dwp name: 1000base-x status: FPGA proven svn-updated: Feb 23, 2012 updated: Sep 16, 2014 wishbone-compliant: 0 - category: Communication controller created: Sep 17, 2009 description: "===== \n Flow Summary Compiled in Quartus 9.0 =====\n\n+-------------------------------------------------------------------------------+\n; Flow Summary ;\n+------------------------------------+------------------------------------------+\n; Flow Status ; Successful - Sun Dec 13 21:49:10 2009 ;\n; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;\n; Revision Name ; Ethernet ;\n; Top-level Entity Name ; test_feedback ;\n; Family ; Cyclone III ;\n; Device ; EP3C40Q240C8 ;\n; Timing Models ; Final ;\n; Met timing requirements ; N/A ;\n; Total logic elements ; 1,026 / 39,600 ( 3 % ) ;\n; Total combinational functions ; 879 / 39,600 ( 2 % ) ;\n; Dedicated logic registers ; 622 / 39,600 ( 2 % ) ;\n; Total registers ; 622 ;\n; Total pins ; 24 / 129 ( 19 % ) ;\n; Total virtual pins ; 0 ;\n; Total memory bits ; 11,992 / 1,161,216 ( 1 % ) ;\n; Embedded Multiplier 9-bit elements ; 0 / 252 ( 0 % ) ;\n; Total PLLs ; 1 / 4 ( 25 % ) ;\n+------------------------------------+------------------------------------------+" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - antiquity name: 10_100m_ethernet-fifo_convertor status: Stable svn-updated: Feb 14, 2013 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Aug 16, 2013 description: "===== \n Description =====\n\nThis is a VHDL code for a datapath processor that performs lots of arithmetic operations.Beside making design for ordinary blocks, we introduced the usage of IP Cores through the usage of divider IP Core. In addition to that, Floating Point Unit \" ADD/SUB, Multiplier, Divider\" is introduced through the usage of IP Cores dedicated for Xilinx FPGA EDA Tools.\n\nThe Architecture Contains the Following Components:\n- 16 bit Data Memory.\nTo read the Operands of the Arithmetic Logic Unit \"ALU\" From it.\n\n- 16 bit Register File.\nTo read the Operands of the Arithmetic Logic Unit \"ALU\" From it.\n\n- 16 bit Register File based FIFO.\nTo write in the Output of the Arithmetic Logic Unit \"ALU\".\n\n- Arithmetic Logic Unit \"ALU\"\nTo perform different Arithmetic and Logic Operations.\n\n- Multiplexers\nTo choose the data input to the ALU either Immediate by the user, memory, register file, or output data from the ALU.\n\n- Integer Divider IP Core\n\n- Floating Point Unit IP Core \"ADD/SUB + Multiplier + Divider\"" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ahmadbassam name: 16-32_processor_datapath status: Empty updated: Aug 16, 2013 wishbone-compliant: 0 - category: Processor created: Mar 25, 2010 description: "===== \n Description =====\n\nOverview\n16,32,64 bit microprocessor - simulator source configurable.\n16 bit fixed instruction length. All instructions conditional.\nup-to 128 instructions. 64 registers.\nRun-time instruction configuration / code obfuscation.\nSimulator software includes macro assembler, console debugger and interpreter using host system calls.\n\n\nPublic domain." language: C/C++ license: custom licensetext: "Terms.\nThis work is governed by Nature's common and immutable laws.\nConsequently the work many be used in any way permissible by Nature." maintainers: - mrdmkg name: 1664 status: Stable svn-updated: Mar 26, 2010 updated: Mar 26, 2010 wishbone-compliant: 0 - category: Other created: Jul 29, 2012 description: "===== \n Description =====\n\nController for 16 character - 2 line LCD displays as used on various Xilinx evaluation boards.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 4-bit LCD data interface \n- One 128bit-wide std_logic_vector input for each diplay line (16x8bit=128). Everything you send to those inputs goes directly to the display.\n \n\n\n \n \n \n\n===== \n Synthesis =====\n\n- Tested on Xilinx ML501 and ML507 \n- Virtex5: 37 flip flops, 228 LUTs, >300MHz" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - stachelsau name: 16x2_lcd_controller status: FPGA proven svn-updated: Nov 28, 2012 updated: Nov 28, 2012 wishbone-compliant: 0 - alternate-download: https://github.com/vishpbharadwaj/2Wss/archive/master.zip category: Arithmetic core created: Nov 28, 2014 description: "===== \n Description =====\n\nA simple 2 way 32-bit data handling in-order superscalar microprocessor with limited op-code and memory designed using VHDL. Its main feature is that it uses one clock and does not use any system bus to read and write data to the memory which increases the performance by decreasing the overall latency of the microprocessor.\n\nCurrently the project files is on GitHub at https://github.com/vishpbharadwaj/2Wss\n \n\n\n \n \n \n\n===== \n License =====\n\nThis project is licensed under LGPL license, version 3.0(LGPL-3.0)\n\nhttp://opensource.org/licenses/LGPL-3.0" homepage: https://github.com/vishpbharadwaj/2Wss language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vishp name: 2-way_superscalar_processor status: Empty updated: Dec 11, 2014 wishbone-compliant: 0 - category: Communication controller created: Nov 24, 2013 description: "===== \n Description =====\n\nThis is a 256-byte depth Serial RS-232 controller, divided into four parts: top-level document, FIFO module, data receive module and data send module." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dreamyy5 name: 256_byte_depth_serial_rs232_controller status: Empty updated: Nov 25, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Apr 11, 2012 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - abhijitav name: 32bit_modbooth_mult status: Empty updated: Apr 16, 2012 wishbone-compliant: 0 - category: Other created: Sep 11, 2005 description: "===== \n Description =====\n\nCVS is currently out of date, update when I get the time (as well as things such as schematics)\n\nCustom built and designed video game system. Also includes hardware interface C routines and code for StarCell XF-1 (the 'release' game). All designs are open source and specification are free to be modified by the community. Specifications are currently for an early 16 bit system.\n \n\n\n \n \n \n\n===== \n Specifications =====\n\n- Graphics accelerator (XESS XSA-50 Spartan II based development board)\n - 320x240 resolution at 64 colors, plus 64 possible intensity field colors\n - 8 MB graphics RAM (approximately 7.5 MB available for user data)\n - Accelerated background and sprite drawing with transparency\n - VGA video generation and output (single and double buffered operation)\n \n - Dual PIC18 Microcontrollers (Main and Sound Processors)\n - 2 x 18F4520 at 50 Mhz (25 MIPS total)\n - 32 KB program memory, 32 KB PCM wavetable memory\n - Capable of tracking over 128 sprites\n\n - Other Hardware\n - Software controlled MP3 player (to be removed)\n - PIC16F628 (serializes controller I/O)\n - ICSP for PIC microcontrollers\n \n\n\n \n \n \n\n===== \n Status =====\n\nHere is a movie of the Impulse running StarCell XF-1\nhttps://netfiles.uiuc.edu/zcheng1/www/impulse.mov\n\nThe hardware unit:\nhttps://netfiles.uiuc.edu/zcheng1/www/impulsehw.jpg\n\nSome screenshots:\nhttps://netfiles.uiuc.edu/zcheng1/www/impulseLogo.jpg\nhttps://netfiles.uiuc.edu/zcheng1/www/starcell.jpg" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - zuofu - cavanaug - esands name: 395_vgs status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Crypto core created: Oct 27, 2006 description: "===== \n Description =====\n\nThis is a VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST.\n\nIn our tests the core has been verified to comply with the http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf (NIST FIPS 46-3) (DES)recommendation.\n\nThis core is provided by:\nhttp://www.coretexsys.com (Coretex Systems, LLC)\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Pipelined architecture.\n\n- VHDL source code.\n\n- Verified in hardware.\n\n- Small footprint (the numbers are for Xilinx Virtex 2 FPGA)\n - 1742 slices,\n - 302 IOBs,\n - no block RAMs,\n - 1 GCLK.\n\n- Fast processing (the numbers assume the pipeline is fully utilized)\n - An output each 17 clocks.\n - Maximum operating frequency 162 MHz.\n - Bandwidth ~581 Mb/s.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- The code is verified, documentation to be added.\n- We are working on an extension to support the Wishbone interface." language: VHDL license: unknown maintainers: - dsocek name: 3des_vhdl status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: May 25, 2010 description: "===== \n Description =====\n\nThis 6502 Project is new to Basic CPU Design(Cisc) before Risc .\nI have made a design as many reference books \n( I read and had reference textbooks as follows\n 1)Verilog HDL,\n 2)Digital Logic,\n 3)Digital System,\n 4)Advanced Digital Design with Verilog HDL,\n 5)Computer Architecture,\n 6)Computer Organization,\n 7)Microprocessors and Microcomputers,\n 8)\xEC\xBB\xB4\xED\x93\xA8\xED\x84\xB0 \xEA\xB5\xAC\xEC\xA1\xB0 \xEC\x84\xA4\xEA\xB3\x84,\n 9)\xEA\xB3\xA0\xEC\x84\xB1\xEB\x8A\xA5 \xEB\xA7\x88\xEC\x9D\xB4\xED\x81\xAC\xEB\xA1\x9C\xED\x94\x84\xEB\xA1\x9C\xEC\x84\xB8\xEC\x84\x9C \xEA\xB5\xAC\xEC\xA1\xB0 \xEB\xB0\x8F \xEC\x84\xA4\xEA\xB3\x84 \xEB\xB0\xA9\xEB\xB2\x95,\n 10)6502,\n 11)8051,\n 12)68000,\n 13)8086,\n 14)80386,\n 15)ARM etc\n ) \nand changed 6502 internal function a little.\nFor example, memory controller is included in my 6502 Cisc ,\nbut will try to follow 6502 compatible instruction Set Architecture.\nNow, I have made 44 instructions of 6502 and tested simulation and verified it.\n\nAdded Instuctions as Followed 2010-05-26\n\n 1)ADC_Imm,\n 2)AND_Imm,\n 3)EOR_Imm,\n 4)ORA_Imm,\n 5)ADC_Abs,\n 6)ASL_ACC,\n 7)LSR_A,\n 8)ROL_ACC,\n 9)ROR_ACC,\n 10)BCC,\n 11)BCS,\n 12)BEQ,\n 13)BNE,\n 14)BPL,\n 15)BVC,\n 16)BVS,\n 17)CLC,\n 18)CLD,\n 19)CLI,\n 20)CLV,\n 21)CMP_Imm,\n 22)CPX_Imm,\n 23)CPY_Imm,\n 24)DEC_AX,\n 25)DEX,\n 26)DEY,\n 27)INC_A,\n 28)INX,\n 29)INY,\n 30)JMP_A,\n 31)LDA_I,\n 32)LDA_A,\n 33)LDX_I,\n 34)NOP_I,\n 35)SED_I,\n 36)SEI_I,\n 37)STA_A,\n 38)STX_A,\n 39)TAX,\n 40)TAY,\n 41)TSX,\n 42)TXA,\n 43)TXS,\n 44)TYA\n\n---------------------------------------------------------------------------------------------------------------------\n2010.05.30 (implemented by today)\n\n1)ADC Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,\n2)AND Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,\n3)ASL,LSR,ROL,ROR: Zero Page,Zero Page X,Absolute,Absolute X,\n4)CMP Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,\n5)CPX Zero Page, Absolute,\n6)CPY Zero Page, Absolute,\n7)DEC Zero Page,Zero Page X,Absolute,\n8)INC Zero Page,Zero Page X,Absolute X,\n9)JMP Indirect\n10)LDA Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y, \n11)PHA,PHP,PLA,PLP,\n12)STA Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,\n13)STX Zero Page,Zero Page Y,\n14)STY Zero Page,Zero Page X,\n \nLater Soon, I will make instructions of 6502 not to be implemented and I will back here.\n---------------------------------------------------------------------------------------------------------------------\n \n \n\n\n \n \n \n\n===== \n 2010-10-06 =====\n\n************************************************************************************\n\nI met problem in verifying CPU Logic.\nbecause, I haven't FPGA evaluation board.\nCan Anybody give FPGA evaluation board to me.\nPlease, help me out !!!!!!!!!!!!!!!!!!!!!!!" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hotak321 name: 6502_verilog_design status: Empty updated: Oct 31, 2010 wishbone-compliant: 0 - category: Processor created: Dec 16, 2003 description: "===== \n Description =====\n\n\n \n\n===== \n Features =====\n\n- feature1\n- feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\n- ...\n- ..." language: VHDL and Verilog license: GPL1 licenselink: https://www.GNU.ORG/licenses/old-licenses/gpl-1.0.html maintainers: - huyvo name: 6502vhdl status: Planning svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Dec 23, 2013 description: "===== \n Description =====\n\nA verilog, vendor independent, no cycle accurate MC6809/HD6309 compatible processor core.\n\nGoals:\n\n- Execute all implemented opcodes\n- Allow asnychronous memories\n- >40 MHz clock\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Most instructions need less clocks than the original.\n- Synthesizes in Lattice Diamond for the MachXO2 requiring ~1260 Slices (two-cycle multiplier) @ >40 MHz, tested, works.\n- Synthesizes in XST for Spartan 2 using a bit less than 1200 Slices (fits in a XC2S100). Testing pending. \n- Synthesizes in XST for Spartan 3 using ~1150 Slices, hw-multiplier. Testing on real FPGA pending.\n- A simple vga text controller has been added, it needs some 70 SLICES and two blocks of ram of 4 kbyte each \n for font and text. It only outputs b/w. It may be removed to make the code smaller.\n\n- All 6809 opcodes have been implemented.\n\n- 6309 opcodes have to be added" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ale500 name: 6809_6309_compatible_core status: FPGA proven svn-updated: Jan 25, 2015 updated: Jul 31, 2014 wishbone-compliant: 0 - category: Processor created: Feb 1, 2007 description: "===== \n MC68HC05 =====\n\nA MC68HC05 clone in VHDL as single file. Twice performance as the original. Multiplication is done in one clock cycle.\n \n\n\n \n \n \n\n===== =====\n\n\n \n\n===== \n 2007.02.11 first version =====\n\ntested with C compiler works OK" language: VHDL license: unknown maintainers: - riedelx name: 68hc05 status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Feb 1, 2007 description: "===== \n MC68HC08 clone =====\n\nA MC68HC08 clone in VHDL as single file. Twice performance as the original. Multiplication is done in one clock cycle. Division in two clock cycles.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2\n \n\n\n \n \n \n\n===== \n 2007.02.08 first version =====\n\ntested with C compiler works OK with interrupts\n2009.07.16 new version, bugfix at opcode 7E mov ,X+,opr8a X post increment fixed" language: VHDL license: unknown maintainers: - riedelx name: 68hc08 status: FPGA proven svn-updated: Jul 16, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/802154crc-mac_crc_16.vhd category: Arithmetic core created: Mar 6, 2013 description: "===== \n Description =====\n\n\n \n\n===== \n References =====" language: VHDL license: GPL3 licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: 802154crc status: Stable svn-updated: Apr 16, 2013 updated: Apr 16, 2013 wishbone-compliant: 0 - category: Communication controller created: Jul 25, 2013 description: "===== \n Description =====\n\nVHDL implementation of the physical layer of the IEEE 802.15.4 standard (TX, RX). \nThe doc/ directory of the repository contains the thesis related to this implementation (ES)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: 802154phycore status: Stable svn-updated: Jan 11, 2015 updated: Jan 11, 2015 wishbone-compliant: 0 - category: Processor created: Sep 25, 2001 description: "===== \n Description =====\n\nThe 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 8-bit CPU optimized for control applications \n- Exstensive Boolean processing (single-bit logic) capabilities \n- 64K Program Memory address space \n- 64K Data Memory address space \n- up to 64K bytes of on-chip Program Memory (ROM)\n- 128 bytes of on-chip Data RAM \n- 4, 8 bit wide, ports outputs (byte or bit addressable)\n- 4, 8 bit wide, ports inputs (byte or bit addressable)\n- Two 16-bit timer/counters \n- 6-source/5-vector interrupt structure with two priority levels priority levels \n \n\n\n \n \n \n\n===== \n Status =====\n\nBasic core is now syntesizable. I test it with XESS XSV board. \nIt have all pheripherals.\n \n\n\n \n \n \n\n===== \n I/O ports =====\n\n- rst (in) reset\n- clk (in) clock\n- int0 (in) external interrupt 0\n- int1 (in) external interrupt 1\n- ea (in) external access\n- iadr_o (out) program rom addres\n- idat_i (in) input from external rom\n- istb_o (out) strobe to program rom\n- iack_i (in) acknowledge from external rom\n- icyc_o (out) cycle output to external rom\n- dat_i (in) exteranal ram input\n- dat_o (out) exteranal ram output\n- adr_o (out) external address\n- we_o (out) write to external ram\n- stb_o (out) strobe\n- ack_i (in) acknowledge\n- cyc_o (out) cycle\n- p0_in, p1_in, p2_in, p3_in (in) port inputs\n- p0_out, p1_out, p2_out, p3_out (out) port outputs\n- rxd\t (in) receive\n- txd\t (out) transmit\n- t0, t1\t (in) t/c external inputs\n \n\n\n \n \n \n\n===== \n IMAGE: interface.jpg =====\n\nFILE: interface.jpg\nDESCRIPTION: interface\n\n \n\n\n \n \n \n\n===== \n Modules =====\n\n- oc8051_acc: accumulator\n- oc8051_alu: aritmetic logic unit\n- oc8051_alu_src1_sel, oc8051_alu_src2_sel, oc8051_alu_src3_sel:\talu source select modules\n- oc8051_b_register: sfr b register\n- oc8051_comp: compare\n- oc8051_cy_select: carry select\n- oc8051_decoder:\t main module, decodes instruction and creates control signals\n- oc8051_defines\n- oc8051_divide: alu submodule for division\n- oc8051_dptr: data pointer register\n- oc8051_ext_addr_sel: external address select\n- oc8051_immediate_sel: innediate data select\n- oc8051_indi_addr:\t indirect address select\n- oc8051_int: interrupt handling module\n- oc8051_multiply: alu submodule for multiplection\n- oc8051_op_select:\t operation select\n- oc8051_pc: program counter\n- oc8051_ports: port inputs and outputs\n- oc8051_psw: program status word\n- oc8051_ram_top: data ram\n- oc8051_ram_rd_sel: select address for reading from ram\n- oc8051_ram_sel: ram output select\n- oc8051_ram_wr_sel: select address for writing to ram\n- oc8051_regX: X wide registers (used to dely signal for 1 clock)\n- oc8051_rom: program rom\n- oc8051_rom_addr_sel: rom address select\n- oc8051_sp: stack pointer\n- oc8051_tc: timer/counter\n- oc8051_timescale\n- oc8051_top: top module\n- oc8051_uart: serial interface\n \n\n\n \n \n \n\n===== \n IMAGE: oc8051.jpg =====\n\nFILE: oc8051.jpg\nDESCRIPTION: design diagram" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - simont - jakas name: 8051 status: Alpha svn-updated: May 5, 2009 updated: Sep 18, 2013 wishbone-compliant: 1 - category: Communication controller created: Sep 11, 2006 description: "===== \n Description =====\n\nThis project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b protocol. 8b/10b is widely used in high speed serial communication standards that need a run-length limited, DC balanced data stream for reliable data transmission and clock recovery. The encoder accepts a parallel 8-bit raw input and generates a parallel 10-bit encoded value based on the data along with a running disparity value. The decoder does the reverse, providing a decoded 8-bit value from the 10-bit encoded input. These cores can be easily incorporated into serializer/deserializer (serdes) communications applications.\n \n\n\n \n \n \n\n===== \n Features: =====\n\nThe two main modules provide a complete VHDL implementation that closely follows the original IBM article \"A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code\" published by A.X. Widmer and P.A. Franaszek and the resulting US patent #4,486,739. For clarity, the VHDL code references the figures and tables of the patent document. Please note that the patent has now expired.\n\nEncoder:\n+ 8b/10b Encoder (file: 8b10b_enc.vhd)\n + Synchronous clocked inputs (latched on each clock rising edge)\n + 8-bit parallel unencoded data input\n + KI input selects data or control encoding\n + Asynchronous active high reset initializes all logic\n + Encoded data output\n + 10-bit parallel encoded output valid 1 clock later\n \nDecoder:\n+ 8b/10b Decoder (file: 8b10b_dec.vhd)\n + Synchronous clocked inputs (latched on each clock rising edge)\n + 10-bit parallel encoded data input\n + Asynchronous active high reset initializes all logic\n + Decoded data, disparity and KO outputs\n + 8-bit parallel unencoded output valid 1 clock later\n\nThere are two Testbench files; one that tests the encoder and a second that drives the decoder with the latched output from the encoder. All 256 data characters, \"D\", and all 12 control characters , \"K\", are sequenced.\n\n- Encoder Testbench (file: enc_8b10b_TB.vhd)\n\n- Combined Testbench (file: endec_8b10b_TB.vhd)\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe two source files and the two testbench files are now complete and have been functionally simulated. The files, and a brief usage document have been uploaded to CVS" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - kboyette name: 8b10b_encdec status: Stable svn-updated: Mar 10, 2009 updated: May 9, 2013 wishbone-compliant: 0 - category: Processor created: Dec 12, 2014 description: "===== \n Description =====\n\nA-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. It differs from the existing (mostly Verilog) Z80 implementations in that it is designed from the ground-up through the schematics and low-level gates. It is a result of a research and tedious reverse-engineering of Z80 at all levels, including micro-photographs of a die.\n\n\n\nProject includes a fully working Sinclair ZX Spectrum implementation based on this CPU.\n\nIt has been described in more details at BaltazarStudios.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n\n Cycle and bus accurate including the correct behavior of nWAIT and nBUSRQ\n All documented and undocumented opcodes, flags and registers, including R, WZ\n Following the actual arcitectural model down to the individual gates and registers for some modules\n Passes ZEXDOC and ZEXLL (except quirky OTIR/LDIR for IX,IY)\n Correct behavior of BIT n,(HL) to expose WZ\n All interrupts modes (IM0,IM1,IM2)\n\nPlaying Mainc Miner on A-Z80 based ZX Spectrum implementation:\n\n\n \n\n\n \n \n \n\n===== \n Documentation =====\n\nA Quick Start document is here: View\n\nComplete User's Guide is here: View\n\nIn addition, project files contain a number of readme's to help you understand, recreate it and/or add A-Z80 to your own project.\n\n\n\n \n\n\n \n \n \n\n===== \n Testbench =====\n\nRTL Simulation\n\nDesign is simulated using ModelSim.\n\n Each module contains a ModelSim project\n Contain individual SystemVerilog test files\n Test wave (*.do) files to quickly set up views\n\nFramework is also developed around the Fuse tests (low-level Z80 CPU) that run\neach Z80 instruction on the ModelSim and automatically compare to the expected Fuse\ntest result files. Mis-matches are flagged.\n\nThere is a \"quick\" sanity test as well as\na much longer comprehensive test.\n\nTop-level Simulation\n\nZMAC assember is used to generate Z80 program test snippets which are then run\nin the simulation and on the actual FPGA hardware. The resulting files should match.\n\nThis level of tests adds UART to the ModelSim and FPGA implementation so the tests can be\nrun and outputs compared.\n\nTests include:\n\n Tests for various complex instructions like DAA, NEG\n Classic \"Hello, World\" application\n Tests for interrupt behavior\n ...and more tests embedded in *.asm test files\n\n\nImplementation\n\nTwo complete and working FPGA designs illustrate implementation and test the A-Z80:\n\n Basic Computer using keyboard and UART to run Z80 tests\n Complete implementation of a Sinclair ZX Spectrum\n\nRunning ZEXDOC and ZEXALL tests on a Basic Computer implementation:\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis design is fully completed, tested and working.\n\nA Cyclone II-based Altera DE1 board implementation used about 20% of its LE's.\n\n\n\nThis implementation is using free Altera tools Quartus II v13.0.1 Web Edition. It also uses Python 2.7 to build some components and tests.\n\nAlthough based on Altera devices, this project can be used with other vendors\nsince each (Quartus-specific) schematic file is pre-compiled into a Verilog file." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gdevic name: a-z80 status: FPGA proven svn-updated: Jan 23, 2015 updated: Dec 24, 2014 wishbone-compliant: 0 - category: Communication controller created: Aug 25, 2011 description: "===== \n Description =====\n\nThe A429 core shall be a single channel transmitter and receiver core for serial communication in airborne applications. It shall support the RTCA ARINC 429 specifications part 1, 2 and 3 and be developed according to RTCA/DO-254 guidelines.\n \n\n\n \n \n \n\n===== \n Definitions / Acronyms =====\n\nARINC - Aeronautical Radio, Inc.\nDAL - Design Assurance Level\nDITS - Digital Information Transfer Systems.\n \n\n\n \n \n \n\n===== \n Referenced Documents =====\n\n* ARINC Specification 429 Part 1 - Functional Description, Electrical Interface, Label Assignments and Word Formats\n* ARINC Specification 429 Part 2 - Discrete Data Standards\n* ARINC Specification 429 Part 3 - File Data Transfer Techniques\n* RTCA/DO-254 - Design Assurance Guidance For Airborne Electronic Hardware\n \n\n\n \n \n \n\n===== \n Applicable Standards =====\n\n- ARINC 429 standard part 1, 2 and 3\n- RTCA/DO-254 ED-80 guidance (DAL criteria TBD)\n \n\n\n \n \n \n\n===== \n Technical Features =====\n\n\n \n\n===== \n Channel Configuration Support =====\n\n- Low speed (LS, 12.5KHz) mode\n- High speed (HS, 100KHz) mode\n- Enable / Disable" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - morpheous name: a429core status: Empty updated: Aug 26, 2011 wishbone-compliant: 0 - category: Communication controller created: Feb 17, 2006 description: "===== \n Description =====\n\nA UART that is compatible with the industry standard 16550D\n\nIncludes wrappers for the Wishbone and AMBA APB busses\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nUses parts from the project (3.17 or later)\n\nSticky parity is not supported \nFIFO's are always enabled\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nDesign is finished \n\n18 Jun 2007\nP. Azkarate's addition of range for integers in Rx, Tx modules\nthis helps when using the Altera tools\n\n12 July 2007\nfix a couple problems found by Matthias Klemm with 5, 6, and 7 bit transfers\n\n14 July 2007\nCorrect FCR bit 3 information (DMA Mode control)\n\n4 Aug 2007\nfix some TOI problems\n\n18 Aug 2007\nadd stopB to sensitivity list in TX module (works the same, but removes warning)\n\n12 Oct 2007\nfixed the bug reports (dated 10/11 Oct 2007)\nTHRE Interrupt will now be generated when trans FIFO is empty and interrupt enable bit changes from disabled to enabled. (note on THRE operation added par 3.3)\n\nThe Receiver Line Status Interrupt is cleared as suggested by Matthias Klemm (note to bug report dated 10/12/07) (mod to this fix 13 oct 2007)\n\n21 July 2008\nmod equ for iBreak_ITR, as suggested by Nathan Z." language: VHDL license: custom licensetext: "Permission is hereby granted, free of charge, to any person obtaining a copy of this \nOpenCores Project and associated documentation (the \"lesser IP\"), to use it in the in \nlarger designs (the \xE2\x80\x9Cgreater IP\xE2\x80\x9D) without restriction, subject to the following conditions: \n1. The copyright notice is retained in the source files, and if they are modified, the \n Revision block must updated to identify the changes. \n2. The lesser IP itself may not be sold, but this restriction is limited to the lesser IP \n itself, not to any greater IP that it may be used in. (Inclusion on a distribution CD \n of, for example, OpenSource Projects is not considered a \xE2\x80\x9Csale\xE2\x80\x9D) \n3. Any greater IP which uses the lesser IP, when distributed as source code or \n synthesized net list, must include in the documentation an acknowledgement of \n using the VHDL 16550 UART core, and the GH VHDL Library (This \n acknowledgement is not required for the distribution of a fuse map or other \n hardware implementation in CPLD, FPGA, ASIC or other form of custom IC). \n4. THE LESSER IP IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY \n KIND, EXPRESS OR IMPLIED. \n5. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE \n LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ARISING \n FROM, OR IN CONNECTION WITH THE USE OF THE LESSER IP. \n" maintainers: - hlefevre name: a_vhd_16550_uart status: Stable svn-updated: Mar 10, 2009 updated: Dec 8, 2010 wishbone-compliant: 0 - category: Other created: Aug 3, 2008 description: "===== \n Description =====\n\na VHDL version of the Intel 8254 timer.\n\nNote: uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.\n\nDesign assumes asynchronous interface/counter clocks \xE2\x80\x93 includes Boolean generics (for each counter) if the same clock is used for interface and counter, or if the clocks are synchronous (different frequency, but with aligned rising edges)\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nUses parts from the gh_vhdl_library project\n \n\n\n \n \n \n\n===== \n Status =====\n\nadded version with AMBA APB interface 16 Aug 2008" language: VHDL license: custom licensetext: "Permission is hereby granted, free of charge, to any person obtaining a copy of this \nOpenCores Project and associated documentation (the \"lesser IP\"), to use it in the in \nlarger designs (the \xE2\x80\x9Cgreater IP\xE2\x80\x9D) without restriction, subject to the following conditions: \n1. The copyright notice is retained in the source files, and if they are modified, the \n Revision block must updated to identify the changes. \n2. The lesser IP itself may not be sold, but this restriction is limited to the lesser IP \n itself, not to any greater IP that it may be used in. (Inclusion on a distribution CD \n of, for example, OpenSource Projects is not considered a \xE2\x80\x9Csale\xE2\x80\x9D) \n3. Any greater IP which uses the lesser IP, when distributed as source code or \n synthesized net list, must include in the documentation an acknowledgement of \n using the VHDL 8254 Timer core, and the GH VHDL Library (This \n acknowledgement is not required for the distribution of a fuse map or other \n hardware implementation in CPLD, FPGA, ASIC or other form of custom IC). \n4. THE LESSER IP IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY \n KIND, EXPRESS OR IMPLIED. \n5. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE \n LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ARISING \n FROM, OR IN CONNECTION WITH THE USE OF THE LESSER IP. \n" maintainers: - hlefevre name: a_vhdl_8253_timer status: Stable svn-updated: Mar 10, 2009 updated: May 14, 2013 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/can_parts.vhd category: Communication controller created: Aug 23, 2007 description: "===== \n Description =====\n\nA (as far as I know) untested VHDL translation of the Verilog Can protocol Controller\n\nTo Download, click at the \"Downloads\" button upper right part of this page\n\nThis project is a translation Igor Mohor's Verilog http://opencores.org/project,can,overview (CAN Protocol Controller)\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe modules have \"_vhdl_\" added to their names, to ease compare simulation with Verilog version (for those with mixed a language simulator)\n \n\n\n \n \n \n\n===== \n Status =====\n\nuse at own risk - have no had time to test/simulate\n\ncheck the Philips SJA1000 data sheet and the http://opencores.org/project,can,overview (Verilog project page) for more information" language: VHDL license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - ghuber name: a_vhdl_can_controller status: Stable svn-updated: Mar 10, 2009 updated: Oct 31, 2014 wishbone-compliant: 0 - category: System controller created: Sep 25, 2001 description: "===== \n Description =====\n\nThis is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio Input/Output. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- AC97 Revision 2.2 Compliant \n- Variable and Fixed Sample Rate Support, up 48 kHz \n- 16, 18 and 20 bit Sample Size Support \n- 6 Channel Surround Sound Support \n- Stereo Input channel Support \n- Mono Microphone Channel Support \n- External DMA Engine Support \n- WISHBONE SoC host Interface \n \n\n\n \n \n \n\n===== \n Status =====\n\n- 8/2/2001 New Directory Structure ! We have agreed on a common directory structure at OpenCores. \n- The AC97 Core is Done ! \n- I will post a message to cores@opencores.org each time I have an update \n \n\n\n \n \n \n\n===== \n Change log =====\n\n- 8/2/2001 RU New Directory Structure Update\n- 19/5/2001 RU First Release\n- 11/5/2001 RU Added link to the spec.\n- 3/5/2001 RU Initial web page \n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi - stekern name: ac97 status: Stable svn-updated: Jul 12, 2011 updated: Jul 11, 2011 wishbone-compliant: 1 - category: Communication controller created: Jul 25, 2013 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - sriramvenkateshan name: ac97spartan6 status: Empty updated: Jul 25, 2013 wishbone-compliant: 0 - category: Prototype board created: Sep 11, 2004 description: "===== \n Description =====\n\nThis is a small board with the low-cost ACEX FPGA with some SRAM and Flash. It is designed as a module for soft-core CPU development. I've used this board as basis for JOP - the Java processor. JOP still fits into the ACEX 1K50.\n\nSee some pictures of the board at: http://www.jopdesign.com/board.jsp\n\nThe schematic and the PCB layout is provided under GPL.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Altera ACEX 1K50TC144-3 FPGA\n- Voltage regulators (3V3, 2V5)\n- Crystal clock (20 MHz)\n- 512KB Flash (for FPGA configuration and program)\n- 128KB Ram\n- Byteblaster port\n- Watchdog with LED\n- EPM7032 PLD to load FPGA from flash (on watchdog reset)\n- Serial interface (MAX323A)\n- 56 general IO pins\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Board is final\n- Used in several projects\n- Single page schematic can be used with the free version of Eagle: http://www.cadsoft.de/\n \n\n\n \n \n \n\n===== \n FILE: jopcore.pdf =====\n\nFILE: jopcore.pdf\nDESCRIPTION: Schematic\n- abc" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - martin name: acxbrd status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Feb 26, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: unknown maintainers: [] name: ad_hard_core_s3esk status: Empty updated: Mar 1, 2011 wishbone-compliant: 0 - category: DSP core created: Apr 24, 2006 description: "===== \n Adaptive LMS Equalizer =====\n\nIn communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.\nand more sevear is such distortion is random.\n\nTo handle this, multipath affected channels require Equalizers at receaver end.\nsuch equalizer uses different learning Algorithms for identifying channels continuously.\n\nThis project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton\n\nIt uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 5 TAP PIPELINED LMS ADAPTIVE FILTER CORE\n- 8 bit data\n- 3TAP Constant Channel Filter\n- Spartan II compitible\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n-initial Release" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - digish name: adaptive_lms_equalizer status: Design done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Jul 25, 2008 description: "===== \n Description =====\n\nThis is a feed forward receiver for an ADAT lightpipe optical datastream. This type of multichannel audio connection is widely used in professional digital recording studios. It consists of eight 24 bit wide audio words, at a sample rate (wordclock) of 32kHz, 44,1kHz or 48kHz. It can double the sample rate at the cost of half the number of channels, this is called S-MUX (not supported yet). There are 4 user bits to carry extra data (MIDI, S-MUX indicator, timecode and spare). ADAT streams are encoded with NRZI coding, meaning a change in the ADAT stream is a \"1\", with no change a \"0\" is sent.\n\nThe receiver needs one extra input besides the ADAT stream: Any stable clock (m_clk) between 80MHz and 160MHz should work.\n\nOne instance is used: a 12x8 multiplier with the 12 MSB's output. Compiled for an Altera Cyclone II the design uses 682LE's and 2 embedded 9 bit multipliers.\n\nI'm glad to announce that I finally had the opportunity to test and optimize this design, and it's now FPGA proven. I also slimmed down the design to 682LE's. If you are using this design in a larger project, and have no use for a bus-like interface, the registers can be implemented in M4K blocks in the Altera Cyclone II, and it uses even less LE's (I think in the 250-300 range).\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feed forward: other than a non-related clock signal, only the ADAT data stream is required.\n- outputs the 8 audio words on a databus.\n- regenerates the wordclock from the received stream.\n- outputs the user bits as seperate pins.\n- adapts to speed changes.\n- should (!) lock on to the stream in a matter of seconds.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- VHDL code written\n- testbench completed\n- simulation of design\n- Tried the design in an FPGA.\n\nTodo:\n- comment the code.\n \n\n\n \n \n \n\n===== \n IMAGE: thumb_waves1.jpg =====\n\nFILE: thumb_waves1.jpg\nDESCRIPTION: Some ADAT frames in simulation\n\n \n\n\n \n \n \n\n===== \n IMAGE: thumb_waves2.jpg =====\n\nFILE: thumb_waves2.jpg\nDESCRIPTION: Frame delimiter closeup" language: VHDL license: unknown maintainers: - dweil name: adat_optical_feed_forward_receiver status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Other created: May 18, 2009 description: "===== \n Description =====\n\nThe Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a System-on-Chip, then perform source-level debugging of that code. In particular, target systems using the OpenRISC 1200 processor and a WishBone bus are currently supported by the Advanced Debug Interface.\n\nThis system includes four components. The first component, the \"adv_dbg_if\" core, is a hardware core designed to interface directly to the OR1200 CPU and a WishBone bus, controlling the CPU and reading and writing data to both the CPU registers and memory addresses on the bus. \n\nThe second component is a JTAG TAP; this relatively small hardware core acts as a connection between the adv_dbg_if core and the external pins of the target chip (ASIC or FPGA). Four different versions of the JTAG TAP core are included, targeting four different types of system.\n\nThe third component is a software program called \"adv_jtag_bridge,\" which is designed to run on the user's workstation. This component acts as a communication bridge between a source-level debugger program (GDB, not included in this package) and the JTAG TAP. Communication is performed via a JTAG cable, which adv_jtag_bridge drives.\n\nThe fourth important component of the system is the documentation. This suite includes a top-level document explaining the workings of the debug system and each of its components, including information to help the user choose the best components for his or her target system, and information on how to connect them. Documents describing each component individually are included (under doc/ in each component's subdirectory) as secondary material.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\nSupports multi-device JTAG chains. This configuration is often found on Xilinx reference hardware, and was not supported by previous debug hardware.\n\nSupports Altera sld_virtual_jtag interface. This allows the user to connect to the advanced debug unit via the same JTAG port which is used to program the FPGA, similar to the way the Altera Nios II processor debugger works.\n\nSupports Xilinx BSCAN_* virtual JTAG interface. This is the Xilinx equivalent of the Altera sld_virtual_jtag interface, it allows a user to connect to the advanced debug unit through the main FPGA JTAG connection.\n\nSupport for Actel UJTAG TAP interface. This is the Actel equivalent of the Altera sld_virtual_jtag or the Xilinx BSCAN TAP, it allows a user to connect to the advanced debug unit through the main FPGA JTAG connection.\n\nCables supported: Altera USB-Blaster, Xilinx Platform Cable USB (DLC9 and DLC10), various FT2232-based cables, various FT245-based cables, Xilinx Parallel Cable III (IV in compatibility mode), Altera ByteBlaster II, XESS parallel interface\n\nIncludes full support for OR1200 hardware watchpoints/breakpoints and counters, including a GUI client program \"AdvancedWatchpointControl\"\n\n\nIncludes a \"JTAG serial port,\" a device which looks like a UART on the SoC WishBone bus, but which transfers data via JTAG to the jtag bridge program, where it can be viewed via telnet. This allows users to get logging from their programs without the need for a dedicated, external RS-232 link.\n\nIncludes support for simulator connection. Programs can now be downloaded and executed on simulated hardware (in ModelSim, Icarus, etc.). Communication can be done via the filesystem, or via network sockets if VPI is supported by the simulator.\n\nIncludes overview document explaining the complete debug system, component selection, and component interconnections. No more guessing which version of the debug unit works with which JTAG core or GDB interface program. All components used in the debug system are bundled together.\n\nJTAG chain auto-enumeration and BSDL parsing keeps command-line options to a minimum when running the adv_jtag_bridge program. Even complex systems can be debugged using only two command-line parameters.\n\nUses less hardware than older \"dbg_interface\" core: 48% less logic, 28% fewer registers under Altera Quartus v7.0.\n\nAdvanced JTAG Bridge program uses RSP to communicate with GDB, making it compatible with GDB 6.8.\n\nAdvanced JTAG Bridge program can be compiled to support the legacy debug hardware unit (dbg_interface). This allows legacy hardware systems to be debugged using GDB 6.8 via RSP.\n\nModular software design allows new JTAG cables to be easily added.\n\nModular hardware design allows new busses and processors to be supported.\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe adv_dbg_if core, all of the JTAG cores, the JTAG serial port, and the adv_jtag_bridge software program have all been tested and shown to work in both ModelSim simulation and in FPGA hardware (Altera Cyclone II, Xilinx Spartan 3, Xilinx Virtex4). Drivers for the Altera USB-Blaster and the FTDI FT245 have been tested by the developer. The FT2232 and XPC3 drivers have also been reported to work by users, as has the ByteBlasterII driver. Bit-bang support for the Xilinx Platform Cable USB (DLC9) was developed and tested by the author, but this has been superseded by a driver with high-speed support, which has been minimally tested. The USB-Blaster is currently the fastest-performing cable tested by the developer, with a transfer rate of around 88k/sec. Support for the parallel 'XESS' cable was taken from the older 'jp2' program, and has not been tested in its new environment.\n\n\n\nHardware watchpoint support has been tested and is known to work using the OR1200v1 and the patch distributed with the Advanced Debug System. Watchpoint counters are also tested and known to work using this patch. The OR1200v1, v2, and v3 as found in SVN (as of this writing) are known NOT to work.\n\n\n\n\nThe 3.0.0 release of the Advanced Debug Interface was tested with minsoc v0.9. Release 2.5.0 was tested with the or1200 core as downloaded on 5/14/2008, the wb_conbus WishBone bus core as downloaded on 3/16/2008, and or32-uclinux-gdb version 6.8 (with one added patch, listed in \"Known Bugs\").\n\n\n\nTested ADI configurations:\n\nXilinx Virtex-4, access via Xilinx Platform Cable USB (DLC9) and BSCAN_VIRTEX4 virtual JTAG TAP\nXilinx Spartan 3A, access via Xilinx Parallel cable III and BSCAN_SPARTAN3A virtual JTAG TAP\nXilinx Spartan 3A, access via Xilinx Parallel cable IV (in XPCIII compatibility mode) and BSCAN_SPARTAN3A virtual JTAG TAP\nXilinx Spartan 3A, access via Xilinx Platform Cable USB (DLC9) and BSCAN_SPARTAN3A virtual JTAG TAP\nAltera Cyclone II, access via Altera USB-Blaster cable and stand-alone JTAG TAP\nAltera Cyclone II, access via USB-Blaster clone and altera_virtual_jtag TAP (usbblaster and ft245 drivers)\nAltera Cyclone IV, access via USB-Blaster clone and altera_virtual_jtag TAP (usbblaster and ft245 drivers)\nAltera Stratix II, access via USB-Blaster (with FT245 driver) and altera_virtual_jtag TAP\nActel A3P1000, access via USB-Blaster clone and actel_ujtag TAP (usbblaster and ft245 drivers)\nSimulation in ModelSim, File IO communication\nSimulation in ModelSim, network sockets (via VPI) connection\nSimulation in Icarus, VPI connection (\"minsoc\" project)\n\n\n\n\nUntested features:\n\nSome Xilinx BSCAN devices\nXESS parallel interface support\nThe boundary scan cell HDL included with the \"jtag\" TAP has not been tested with the modified TAP\n\n \n\n\n \n \n \n\n===== \n Dependencies =====\n\nThe adv_jtag_bridge software relies on libUSB to drive the USB-Blaster and XPC-USB/DLC9 cables. This Free/Open Source library can be downloaded from http://libusb.wiki.sourceforge.net. Note that adv_jtag_bridge uses the older v0.1 libUSB interface; as of December 2008, libUSB changed its interface to version 1.0. Be sure to install the \"compatibility layer\" of libUSB on your system if you use Linux; the libUSB-Win32 version still used the v0.1 interface as of Dec. 2008.\n\nSupport for FT2232-based cables depends on libftdi. This LGPL library may be found at http://www.intra2net.com/en/developer/libftdi/. Adv_jtag_bridge version 1.2.0 was tested with libftdi version 0.16, this is the last time the author had access to a DLC9 cable. Release 3.0.0 is known to compile against libftdi version 0.19. Note that in some Linux distributions (Ubuntu 10.04 for example) you must install both the libftdi and the libftdi-dev packages from your OS provider's software repository.\n \n\n\n \n \n \n\n===== \n To Do =====\n\n\nTest other BSCAN_x interfaces\nPort adv_jtag_bridge to use libUSB v1.0\nPort the adv_jtag_bridge cable drivers and BSDL parsing to use the UrJTAG project, once it is available as a library\nMore testing and verification is always needed, improved testbenches, etc!\n\n \n\n\n \n \n \n\n===== \n Known Bugs =====\n\n\nGDB 6.8 has a bug which prevents it from working when no stack frame is present (such as at start-up on a bare-metal debugger, as we are doing here). A simple patch applied to GDB 6.8 will work around the problem (a general solution is not yet available). This patch can be found in the Patches/GDB6.8/ directory.\n\nThe OR1200v1 hardware breakpoint implementation is broken. A patch which fixes the support is distributed with the Advanced Debug System in the Patches/OR1200v1/ directory. Support for other versions of the OR1200 is not yet available.\nThere is a bug in the OR1200v3 which affects the debug unit. This version will not pass the adv_jtag_bridge self-test, but will instead lock the processor (and debugger). The bug also manifests itself during single-stepping.\nGDB versions 7.0 and 7.2 have bugs which prevent them from working correctly with the Advanced Debug System (and probably other debug units and well).\n\n\n \n\n\n \n \n \n\n===== \n Changelog =====\n\n\n5/18/2009 Version 1.0 released (OpenCores SVN tag ADS_RELEASE_1_0_0)\n6/16/2009 Version 1.1 released (tag ADS_RELEASE_1_1_0). Added support for the legacy debug unit (dbg_interface) to adv_jtag_bridge. Changed TDI/TDO signal names in TAP cores for clarity. Updated docs.\n7/23/2009 Version 1.2 released (tag ADS_RELEASE_1_2_0). Added support for FT2232-based JTAG cables (thanks to Jose Villar). Fixed critical bugs in XPC3 and XESS parallel cable drivers (thanks to Raul Fajardo).\n1/17/2010 Version 2.0. Changes to the communication protocol, allowing an order-of-magnitude speed improvement for USB-Blaster cables. Added alternate USB-Blaster cable driver as compile-time option (thanks to Xianfeng Zeng). Fixed BSDL parsing directory bug. Other minor improvements. Updated docs to reflect new hi-speed mode.\n3/31/2010 Version 2.5. Added actel_ujtag core. Added JTAG Serial Port feature. More speed improvements for USB cables.\n12/29/2011 Version 3.0. Autotools support, thanks to R. Diez. High-speed DLC9 support, thanks to Raul Fajardo. Non-priviledged parallel port access, also thanks to Raul Fajardo. Altera ByteBlasterII support. Bugfixes and minor speed improvements." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - nyawn name: adv_debug_sys status: FPGA proven svn-updated: Jan 21, 2012 updated: Jul 4, 2013 wishbone-compliant: 1 - category: Processor created: Aug 7, 2003 description: "===== \n Description =====\n\nThe AE18 is a clean room implementation of the Microchip PIC18 series CPU core using information from the PIC18C documentation from their website. It is cycle and instruction compatible to the PIC18 for most software commands. \n\nThis is just a CPU core that is capable of moving and manipulating data to and from memory. It does not have any peripherals nor interrupt controllers although support for both high and low level interrupts are provided. Any peripherals and their respective registers should be mapped to the data memory space. It has a separate instruction and data bus.\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Harvard architecture with separate instruction and data bus.\n- Wishbone compatible bus.\n- Full 24bits instruction memory capable.\n- Full 16bits data memory capable.\n- Custom user peripheral/interrupt controllers.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested in software simulation running C code compiled using SDCC 2.5 and GPUTILS 0.13.4.\n- Simulated using both Icarus Verilog 0.8.2 and GPLCVER 2.11a.\n- Simulation results verified against GPSIM 0.22.0.\n- Synthesised for 25k gates @ 50 MHz on a Spartan3 with ISE.\n- This initial revision of the design can definitely be further optimised.\n- Drop me an email to inform me if you use this core in any of your projects.\n \n\n\n \n \n \n\n===== \n Links =====\n\n- http://gputils.sourceforge.net (GPUTILS - GNU PIC assembler and linker).\n- http://sdcc.sourceforge.net (SDCC - PIC18 C compiler).\n- http://www.dattalo.com/gnupic/gpsim.html (GPSIM - PIC Simulator)\n- http://ww1.microchip.com/downloads/en/DeviceDoc/33023a.pdf (PIC18C complete reference manual).\n- http://en.wikipedia.org/wiki/PIC18 (PIC18 wikipedia entry).\n- http://www.ece.ncsu.edu/asic/hw/Project04.pdf (North Carolina State University class project).\n\n \n\n\n \n \n \n\n===== \n Notes =====\n\nPlease test it extensively before using. Although every care has been taken to test this core, it is supplied WITHOUT WARRANTY of any kind. If you do find bugs, please feel free to report it using the bug tracker. In order to facilitate debugging, please include any code sequence that is necessary to reproduce the bug. Also, any other information that is necessary will be greatly appreciated." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - sybreon name: ae18 status: Design done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Processor created: Aug 10, 2004 description: "===== \n Features =====\n\n- Non-architecture compatible with MB.\n - Harvard architecture with separate instruction and data bus.\n - Provides GET/PUT implementation on a FSL bus.\n - Uses WISHBONE instead of LMB/OPB bus protocol for I/O.\n - Fully pipelined for single cycle execution of all instructions.\n - Single cycle barrel shifter and multiplier.\n- Instruction compatible except for optional instructions not used in GCC.\n - Missing: WIC,WDC,IDIV,IDIVU\n - Optional parameterised multiplier and barrel shifter.\n - Software division\n - Software floating-point\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested in software simulation:\n - Simulated using both Icarus Verilog 0.8.5 and GPLCVER 2.11a.\n - C code compiled with GCC 3.4.1 ( Xilinx EDK 8.1.01 Build EDK_I.19.4 061107).\n - Fibonacci numbers (integer)\n - Euclidean algorithm (modulo)\n - Newton-Rhapson method (floating point)\n- Some ISE synthesis results:\n - 38k gates @ 88 MHz on Virtex4 (with hardware multiplier and barrel shifter).\n - 38k gates @ 136 MHz on Virtex4 (with barrel shifter).\n- Tested and independently proven in FPGA hardware.\n- Drop me an email to inform me if you use this core in any of your projects.\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe aeMB is a clean room implementation of the EDK3.2 compatible Microblaze core using information from the Internet. It is cycle and instruction compatible to the MB for most software commands. It is not meant as a drop in replacement for the Microblaze as it is not 100% architecturally compatible. \n\nThis is a CPU core that is capable of moving and manipulating data to and from memory. It does not have any peripherals nor interrupt controllers although support for external interrupts is provided. Any peripherals and their respective registers could be mapped to the data memory or FSL memory space. It has a separate instruction, data and FSL buses.\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Links =====\n\n- http://www.petalogix.com/resources/downloads/mb-gcc (Microblaze GCC Toolchain)\n- http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf (Microblaze Reference Guide PDF)\n- http://en.wikipedia.org/wiki/MicroBlaze (Microblaze Wikipedia Entry)\n- http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux (Microblaze uClinux Project)\n \n\n\n \n \n \n\n===== \n Notes =====\n\nPlease test it extensively before using. Although every care has been taken to test this core, it is supplied WITHOUT WARRANTY of any kind. If you do find bugs, please feel free to report it using the bug tracker. In order to facilitate debugging, please include any code sequence that is necessary to reproduce the bug. Also, any other information that is necessary will be greatly appreciated." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - sybreon name: aemb status: FPGA proven svn-updated: Jul 25, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Crypto core created: Sep 7, 2013 description: "===== \n Description =====\n\nThe AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts data to an unintelligible form called ciphertext .Here the AES algorithm is capable of using cryptographic keys of 128bit to do this conversion .This module is optimized for speed as it pipeline hardware to perform repeated sequence called round. This module synthesized on Xilinx virtex 6 6vcx240tff784-2 board using ISE. Fuctional and gate level simulation were done using AES validation suite (AESVS) vectors \n \n\n\n \n \n \n\n===== \n Features =====\n\n-128 bit data\n-128 bit Cipher Key\n-One Clock domain\n-Optimized for speed\n-Pipelined architecture\n-Generic RTL (vendor independent)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Amr_Salah name: aes-128_pipelined_encryption status: FPGA proven svn-updated: Sep 9, 2013 updated: Apr 3, 2015 wishbone-compliant: 0 - category: Crypto core created: Oct 14, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: unknown maintainers: - tariq786 name: aes-encryption status: ASIC and FPGA proven svn-updated: Jan 2, 2013 updated: Nov 19, 2010 wishbone-compliant: 0 - alternate-download: https://github.com/AessentTechnology/aes220/archive/master.zip category: Prototype board created: Aug 1, 2013 description: "===== \n Description =====\n\nThe aes220 is a High-Speed USB 2.0 FPGA based on the Cypress FX2 micro-controller and Xilinx Spartan3AN (XC3S200AN or XC3S400AN) FPGA. The 'N' denomination of the Spartan device means it includes 4Mb of flash memory to retain 2 configuration bit streams or user data. The board also offers 16MB of SDRAM and 72 GPIOs. Power is provided by the USB cable or by an external 5V supply. The mini-module is only 42x61mm making it way smaller than a credit card.\n\nThe device is programmed through the USB port and does not require any external programmer, although a JTAG port is available. Once programmed communication with the FPGA happens through the USB port and is rendered easy thanks to the open-source libraries provided in C/C++ and C# on the PC side and in VHDL on the FPGA side. The API works on Windows and Linux platforms (including the Beaglebone Black) and does not require any prior knowledge of USB communication. Source code is available in the git repository (see link below). The board is also compatible with the FPGALink library.\n \n\n\n \n \n \n\n===== \n Specifications =====\n\n\nCypress EZ-USB FX2LPTM micro-controller (CY7C68013A)\n16KB EEPROM for micro-controller program\n24MHz crystal oscillator\nXilinx Spartan3AN FPGA (aes220a: XC3S200AN, aes 220b: XC3S400AB)\n4Mb SPI FLASH memory\n288Kb RAM\n4 Digital Clock Managers (each including a Digital Frequency Synthesizer)\n128Mb 100Mhz SDRAM\n1.2V, 1.8V and 2x3.3V on-board buck and LDO regulators\n72 general purpose 3 state pins, of which 16 GCLK inputs\nI2C bus interface pins (SDA/SCL)\n5 user LEDs\n2 user switches\nJTAG 14 pin connector footprint\nPowered from USB port or external 5V supply\nSmall size at 42x61mm\n\n \n\n\n \n \n \n\n===== \n Images =====\n\n\n aes220 High-Speed USB FPGA mini-module shown here on top of a credit card\n \n \n\n aes220 with aes2200 ADC/DAC daughter board\n \n\n\n \n \n \n\n===== \n Documentation =====\n\naes220 High-Speed USB FPGA Data Sheet (pdf)\naes220 High-Speed USB FPGA User Manual (pdf)\n\n\n \n\n\n \n \n \n\n===== \n External Links =====\n\naes220 product page\naes220 git repository\nFPGALink project" homepage: https://github.com/AessentTechnology/aes220 language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ssaury name: aes220 status: Empty updated: Feb 23, 2014 wishbone-compliant: 0 - category: Communication controller created: Apr 19, 2009 description: "===== \n Features =====\n\n\n AES3 / SPDIF compatible receiver\n locks to any sample rate from 20kHz to 100kHz with 50MHz master clock and reg_width = 5\n locks to any sample rate from 20kHz to 200kHz with 100MHz master clock and reg_width = 6\n very compact (only 39 macrocells with reg_width = 5)\n\n \n\n\n \n \n \n\n===== \n Newss =====\n\n\n2009/08/31 - Fixed previous fix - removed redundant bbbr_shift_reg_proc.\n2009/08/30 - Fixed bug preventing the receiver to lock on input signal in case that shortest pulse length was longer then master clock/2^reg_width. Also simple testbench has been uploaded to SVN.\nDesign is finally done and FPGA proven. Fundamental changes (instead of measuring shortest pulse length, feedback is used for locking on the input signal) were made in last revision, so please update your copies.\n \n\n\n \n \n \n\n===== \n Overview =====\n\nAES3 / SPDIF receiver is simple, minimalistic but powerful core which decodes biphase mark coded AES3 compatible signal and retransmitts it in I2S-like format. Audio words are coded in 2's complement format, however, in contrast to I2S, they are LSb and not MSb aligned and all auxiliary bits of AES3 are left unchanged and transmitted together with audio word. There is even some mess in first four bits of each word as result of preamble detection. Nevertheless, this core can be implemented on XC9572XL-5 with only 43 macrocells utilization and fmax around 100MHz while capable of receiving AES3 at fs = 96kHz with clk at 50MHz." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - nohous name: aes3rx status: FPGA proven svn-updated: Aug 31, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Crypto core created: May 10, 2006 description: "===== \n Consecutive AES core =====\n\nDescription of project..\n \n\n\n \n \n \n\n===== \n Features =====\n\n- AES encoder\n - 128/192/256 bit\n- AES decoder\n - 128/192/256 bit\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Key Expansion added\n- Encoder added\n- Decoder added\n- Documentation added" language: VHDL license: unknown maintainers: - furia name: aes_128_192_256 status: Stable svn-updated: Mar 10, 2009 updated: Nov 24, 2011 wishbone-compliant: 0 - category: Crypto core created: Jun 24, 2013 description: "===== \n Description =====\n\nFour stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely, encrypting up to 4.25 Gbits data per second (0.361Ghz* 4 stage pipe * 128 bits parallel / 44 cycles a block)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - feketebv name: aes_all_keylength status: Alpha svn-updated: Sep 15, 2014 updated: Aug 10, 2014 wishbone-compliant: 0 - category: Crypto core created: Jul 3, 2013 description: "===== \n Description =====\n\nThe AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.\n\nTraditionally crypto IPs are verified with C/C++ model, but that requires you to either interface with an external language in your HDL testbench, or to modify your C/C++ model to export test vectors in a format acceptable by your testbench. Either way is time consuming. A native SystemVerilog model elimates the need to interface with an external language model. You can include this model in your testbench and drive it in your simulation like a C model.\n\nBoth encryption and decryption are now supported.\n\nThe model itself is an un-timed SystemVerilog class which implements the encryption and decryption algorithm described in the FIPS-197 specification. A set of tasks (methods) is provided for users to drive the model to go through the encryption and decryption algorithm to generate known good results (either per round intermediate results or final plaintext/ciphertext). It can be included in a testbench as golden model or test vector generator." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - schengopencores name: aes_beh_model status: Design done svn-updated: Aug 12, 2013 updated: Aug 12, 2013 wishbone-compliant: 0 - category: Crypto core created: Nov 8, 2002 description: "===== \n Description =====\n\nSimple AES (Rijndael) IP Core.\n\nI have tried to balance this implementation and to trade off size and performance. The goal was to be able to fit in to a low cost Xilinx Spartan series FPGA and still be as fast as possible.\nAs one can see from the implementation results below, this goal has been achieved !\n\nOther Implementations of this standard with different key sizes (192 & 256 bit) and performance attributes (like a fully pipelined ultra-high-speed version) are commercially available from ASICS.ws.\n\nEven though no official testing has been performed we believe that this core is fully complies to FIPS-197 (pdf).\n\nFor more information see the core documentation.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\n16 byte block size\n16 byte key size\nseparate cipher (encrypt) block\nseparate inverted cipher (decrypt) block\nincorporated key expansion module\nwritten in verilog\n\n\n\nSample Synthesis Results for the Cipher Block\n\n\n\n \n Technology\n\n \n Size/Area\n\n \n Speed/Performance\n\n\t\n Xilinx Spartan IIe XS2V200-6\n\n \n 3497 LUTs (74 %),1026 Regs. (21 %)\n\n \n 101 Mhz (1.08 Gbits/sec)\n\n\t\n UMC 0.18u Std. Cell\n\n \n 38K Gates\n\n \n 265 Mhz (2.82 Gbits/sec)\n \n\n\nSample Synthesis Results for the Inverse Cipher Block\n\n\n \n Technology\n\n \n Size/Area\n\n \n Speed/Performance\n\n\t\n Xilinx Spartan IIe XS2V200-6\n\n \n 3393 LUTs (72 %),883 Regs. (18 %)\n\n \n 85 Mhz (906 Mbits/sec)\n\n\t\n UMC 0.18u Std. Cell\n\n \n 50K Gates\n\n \n 235 Mhz (2.5 Gbits/sec)\n \n \n\n\n \n \n \n\n===== \n Status =====\n\n- Nov 12, 2002 Found a bunch of test vectors on the NIST site, added them today to the testbench. Added missing timescale.v file.\n- I could use some \"official\" testvectors. If you know were to get them or have any, please contact the author.\n- This core is done. Initial Release: Nov. 9, 2002\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: aes_core status: Stable svn-updated: Mar 10, 2009 updated: Oct 23, 2013 wishbone-compliant: 0 - category: Crypto core created: Dec 7, 2004 description: "===== \n Description =====\n\nThis Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197.\nThis AES core is developed for a key size of 128 bits and operates in ECB mode. \nThe project contains a synthesizable RTL along with a Test Bench set up to verify the Core with test vectors as described in the FIPS document.\n \n\n\n \n \n \n\n===== \n General Features =====\n\nInput and Key size of 128 bits.\nOperation in ECB mode.\nPerformance adheres to FIPS-197.\nCore with high speed and low latency.\nRTL and TB in VHDL.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nCore verified in simulation and uploaded." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hemanth name: aes_crypto_core status: Stable svn-updated: Mar 10, 2009 updated: Mar 26, 2014 wishbone-compliant: 0 - category: Crypto core created: Jan 30, 2014 description: "===== \n Description =====\n\nWhile there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one.\n\nThe AES Decryption Core for FPGA implements the decryption portion of the AES (a.k.a. Rijndael) algorithm described in the FIPS-197 specification. Key lengths of 128 / 192 / 256 bits are supported, each with a separate instantiation wrapper. Since the core is designed to take advantage of LUT6 based FPGA architecture, it packs very well in those devices. The result is a peak throughput of over 3Gbps for 256-bit key, yet occupies about 2000 LUTs only. The core has been verified with random test vectors as well as selected test vectors in FIPS-197, SP-800a, and AESAVS specifications. Self checking testbenches are included.\nThe core has been tested on Xilinx KC705 development board.\n\nBenchmark numbers are shown below.\nXilinx Kintex xc7k325tffg900-3 \n\n\n \n128-bit\n192-bit\n256-bit\n\n\nLUT\n1865\n2350\n2033\n\n\nFF\n310\n443\n448\n\n\nBRAM\n0\n0\n0\n\n\nLatency w/ key switching\n22clk\n26clk\n30clk\n\n\nLatency w/o key switching\n11clk\n13clk\n15clk\n\n\nFmax\n369MHz\n361MHz\n365MHz\n\n\nPeak throughput\n4.293Gbps\n3.554Gbps\n3.114Gbps\n\n\n\n\nXilinx Kintex UltraScale xcku040-ffva1156-2-e\n\n\n \n128-bit\n192-bit\n256-bit\n\n\nLUT\n1791\n2269\n1969\n\n\nFF\n299\n441\n438\n\n\nBRAM\n0\n0\n0\n\n\nLatency w/ key switching\n22clk\n26clk\n30clk\n\n\nLatency w/o key switching\n11clk\n13clk\n15clk\n\n\nFmax\n380MHz\n364MHz\n375MHz\n\n\nPeak throughput\n4.421Gbps\n3.584Gbps\n3.200Gbps" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - schengopencores name: aes_decrypt_fpga status: FPGA proven svn-updated: May 7, 2015 updated: May 7, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Aug 19, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - issei name: aes_encryption_decryption status: Empty updated: Jan 31, 2014 wishbone-compliant: 0 - category: Crypto core created: Mar 3, 2010 description: "===== \n Description =====\n\nThe High Throughput Low Area AES IP core implements the Rijndael encryption & decryption algorithm used in the AES standard. The standalone core implements the basic ECB mode described in publication 800-38A by NIST. Other modes can be easily implemented using the core. \nThe core implements both key expansion, required each time the key is changed (also after reset or power-up), and encryption/decryption algorithms. The core supports all three key lengths: 128, 192 & 256 bits, selected by an input signal. Encryption or decryption modes of operation are also selected on the fly using an input signal. \nThe core can achieve data rates of about 880Mbps with 256 bits key length, 1Gbps with 192 bits key length and 1.2Gbps with 128 bits key length when operated at a clock of 100MHz. \nTest bench for basic simulation is provided to demonstrate the core functionality and interfaces. An additional test bench is supplied for verification of the core using the KAT test vectors files for ECB mode. \n\nBlock Diagram\nSimplified core block diagram: \n\n\n\nFor detailed information download the Core Specifications 0.2 document.\n\nSynthesis Results\n\n\n Manufacturer \n Family \n Device \n Device Utilization \n Elements Utilization \n Fmax \n\n\n Xilinx \n Spartan 3 \n xc3s1500-4fg456 \n 23% \n 3,110 Slices \n >100MHz \n\n\n Xilinx \n Virtex 5 \n xc5vlx30-3ff324 \n 45% \n 1,408 Slices \n >135MHz \n\n\n Altera \n Cyclone III \n ep3c10f256c6 \n 44% \n 4,657 LEs \n >110MHz \n\n\n Altera \n Arria II GX \n ep2agx45cu17i3 \n 13% \n 1,806 Registers3,247 ALUTs \n >145MHz" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - motilito - rainrhythm name: aes_highthroughput_lowarea status: FPGA proven svn-updated: May 6, 2013 updated: Apr 1, 2012 wishbone-compliant: 0 - category: Crypto core created: Mar 22, 2010 description: "===== \n Description =====\n\nThis is a fully pipelined implementation of the AES (rijndael) cipher with 128 bit keysize. Post place and route logs show the maximum speed to be 333 MHz when implemented on a Virtex-5 LX50T speed grade -1 FPGA with 45% LUT utilization and 27% register utilization. This comes out to a maximum throughput of ~ 42Gbps with an average of 1 encryption every cycle. The overall design has a latency of 30 clock cycles. A brief documentation is available here.\n\n\nThis core has been verified to be correct by the NIST designed Known Answer Tests (KAT).\n\n\nP.S. If you download the project and find it to be useful, please do drop me a mail at my address subhasis256@opencores.org. I will appreciate it very much. :-) \n\n\n \n\n\n \n \n \n\n===== \n TODO =====\n\n\n Design a corresponding fully pipelined decryption engine" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - subhasis256 name: aes_pipe status: Stable svn-updated: Jul 9, 2010 updated: Jul 9, 2010 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/aesccm-r2.tar.gz category: Crypto core created: Aug 19, 2011 description: "===== \n Description =====" language: VHDL license: GPL3 licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: aesccm status: Design done svn-updated: Apr 16, 2013 updated: Apr 16, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Jul 25, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: aesfoldedcore status: Empty updated: Sep 28, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: aesfoldedcorearch status: Empty updated: Sep 28, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: aesitcore status: Empty updated: Sep 28, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: aespipecore status: Empty updated: Oct 25, 2013 wishbone-compliant: 0 - category: Processor created: Mar 13, 2012 description: "===== \n Description =====\n\nThe main features of ag_6502 implementation:\n* It provides not only clock-level compatibility, but phase-level compatibility too. Thus it may be possible to connect simulated 6502 instead of the original one. Source code includes two possibilities to simulate two-phase clocking: by the use of external phi1 and phi2 clock generators and by the simulation of the phase shift using higher frequency source (I used standard 50 MHz clock generator to simulate phases phi1 and phi2 in my test project).\n\n* It requires a relatively small amount of FPGA logic, for example in Xilinx Spartan-3E:\n Flop Flops: 93\n LUTs: 978\n Slices: 512\n\n* In the current implementation the following CPU commands are implemented:\n - All legitimate commands including ADC/SBC in decimal mode (not all illegal features are fully implemented, such as N, Z flags usage in the decimal mode);\n - All KILLs;\n - All NOPs including their \"addressing modes\";\n - All LAX illegal commands;\n - For all other known illegal commands, only fetch and addressing parts are implemented. No real operations are performed, and timings for these commands may be not accurate.\n\n* All input signals are implemented, including RST, IRQ/NMI interrupts, RDY line and even SO pin.\n\n* Maximum tested frequency for Spartan 3E: 10 MHz (10 times faster than original 6502).\n \n\n\n \n \n \n\n===== \n \"Genstates\" Compiler Information =====\n\nFor the development of this core I designed and implemented a simple programming language with optimizing compiler (\"genstates\") producing verilog source (see states.v in the source tree).\nThe main idea of this approach is to minimize required amount of registers replacing them with wires and assigns in Verilog, like it was in MOS 6502.\nThe process of the execution of processor command is described by a sequence of arbitrary mnemonical commands divided by two clock phases and by execution stages (0-fetch etc).\nOn the first phase (phi1) processor drives address bus, R/W line and data output bus (for write). Also it multiplexes internal buses and sets the necessary modes for the following execution.\nOn the second phase (phi2) processor reads data input bus (for read) and performs all internal operations like it was in it's original prototype.\nThe compiler transforms all mnemonical commands into a list of assigns where single command will be just a wire which will be assigned to 1 if in the current moment this command should be executed, and to 0 if not. The real execution of this commands is performed by a main hand-written code.\n\nExample of mnemonical program:\n\n#09: % ORA #IMM\n(0:1 AB <= PC\n(0:2 PC <= PC + 1\n(1:1 AB <= PC\n SB = DB\n ALU_A = AC\n ALU_B = SB\n ALU_OP = ORA\n(1:2 PC <= PC + 1\n AC <= RES\n N,Z <= RES\n T <= 0\n\n\nExample of some of generated wires (after automatic optimization):\n\n// action: DB <= ALU:\n assign E_DB__ALU = ({L[0],L[1],L[2],L[3],L[4],L[6],L[7],L[8],L[9],L[10]} == 10'b0110011110) || \n(({L[0],L[1],L[2],L[6],L[7],L[10]} == 6'b011111) && ((!L[9] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && \n(({L[4],L[8]} == 2'b00) || L[8])))) || ({L[3],L[4],L[8],L[9]} == 4'b1101)));\n\n// action: DB <= PCH:\n assign E_DB__PCH = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000010) || \n({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100110);\n\n// action: PCL <= EAL:\n assign E_PCL__EAL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100101);\n\n\nIn the example above the L vector is just a selector made of 8-bit opcode and 3-bit time counter:\n\n wire[10:0] L = {T, IR_eff};\n\n\nExample of some action handlers:\n\n assign SB = A_SB_DB? db_in:\n A_SB_AC? AC:\n A_SB_X? X:\n A_SB_Y? Y:\n A_SB_S? S:\n A_SB_P? P:\n A_SB_ALU? ALU:\n A_SB_0? 8'b0:\n A_SB_PCH? PCH:\n A_SB_PCL? PCL:\n 8'bX;\n assign ALU_B = A_ALU_B_SB? SB:\n A_ALU_B_NOTSB? ~SB:\n 8'bX;\n always @(posedge phi_1) begin\n if (E_AB__PC) ab <= PC;\n else if (E_AB__EA) ab <= EA;\n else if (E_AB__S) ab <= {8'b1, S};\n ...\n\n\nThus it is possible to easily extend functionality of this model without the need of boring bit-level programming, because main code deals only with relatively high-level objects described by auto-generated wires. Also it is possible to implement any other processor core with this approach, because the description language is completely abstract.\n\n \n\n\n \n \n \n\n===== \n Resource consumption =====" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - olegodintsov name: ag_6502 status: FPGA proven svn-updated: Jun 11, 2012 updated: Jul 31, 2012 wishbone-compliant: 0 - category: Processor created: Oct 23, 2010 description: "===== \n Description =====\n\nA Xilinx Spartan-3E FPGA implementation of the Block II Apollo Guidance Computer (AGC) in VHDL.\n\nHas anyone found this project useful? Any chance of some feedback so I can improve the project?" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - daver2 name: agcnorm status: FPGA proven svn-updated: Jan 4, 2012 updated: Jul 25, 2012 wishbone-compliant: 0 - category: System on Chip created: Jul 31, 2007 description: "===== \n Description =====\n\nAHB Protocol to Wishbone Protocol Bridge.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- AHB 2.0 compliant\n- Wishbone B.3 compliant\n- AHB Burst NOT SUPPORTED\n- Fully synthesisable\n- Synchronous\n- Verilog RTL\n- Includes a Verilog Testbench with 10 Testcases\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- RTL : Complete\n- Testbench : Complete\n- Document : Complete" language: Verilog license: unknown maintainers: - toomuch name: ahb2wishbone status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Testing / Verification created: Apr 24, 2011 description: "===== \n Description =====\n\nGeneric AHB master stub. Built out of an AXI master and an AXI2AHB bridge. Supports 32/64 data bits, AHB bursts and random wait-states. The design is built according to input parameters: address bits, data bits, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: ahb_master status: Alpha svn-updated: Jul 3, 2011 updated: Apr 27, 2011 wishbone-compliant: 0 - category: Testing / Verification created: Apr 13, 2011 description: "===== \n Description =====\n\nGeneric AHB slave stub. Supports 32/64 data bits, AHB bursts and random wait-states. The design is built according to input parameters: address bits, data bits, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: ahb_slave status: Alpha svn-updated: Jul 3, 2011 updated: Apr 27, 2011 wishbone-compliant: 0 - category: System on Chip created: Sep 23, 2004 description: "===== \n Other project properties =====\n\nCategory :: SoC\nLanguage :: VHDL\nLicense :: LGPL\nDevelopment status :: Production/Stable\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- AMBAtm specification compliant (rev 2.0)\n- unified approach to multi-layer, lite and full amba systems\n- programmable arbiter\n- \"template\" master with programmable internal fifo and read/write latencies\n- \"template\" slave with simple default behaviour (i.e. no \"split/retry\" responses)\n- GUI for start-up\n- testbench generation specific to the created system\n- check of connection correctness\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe intention is to provide an easy way to configure, create and simulate a \"complete\" AHB system.\n\nThe main block is the \"AHB matrix\", in which every declared master has to be connected to one or more slaves.\n\nIn order to test the connectivity of the matrix, and to evaluate performance tradeoffs between different architectural choises a configurable arbitration scheme and a \"template\" model of a parametrizable master and slave are provided.\n\nA complete testbench is also available to test the main write and read accesses made by every master to the slaves mapped on its address space.\n\nAHB system generator is a script which builds via GUI or file all .vhd files required to\nsimulate the system: masters, slaves, arbiters, decoders, master and slave muxes.\n\nTo run the AHB system generator you must have installed PERL and a GUI PERL module called Tk (see for example http://www.cpan.org/).\n\nThis configurator is provided by www.ipdesign.eu\n \n\n\n \n \n \n\n===== \n Available on request: =====\n\n- Slave with \"retry\" behaviour with internal fifo\n- Slave with \"split\" behaviour with internal fifo\n- APB slave (simple memory-like interface)\n\nMore IPs on www.ipdesign.eu:\n- AHB/AHB bridge\n- AHB/APB bridge\n- AHB DMA\n- WB/AHB bridge" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: ahb_system_generator status: Stable svn-updated: Feb 7, 2010 updated: Mar 31, 2013 wishbone-compliant: 0 - alternate-download: https://github.com/linuxbest/ahci/archive/master.zip category: Communication controller created: Feb 13, 2013 description: "===== \n Description =====\n\nplease check the source code from:\n\nhttps://github.com/linuxbest/ahci\nhttps://github.com/linuxbest/ahci_mpi" homepage: https://github.com/linuxbest/ahci language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - linuxbest name: ahci_sata status: Empty updated: Feb 18, 2013 wishbone-compliant: 0 - category: System on Chip created: Oct 20, 2011 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - aw1231 name: alex status: Empty updated: Dec 13, 2011 wishbone-compliant: 1 - category: DSP core created: Jun 10, 2011 description: "===== \n Description =====\n\nThe circuits found here implement digital leapfrog filters as described in http://en.wikibooks.org/wiki/Signal_Processing/Digital_Filters >. All filters are of lowpass type. They are optimised in terms of area.\n\nThis kind of filter structure is the digital counterpart of an analog lumped-elements ladder filter. It simulates the functioning of an all-pole lowpass filter under the assumption of a large oversampling. The circuit implements the integral relations between voltages and currents of the capacitors and the inductances with the help of accumulators. This corresponds to simplify the Z-transform to z = 1 + sT.\n\nThe relative values of the filter coefficients specify the transfer function shape (Butterworth, Chebyshev, ...). The amplitude of the coefficients specify the cutoff frequency. In the circuits provided here, this amplitude is set by a shift value given as a generic.\n\nThe filter provided are\n - a 3rd order Butterworth with no multiplier (coefficients are only shifts)\n - a 6th and an 8th order Bessel with coefficients optimised to 2 shifts and an addition\n - a generic filter where the coefficient multiplications are executed iteratively" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - fcorthay name: all-pole_filters status: FPGA proven svn-updated: Jul 1, 2011 updated: Jul 20, 2012 wishbone-compliant: 0 - category: Other created: Mar 14, 2005 description: "===== \n Description =====\n\nThe design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency, and the respective output frequency, via phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked.\n\nIn the new architecture we propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera\xC2\xAE APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal.\n\n- The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device. The real measurement is done using ChipScope Pro 6.3i.\n\n- The new architecture is fall into compact size architecture, a new simple demodulation algorithm without multiplier, very fast, running without ROM or look-up table, and takes an absolute stability structure which has no feedback loop for input phase tracking.\n\n- The new architecture enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera\xC2\xAE APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Done in simulation level\n- Try to de-modulate real time sound signal" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - rahmatullah name: all_digital_fm_receiver status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 7, 2012 wishbone-compliant: 0 - category: Other created: May 30, 2005 description: "===== \n Description =====\n\nAlternaScope provides a cheap alternative to expensive oscilloscopes; Using a VGA display and a simple mouse interface, a user can use this scope to look at and measure signals up to about 80Mhz. \nThis kind of scope would be ideal for hobbyists and students looking to learn and debug circuits. \n\nDevelopment is based on the Spartan III Starter Kit from Xilinx. The ADC is simply controlled by an MCU (another starter kit: the ATK500 from Atmel) but will soon be controlled by the FPGA (to achieve the faster speeds).\nIn the future, schematics and PCB layout binaries will be available.\n\nNOTICE: I have started working on a 'BMP Picture' style of exporting data via RS-232 or USB, but do not have the time to write a Win-32 application to interpret the data. Anybody interested?\n\nI aplogize for the bad quality of the snapshot. This is why I need screenshot support :)\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Timescale selection\n- Selectable trigger (Rising, Falling / Normal, Single, Auto) \n- Horizontal and Vertical position offsets\n- Grid Display On/Off/Outline\n- Semi-standard Oscilloscope look and feel\n- VGA display; drives a standard computer monitor\n- PS/2 Mouse User Interface\n- 9-bit input data width\n- Developed specifically for the Spartan III devleopment kit from Xilinx (for now)\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Soon to come =====\n\n(Not necessarily in this order)\n- FFT display\n- Measurement Display (amplitude, frequency)\n- Cursors\n- Vectors\n- Multi channel display (up to 8+)\n- Channel Math\n- UART or USB computer communication (data export)\n\n \n\n\n \n \n \n\n===== \n IMAGE: BlockDiagram_small.GIF =====\n\nFILE: BlockDiagram_small.GIF\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n IMAGE: OpenCores.JPG =====\n\nFILE: OpenCores.JPG\nDESCRIPTION:" language: Verilog license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - smpickett name: alternascope status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Jun 9, 2012 description: "===== \n Description =====\n\nAltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc project. \nInstructions & registers relating to Vector, floating-point, 64-bit extensions, MMU & Cache have been omitted. \nThe aim of AltOR32 is to provide a simple 32-bit soft CPU architecture aimed at control applications that can fit in low-end FPGA technology. \n\nThis design implements all instructions that cannot be disabled. Anything else is viewed as beyond the scope of this cut-down soft-CPU implementation. \n\nAltOR32 does not make use of delay slots, unlike the original OpenRisc implementation. \nDue to this, the or1knd toolchain is required. \n \n\n\n \n \n \n\n===== \n Toolchain =====\n\nThe 'or1knd' toolchain is required for this target. \n\nTo build from source: \n\ngit clone git://github.com/openrisc/or1k-src.git \ngit clone git://github.com/openrisc/or1k-gcc.git \n\nBuild the first set of tools, binutils etc.\n\n../or1k-src/configure --target=or1knd-elf --prefix=/opt/or1k-toolchain --enable-shared \\ \n--disable-itcl --disable-tk --disable-tcl --disable-winsup --disable-libgui --disable-rda \\ \n--disable-sid --disable-sim --disable-gdb --with-sysroot --disable-newlib --disable-libgloss --disable-werror \nmake \nmake install \n\nBuild gcc \n\n../or1k-gcc/configure --target=or1knd-elf --prefix=/opt/or1k-toolchain --enable-languages=c \\ \n--disable-shared --disable-libssp --disable-werror \nmake \nmake install \n \n\n\n \n \n \n\n===== \n Verilator =====\n\nThe project contains a Verilator cycle accurate model of the CPU which can execute the same code as the simulator. Waveforms can be outputted and viewed in GTKWave.\n\n \n\n\n \n \n \n\n===== \n Current Status =====\n\n- Pipelined Verilog core with optional instruction & data cache. \n- Synthesizes to ~100MHz on a Xilinx Spartan 6 LX9 -3\n- Harvard architecture (separate instruction & data cache / memory interfaces). \n- Support for interrupts & tick timer. \n- Also non-pipelined 'lite' version available. \n \n\n\n \n \n \n\n===== \n Instruction Set Simulator =====\n\n- A simple simulator for OpenRisc instructions. \n- Able to execute OpenRisc 1000 (ORBIS32) code compiled with the following options: \n-msoft-div -msoft-float -msoft-mul -mno-ror -mno-cmov -mno-sext \n- Extensible" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ultra_embedded name: altor32 status: FPGA proven svn-updated: Jun 29, 2014 updated: Feb 15, 2015 wishbone-compliant: 1 - category: Processor created: May 9, 2009 description: "===== \n Description =====\n\nAlwcpu is a light weight CPU in terms of logic resources.\n - 16 bit address and data bus. (Instructions are 16 bit as well)\n - Wishbone interface\n - Is parameterizable to optimize size, e.g. skipping of instruction groups, selectable 8 or 16 registers...\n - Core size is about 52-55 FF and 335-478 LUT's (depending on configuration) in a Spartan 3-400 when compiled for Area.\n - The core has 4 special registers and 4(*4) general purpose registers in minimum configuration\n - If more registers needed another 8(*2) registers could be enabled through configuration. See documentation for the CPU.\n - Some binary combinations for instructions are left reserved for the future for more instructions.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Core written\n - Core optimization done for now, more to do in the future\n - Simulation and initial testing done\n - Finally released core in SVN (Check Web-upload dir)\n - Assembler development is planned.\n \n\n\n \n \n \n\n===== \n Future =====\n\n- More instructions should be possible to disable with generics\n - Maybe develop interrupt handling (register map switching is even more useful when having interrupts)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - avmcu name: alwcpu status: Design done svn-updated: Jun 7, 2009 updated: Oct 26, 2010 wishbone-compliant: 1 - category: Communication controller created: Sep 17, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: amba_to_wb_con status: Empty updated: Sep 18, 2014 wishbone-compliant: 0 - category: Processor created: Dec 23, 2010 description: "===== \n Description =====\n\nThe Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core \nis fully compatible with the ARM\xC2\xAE v2a instruction set architecture (ISA) and is \ntherefore supported by the GNU toolset. The Amber project provides a complete embedded \nsystem incorporating the Amber core and a number of peripherals, including a UART, a\ntimer and an Ethernet MAC.\n\n\n\n\nThere are two versions of the core provided in the Amber project. The Amber 23 has \na 3-stage pipeline, a unified instruction & data cache, a 32-bit Wishbone \ninterface, and is capable of 0.75 DMIPS per MHz. The Amber 25 has a 5-stage \npipeline, seperate data and instruction caches, a 128-bit Wishbone interface,\nand is capable of 1.05 DMIPS per Mhz. Both cores implement exactly the same ISA\nand are 100% software compatible. The cores do not contain a memory management \nunit (MMU) so they can only run the non-virtual memory variant of Linux. The \ncores has been verified by booting a 2.4 Linux kernel.\n\nThe cores were developed in Verilog 2001, and are optimized for FPGA synthesis.\nFor example there is no reset logic, all registers are reset as part of FPGA\ninitialization. The complete system has been tested extensively on the Xilinx SP605\nSpartan-6 FPGA board. The full Amber system with the A23 core uses 32% of the\nSpartan-6 XC6SLX45T-3 FPGA Look Up Tables (LUTs), with the core itself\noccupying less than 20% of the device using the default configuration, and running at\n40MHz. It has also been synthesized to a Virtex-6 device at 80MHz.\n\nThe older v2a version of the ARM instruction set is supported because it is still \nfully supported by the GNU tool chain and is not covered by patents so can be \nimplemented without a license from ARM. For a description of the ISA, see \n\nArchimedes Operating System - A Dabhand Guide or \n\nAcorn RISC Machine Family Data Manual\n\nFor project documentation, see \n\namber-user-guide.pdf and amber-core.pdf.\n\nAfter reading the project documentation you can find further help on the Amber A23 Core page on the opencores forum." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - csantifort name: amber status: FPGA proven svn-updated: Apr 11, 2015 updated: Apr 29, 2015 wishbone-compliant: 1 - category: Arithmetic core created: Apr 8, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - raiogam name: ambermiddle status: Empty updated: Apr 8, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Mar 2, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - pydisrinivasarao name: an-algoritham-to-detect-the-proximity-of-a-moving-target status: Empty updated: Mar 2, 2013 wishbone-compliant: 0 - category: System on Chip created: Jan 13, 2014 description: "===== \n Description =====\n\nThis project aims to present an open-source, platform independent MPSoC, targeting FPGA implementation. \n\xC2\xA0\nThe NoC based MPSoC is generated by connecting the processing tiles via a low latency NoC network. A processing tile includes one aeMB processor, RAM, NoC interface adapter, and other optional peripheral devices such as GPIO, timer, external interrupts and interrupt controller. All components inside a tile are connected using wishbone bus. The processing tiles can have different number of peripheral devices, which is defined using parameter.\n\nIn this project A two clock-cycles pipelined wormhole virtual channel network-on-chip (NoC) router RTL is proposed. The router first pipeline stage is the parallel look-ahead route computation with a non-speculative VC/switch allocation. The second stage is the crossbar switch traversal. The proposed router micro-architecture is optimized in three main criteria of hardware cost, maximum operating frequency and QoS compared to existing related works.\n\nTwo Network interface (NI) modules are proposed: one for connecting the processor core to NoC via wishbone bus. The proposed NI is able to read and write on the processor data memory in a DMA fashion. Another NI is designed to connect any shared memory (eg. external SDRAM) to NoC. \n\n We tested our NoC based MPSoC on DE2-115 Altera board. \n \n\n\n \n \n \n\n===== \n Features =====\n\n \n . Two clk cycles, low latency, low hardware cost NoC\n . Virtual Channel (VC), wormhole based router\n . Non-speculative switch and VC allocation\n . Look-ahead routing \n . Fully parameterizable in terms of, VC number, buffer size and node-number\n . Platform independent\n . Wishbone adaptable NI\n . Mesh and Torus topology \n . parameterizable processing cores\n\n\n \n \n\n\n \n \n \n\n===== \n Compiler =====\n\nThe aeMB compiler can be downloaded from : http://gnuradio.org/tools/mb-gcc-4.1.1.gr2.i386.tar.gz\n\n \n\n\n \n \n \n\n===== \n To Do List =====\n\n. Support RTOS" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - alirezamonemi name: an-fpga-implementation-of-low-latency-noc-based-mpsoc status: FPGA proven svn-updated: Mar 19, 2014 updated: Apr 19, 2014 wishbone-compliant: 1 - category: Arithmetic core created: Dec 18, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: ann status: Empty updated: Dec 18, 2013 wishbone-compliant: 0 - category: Processor created: Mar 30, 2014 description: "===== \n Description =====\n\nThe ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.\nThe core was modeled and tested based on the Bochs software x86 implementation.\nTogether with the 486 core, the ao486 project also contains a SoC capable of\nbooting the Linux kernel version 3.13 and Microsoft Windows 95.\n \n\n\n \n \n \n\n===== \n Current status =====\n\n\n31 March 2014 - initial version 1.0.\n19 August 2014 - driver_sd update, ps2 fix.\n\n\n \n\n\n \n \n \n\n===== \n Links =====\n\n\nao486 project on github.com: http://github.com/alfikpl/ao486.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe ao486 processor model has the following features:\n\npipeline architecture with 4 main stages: decode, read, execute and write,\nall 486 instructions are implemented, together with CPUID,\n16 kB instruction cache,\n16 kB write-back data cache,\nTLB for 32 entries,\nAltera Avalon interfaces for memory and io access.\n\n\nThe ao486 SoC consists of the following components:\n\nao486 processor,\nIDE hard drive that redirects to a HDL SD card driver,\nfloppy controller that also redirects to the SD card driver,\n8259 PIC,\n8237 DMA,\nSound Blaster 2.0 with DSP and OPL2 (FM synthesis not fully working).\n Sound output redirected to a WM8731 audio codec,\n8254 PIT,\n8042 keyboard and mouse controller,\nRTC,\nstandard VGA.\n\n\n\n\n\nAll components are modeled as Altera Qsys components. Altera Qsys connects all\nparts together, and supplies the SDRAM controller.\n\n\n\n\n\n\n\nThe ao486 project is currently only running on the Terasic DE2-115 board.\n\n\n\n\n \n\n\n \n \n \n\n===== \n Resource usage =====\n\nThe project is synthesised for the Altera Cyclone IV E EP4CE115F29C7 device.\nResource utilization is as follows:\n\n\nUnitLogic cellsM9K memory blocks\n\nao486 processor 3651747\nfloppy 1514 2 \nhdd 2071 17\nnios2 1056 3 \nonchip for nios20 32\npc_dma 848 0 \npic 388 0 \npit 667 0 \nps2 742 2 \nrtc 783 1 \nsound 3713129\nvga 2534 260\n\n\n\n\n\nThe fitter raport after compiling all components of the ao486 project is as\nfollows:\n\n\n\n\n\nFitter Status : Successful - Sun Mar 30 21:00:13 2014 \nQuartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition\nRevision Name : soc \nTop-level Entity Name : soc \nFamily : Cyclone IV E \nDevice : EP4CE115F29C7 \nTiming Models : Final \nTotal logic elements : 91,256 / 114,480 ( 80 % ) \n Total combinational functions : 86,811 / 114,480 ( 76 % ) \n Dedicated logic registers : 26,746 / 114,480 ( 23 % ) \nTotal registers : 26865 \nTotal pins : 108 / 529 ( 20 % ) \nTotal virtual pins : 0 \nTotal memory bits : 2,993,408 / 3,981,312 ( 75 % ) \nEmbedded Multiplier 9-bit elements : 44 / 532 ( 8 % ) \nTotal PLLs : 1 / 4 ( 25 % ) \n\n\n\n\n\nThe maximum frequency is 39 MHz. The project uses a 30 MHz clock.\n\n\n\n\n \n\n\n \n \n \n\n===== \n CPU benchmarks =====\n\nThe package DosTests.zip from\nhttp://www.roylongbottom.org.uk/dhrystone%20results.htm\nwas used to benchmark the ao486.\n\n\nTestResult\nDhryston 1 Benchmark Non-Optimised1.00 VAX MIPS\nDhryston 1 Benchmark Optimised 4.58 VAX MIPS\nDhryston 2 Benchmark Non-Optimised1.01 VAX MIPS\nDhryston 2 Benchmark Optimised 3.84 VAX MIPS\n\n\n \n\n\n \n \n \n\n===== \n Running software =====\n\nThe ao486 successfuly runs the following software:\n\nMicrosoft MS-DOS version 6.22,\nMicrosoft Windows for Workgroups 3.11,\nMicrosoft Windows 95,\nLinux 3.13.1.\n\n\n \n\n\n \n \n \n\n===== \n BIOS =====\n\nThe ao486 project uses the BIOS from the Bochs project\n(http://bochs.sourceforge.net, version 2.6.2). Some minor changes\nwere required to support the hard drive.\n\n\n\n\n\n\n\nThe VGA BIOS is from the VGABIOS project (http://www.nongnu.org/vgabios,\nversion 0.7a). No changes were required. The VGA model does not have VBE\nextensions, so the extensions were disabled.\n\n\n\n\n \n\n\n \n \n \n\n===== \n NIOS2 controller =====\n\nThe ao486 SoC uses a Altera NIOS2 processor for managing all components and\ndisplaying the contents of the On Screen Display.\n\n\n\n\n\n\n\nThe OSD allows the user to insert and remove floppy disks.\n\n\n\n\n \n\n\n \n \n \n\n===== \n License =====\n\nAll files in the following directories:\n\nrtl,\nao486_tool,\nsim.\n\nare licensed under the BSD license:\n\nAll files in the following directories:\n\nbochs486,\nbochsDevs.\n\nare taken from the Bochs Project and are licensed under the LGPL license.\n\n\n\n\nThe binary file sd/fd_1_44m/fdboot.img is taken from the FreeDOS project.\n\n\n\n\n\n\n\nThe binary file sd/bios/bochs_legacy is a compiled BIOS from the Bochs project.\n\n\n\n\n\n\n\nThe binary file sd/vgabios/vgabios-lgpl is a compiled VGA BIOS from the vgabios\nproject." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - alfik name: ao486 status: FPGA proven svn-updated: Aug 19, 2014 updated: Aug 19, 2014 wishbone-compliant: 0 - category: Processor created: Mar 28, 2010 description: "===== \n Description =====\n\nThe OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.\n\n \n\n\n \n \n \n\n===== \n Introduction =====\n\nJuly 2011: Project copied to (https://github.com/alfikpl/ao68000). Further development of ao68000 will continue on github.\n\nFeatures\n\nCISC processor with microcode,\nWISHBONE revision B.3 compatible MASTER interface,\nNot cycle exact with the MC68000, some instructions take more cycles to complete, some less,\nUses about 4750 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,\nTested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents (Processor verification). The result of execution was compared,\nContains a simple prefetch which is capable of holding up to 5 16-bit instruction words,\nDocumentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification is automatically extracted from the Doxygen HTML output.\n\nWISHBONE compatibility\n\nVersion: WISHBONE specification Revision B.3,\nGeneral description: 32-bit WISHBONE Master interface,\nWISHBONE signals described in IO Ports,\nSupported cycles: Master Read/Write, Master Block Read/Write, Master Read-Modify-Write for TAS instruction, Register Feedback Bus Cycles as described in chapter 4 of the WISHBONE specification,\nUse of ERR_I: on memory access \xE2\x80\x93 bus error, on interrupt acknowledge: spurious interrupt,\nUse of RTY_I: on memory access \xE2\x80\x93 repeat access, on interrupt acknowledge: generate auto-vector,\nWISHBONE data port size: 32-bit,\nData port granularity: 8-bits,\nData port maximum operand size: 32-bits,\nData transfer ordering: BIG ENDIAN,\nData transfer sequencing: UNDEFINED,\nConstraints on CLK_I signal: described in Clocks, maximum frequency: about 82 MHz.\n\nUse\n\nThe ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC (http://opencores.org/project,aoocs)\nIt can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to init program lookup (System-on-Chip example with ao68000 running Linux).\n\nSimilar projects\n\n\nOther free soft-core implementations of M68000 microprocessor include:\n\n\n\nOpenCores TG68 (http://www.opencores.org/project,tg68) - runs Amiga software, used as part of the Minimig Core,\nSuska Atari VHDL WF_68K00_IP Core (http://www.experiment-s.de/en) - runs Atari software,\nOpenCores K68 (http://www.opencores.org/project,k68) - no user and supervisor modes distinction, executes most instructions, but not all.\nOpenCores ae68 (http://www.opencores.org/project,ae68) - no files uploaded as of 27.03.2010.\n\nLimitations\n\nMicrocode not optimized: some instructions take more cycles to execute than the original MC68000,\nTRACE not tested,\nThe core is still large compared to other implementations.\n\nTODO\n\nOptimize the desgin and microcode,\nCount the exact cycle count for every instruction,\nTest TRACE,\nWrite more documentation.\n\nStatus\n\nApril 2010: Tested with WinUAE software MC68000 emulator,\nApril 2010: Booted Linux kernel up to init process lookup,\nDecember 2010: Runs as a processor in OpenCores aoOCS project,\nJanuary 2011: Core area optimization by over 33% (Thanks to Frederic Requin).\nJuly 2011: Project copied to (https://github.com/alfikpl/ao68000). Further development of ao68000 will continue on github.\n\nRequirements\n\nIcarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the tb_ao68000 testbench/wrapper,\nAccess to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the tb_ao68000 testbench/wrapper,\nGCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator,\nJava runtime (http://java.sun.com) is required to run the ao68000_tool (ao68000_tool documentation),\nJava SDK (http://java.sun.com) is required to compile the ao68000_tool (ao68000_tool documentation),\nAltera Quartus II synthesis tool (http://www.altera.com) is required to synthesise the soc_for_linux System-on-Chip (System-on-Chip example with ao68000 running Linux).\n\nGlossary\n\nao68000 - the ao68000 IP Core processor,\nMC68000 - the original Motorola MC68000 processor. \n\n\nStructure diagram" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - alfik name: ao68000 status: Beta svn-updated: Feb 24, 2011 updated: Oct 23, 2012 wishbone-compliant: 1 - category: System on Chip created: Dec 19, 2010 description: "===== \n Description =====\n\nThe OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality.\naoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.\n \n\n\n \n \n \n\n===== \n Introduction =====\n\nJuly 2011: Project copied to (https://github.com/alfikpl/aoOCS). Further development of aoOCS will continue on github.\n\nFeatures\n\nThe aoOCS SoC contains the following Amiga/OCS components:\nblitter\ncopper\nsystem control (interrupts)\nvideo: bitplains, sprites, collision detection\naudio: 4 channels, low-pass filter\nuser input: PS/2 mouse, PS/2 keyboard and joystick (keyboard arrow keys)\nfloppy: read and write ADF files directly from a SD card. Only the internal floppy drive is implemented\n8520 CIA\nao68000 OpenCores IP core is used as the aoOCS processor\n\n\nAll of the above components are WISHBONE revision B.3 compatible\nThe aoOCS contains the following additional components:\nSD card controller written in HDL with DMA. Supports SDHC cards only.\n10/100 Mbit Ethernet controller written in HDL to send the current VGA frames (frame grabber)\nHDL drivers for SSRAM, PS/2 keyboard, PS/2 mouse, audio codec, VGA DAC\n\n\naoOCS uses only one external memory: a SSRAM with 36-bit words and pipelined access. A video buffer with about 250KB is located SSRAM. Another 256KB are used by the ROM. All the rest memory can be used as Chip RAM.\nThe On-Screen-Display is implemented in HDL as a finite state machine. No additional controller/processor with firmware required to handle the SoC.\nThe following options are available on the On-Screen-Display:\nselect ROM file to load (only Amiga Kickstart v1.2 was tested)\nenable or disable Joystick (keyboard arrow keys)\nenable or disable floppy write protection\ninsert a floppy - select one from a list\neject an inserted floppy\nreset the system\n\n\nThe On-Screen-Display is independent of the running Amiga software. It is enabled and disabled by the Home key and controled by the keyboard arrow keys and the right CTRL key.\nOnly PAL timings are implemented.\nThe video output is VGA compatible: 640x480 at 70 Hz. A rather simple method is used to extend the 256 PAL horizontal lines to 480 VGA lines: all lines are doubled except for every 8th one.\nThe system uses generally a single clock: 30 MHz. There are two more clocks: 12 MHz, 25 MHz generated to interface with external hardware (Audio codec, Ethernet controller). A single altpll is used to generate all three clocks from one 50 MHz external clock. More information about clocks is available at Clocks.\nA VGA frame grabber is implemented that sends captured frames by 100 Mbit Ethernet in IP/UDP packets.\nThe system uses about 26.400 LE on Altera Cyclone II and about 267.000 bits of on-chip RAM.\nThe blitter functionality was tested against the E-UAE Amiga software emulator.\nTested only on a Terasic DE2-70 board (www.terasic.com.tw).\nDocumentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification is automatically extracted from the Doxygen HTML output.\n\nWISHBONE compatibility\n\nVersion: WISHBONE specification Revision B.3,\nGeneral description: 32-bit WISHBONE interface,\nWISHBONE data port size: 32-bit,\nData port granularity: 8-bits,\nData port maximum operand size: 32-bits,\nData transfer ordering: BIG ENDIAN,\nData transfer sequencing: UNDEFINED,\nConstraints on CLK_I signal: described in Clocks.\n\nSimilar projects\n\n\nOther Open-Source Amiga implementations include:\n\n\n\nMinimig (http://code.google.com/p/minimig/) - FPGA-based re-implementation of the original Amiga 500 hardware. Runs on the Minimig PCB and also on Terasic DE1,2 boards.\n\nLimitations\n\nNo filesystem support on the SD card. Data is read from fixed positions. The contents of the SD card is generated by the aoOCS_tool described at Operation.\nNo video external synchronize, lace mode, lightpen, genlock audio enable, color composite (BPLCON0)\nAll bitplain data is fetched at once in a burst memory read at the begining of each line. No changes to the bitplain data done after the beginning of a line are visible.\nCurrently aoOCS requires an 36-bit word SSRAM to store the video buffer. This way 3 pixels 12-bits each can be stored in one word.\nSerial port not implemented.\nParallel port not implemented.\nLow-pass filter disable/enable by CIA-A port A bit 1 not implemented.\nProportional controller and light pen not implemented.\nSome rarely used OCS registers are not implemented: strobe video sync, write beam position, coprocessor instruction fetch identify. For a complete list of not implemented registers look at Registers.\nOnly some of the Amiga software was tested and works on the aoOCS. A list of aoOCS software compatability is located at Operation.\n\nTODO\n\nFix some of the above limitations.\nOptimize the design.\nRun WISHBONE verification models.\nMore documentation of Verilog sources.\nDescribe testing and changes done in E-UAE sources.\nPrepare scripts for VATS: run_sim -r -> regresion test.\nPort the aoOCS SoC to a Xilinx FPGA.\n\nStatus\n\nAmiga Workbench v1.2 runs with some minor graphic problems: bottom of screen not displayed correctly.\nPrince of Persia runs perfectly.\nWings of Fury runs correctly. Some sound glitches in intro.\nLotus 2 runs correctly. Some sound problems in intro.\nWarzone runs poor. Some major graphic problems.\nMore information about aoOCS software compatability is available at Operation.\nJuly 2011: Project copied to (https://github.com/alfikpl/aoOCS). Further development of aoOCS will continue on github.\n\nRequirements\n\nAltera Quartus II synthesis tool (http://www.altera.com) is required to synthesise the aoOCS System-on-Chip.\nJava SDK (http://java.sun.com) is required to compile the aoOCS_tool (The tool is described in Operation).\nA FPGA board. Currently only the Terasic DE2-70 board was tested.\nIcarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the and run some tests.\nAccess to Altera Quartus II directory (directory eda/sim_lib/) is required to compile and run some tests.\nGCC (http://gcc.gnu.org) is required to compile some testes based on E-UAE sources. \n\n\nStructure Diagram:\n\n\nScreenshots:\n\n\n\n\nAmiga Kickstart v1.2 bootstrap screen with aoOCS On-Screen-Display\n\n\n\n\n\n\n\n\nAmiga Workbench v1.2 screen\n\n\n\n\n\n\n\n\nWings of Fury" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - alfik name: aoocs status: FPGA proven svn-updated: Dec 20, 2010 updated: Aug 4, 2011 wishbone-compliant: 1 - category: Processor created: Aug 11, 2014 description: "===== \n Description =====\n\nThe aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.74 BogoMIPS. It features a compatible MMU, but no FPU.\n \n\n\n \n \n \n\n===== \n Current status =====\n\n\n11 August 2014 - initial version 1.0.\n\n\n \n\n\n \n \n \n\n===== \n Links =====\n\n\naoR3000 project on github.com: http://github.com/alfikpl/aoR3000.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe aoR3000 soft processor core has the following features:\n\n 5 stage pipeline (single-issue, in-order, forwarding, hazard detection);\n implements all MIPS I instructions (this includes the privileged coprocessor 0 instructions);\n the MMU in coprocessor 0 is compatible with the R3000A but has more micro-TLB entries: 64 TLB entries, 8 micro-TLB entries for data, 4 micro-TLB entries for instructions;\n 2 kB instruction cache (direct map);\n 2 kB data cache (direct map);\n all exceptions are implemented (bus error exceptions are not issued, exceptions in branch delays are supported);\n the core has one combined instruction/data Altera Avalon MM master interface (with burst and pipelined instruction reads, pipelined data reads);\n multiplication implemented in hardware using vendor-independent modules (Altera Quartus II infers embedded multipliers);\n division implemented in hardware using long division (33 clock cycles required);\n the core uses 7700 LE and runs at 50 MHz on a Altera Cyclone IV EP4CE115F29C7;\n the core is modeled in a vendor-independent subset of Verilog consistent with the requirements of Verilator (fully synchronous design, no vendor specific module instances);\n a Verilator generated executable C++ model is available;\n the core was tested and compared with the vmips software R3000 emulator;\n the core is chosen to be little-endian and can not be changed by software;\n\n\n \n\n\n \n \n \n\n===== \n Resource usage =====\n\nThe following table shows the result of synthesis using a balanced area/speed optimization: \n\n\n +---------------------------------------------------------------------------------+ \n ; Flow Summary ; \n +------------------------------------+--------------------------------------------+ \n ; Flow Status ; Successful - Mon Aug 11 21:46:48 2014 ; \n ; Quartus II 64-Bit Version ; 14.0.0 Build 200 06/17/2014 SJ Web Edition ; \n ; Revision Name ; aoR3000 ; \n ; Top-level Entity Name ; aoR3000 ; \n ; Family ; Cyclone IV E ; \n ; Device ; EP4CE115F29C7 ; \n ; Timing Models ; Final ; \n ; Total logic elements ; 7,660 / 114,480 ( 7 % ) ; \n ; Total combinational functions ; 7,174 / 114,480 ( 6 % ) ; \n ; Dedicated logic registers ; 2,633 / 114,480 ( 2 % ) ; \n ; Total registers ; 2633 ; \n ; Total pins ; 115 / 529 ( 22 % ) ; \n ; Total virtual pins ; 0 ; \n ; Total memory bits ; 61,616 / 3,981,312 ( 2 % ) ; \n ; Embedded Multiplier 9-bit elements ; 8 / 532 ( 2 % ) ; \n ; Total PLLs ; 0 / 4 ( 0 % ) ; \n +------------------------------------+--------------------------------------------+ \n\n +-------------------------------------------------+ \n ; Slow 1200mV 85C Model Fmax Summary ; \n +-----------+-----------------+------------+------+ \n ; Fmax ; Restricted Fmax ; Clock Name ; Note ; \n +-----------+-----------------+------------+------+ \n ; 52.58 MHz ; 52.58 MHz ; clk ; ; \n +-----------+-----------------+------------+------+ \n\n\n \n\n\n \n \n \n\n===== \n Implemented instructions =====\n\nAll the MIPS I instructions are implemented:\n\n ADD, ADDI, ADDIU, ADDU, AND, ANDI, NOR, OR, ORI, SLL, SLLV, SLT, SLTI, SLTIU, SLTU, SRA, SRAV, SRL, SRLV, SUB, SUBU, XOR, XORI, LUI;\n DIV, DIVU, MULT, MULTU, MTHI, MTLO, MFHI, MFLO;\n BREAK, SYSCALL;\n CFCz, CTCz, LWCz, SWCz;\n MFCz, MTCz;\n COPz, RFE, TLBP, TLBR, TLBWI, TLBWR;\n BEQ, BGEZ, BGEZAL, BGTZ, BLEZ, BLTZ, BLTZAL, BNE, J, JAL, JALR, JR;\n LB, LBU, LH, LHU, LW, LWL, LWR, SB, SH, SW, SWL, SWR;\n\n\n \n\n\n \n \n \n\n===== \n Running the tests =====\n\nThe aoR3000 core can be converted by Verilator to a C++ executable model. This executable model was compared with the vmips software R3000 emulator (http://vmips.sourceforge.net/) in simulation.\nAll instructions were simulated with random register and memory contents. After every instruction the register contents are compared.\n\nTo run the test the following steps have to be taken:\n\n compile the vmips emulator in sim/vmips/ by 'make tester';\n compile the Verilator aoR3000 model in sim/aoR3000/ by 'make tester';\n choose the test to be run in sim/tester/main_tester.cpp by setting the pointer 'tst_t *tst_current =';\n compile the tester in sim/tester/ by 'make tester';\n run the tester in sim/tester/ by './main_tester';\n\n\n \n\n\n \n \n \n\n===== \n GNU toolchain =====\n\nTo run programs on the aoR3000 a standard GNU toolchain in required. I used the following options during compilation of the toolchain:\n\n for GNU binutils: './../binutils-2.24.51/configure --prefix= --target=mipsel-unknown-linux-gnu';\n for GCC: './../gcc-4.9.1/configure --prefix= --target=mipsel-unknown-linux-gnu --enable-languages=c --disable-threads --disable-shared --disable-libssp --disable-libquadmath --disable-libgomp --disable-libatomic';\n\n\nThe target 'mipsel-unknown-elf' can also be used, but more changes are required to the Linux kernel in that case.\n \n\n\n \n \n \n\n===== \n Building a minimal Linux kernel =====\n\nIn the directory linux/ there is a minimal set of files required to add the aoR3000 SoC platform to the kernel sources version 3.16. To compile the kernel with these changes just copy/overwrite the files in\na Linux source tree. After that 'make ARCH=mips CROSS_COMPILE=mipsel-unknown-linux-gnu- vmlinux.bin' to build the kernel.\n\n \n\n\n \n \n \n\n===== \n Booting the Linux kernel in simulation on a Verilator executable model of the aoR3000 =====\n\nThe booting of the Linux kernel is performed in a similar method like the tests described above. The Verilator executable model of the aoR3000 is run together with the vmips R3000 software simulator to verify\nthe correctness of the aoR3000. Every write to memory is checked to confirm that both of the models write the same data at the same time and in the same order.\n\nTo boot the Linux kernel in simulation the following steps have to be taken:\n\n compile the vmips emulator in sim/vmips/ by 'make linux';\n compile the Verilator aoR3000 model in sim/aoR3000/ by 'make linux';\n compile the tester in sim/tester/ by 'make linux';\n compile the Linux kernel to get the 'vmlinux.bin' file in the arch/mips/boot/ directory;\n run the tester in sim/tester/ by './main_linux ';\n\n\nThe booting of the Linux kernel takes about 12 minutes on a modern PC (more than 46 milion instructions have to be executed/simulated).\n\nThe tester simulates the following hardware devices:\n\n an eary Linux console that outputs the data written to that console to the file 'tester/early_console.txt';\n a simple hardware time interrupt device that signals IRQ 0 every 10 miliseconds;\n an Altera JTAG UART connected to a pseudo terminal (Unix PTY). The terminal name is printed just after executing the tester (for example: 'slave pty: /dev/pts/9');\n\n\nTo connect to this terminal one can use the following command: 'picocom --nolock /dev/pts/9'. Data can be read and written to this terminal.\n\n \n\n\n \n \n \n\n===== \n Booting the Linux kernel on a FPGA with a synthesized aoR3000 =====\n\nTogether with the aoR3000 core there is also a example SoC in the syn/soc/ directory. It consists of:\n\n the aoR3000 core;\n an Altera JTAG UART;\n an Altera SDRAM controller;\n a simple time interrupt device;\n onchip memory for the boot code of the aoR3000;\n an Altera JTAG to Avalon Master Bridge to upload the Linux kernel;\n\n\nThe SoC is designed for the Terasic DE2-115 board.\n\nTo compile the SoC the following steps have to be taken:\n\n open the Altera Quartus II project in syn/soc/;\n open the Qsys tool and generate the HDL;\n compile the project;\n program the FPGA with the compiled project;\n in the Altera Nios2 Command Shell enter the directory arch/mips/boot/ of the Linux kernel and run 'system-console -cli';\n load the Linux kernel binary using the system-console by entering the following TCL commands at the system-console prompt:\n\n\n\n\n set srv [claim_service \"master\" [lindex [get_service_paths \"master\"] 0] \"\"]; \n master_write_from_file $srv vmlinux.bin 0; \n close_service master $srv; \n\n\n\n\n open the nios2-terminal in a Altera Nios2 Command Shell;\n verify that the following text is displayed in the terminal: 'Press any key to boot kernel...';\n press any key to boot the kernel;\n\n\nThe kernel is booted with the following output displayed on the nios2-terminal:\n\n\n\n Press any key to boot kernel... \n Booting kernel... \n console [ttyJ0] enabled \n bootconsole [early0] disabled \n Freeing unused kernel memory: 176K (80204000 - 80230000) \n # \n\n\n\nA shell is run as init in the early root-fs. The early root-fs is the compiled klibc project.\n\nAfter running the command dmesg the following output is displayed:\n\n\n\n Linux version 3.16.0 (alek@duke) (gcc version 4.9.1 (GCC) ) #4 Mon Aug 11 23:49:07 CEST 2014 \n bootconsole [early0] enabled \n CPU0 revision is: 00000230 (R3000A) \n Determined physical RAM map: \n memory: 08000000 @ 00000000 (usable) \n Initrd not found or empty - disabling initrd \n Zone ranges: \n Normal [mem 0x00000000-0x07ffffff] \n Movable zone start for each node \n Early memory node ranges \n node 0: [mem 0x00000000-0x07ffffff] \n On node 0 totalpages: 32768 \n free_area_init_node: node 0, pgdat 80203600, node_mem_map 81000000 \n Normal zone: 256 pages used for memmap \n Normal zone: 0 pages reserved \n Normal zone: 32768 pages, LIFO batch:7 \n Primary instruction cache 2kB, linesize 4 bytes. \n Primary data cache 2kB, linesize 4 bytes. \n pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 \n pcpu-alloc: [0] 0 \n Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 \n Kernel command line: console=ttyJ0,115200 \n PID hash table entries: 512 (order: -1, 2048 bytes) \n Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) \n Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) \n Memory: 127492K/131072K available (1741K kernel code, 101K rwdata, 212K rodata, 176K init, 171K bss, 3580K reserved) \n SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 \n NR_IRQS:128 \n Console: colour dummy device 80x25 \n Calibrating delay loop... 48.74 BogoMIPS (lpj=243712) \n pid_max: default: 32768 minimum: 301 \n Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) \n Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) \n futex hash table entries: 256 (order: -1, 3072 bytes) \n io scheduler noop registered \n io scheduler deadline registered \n io scheduler cfq registered (default) \n ttyJ0 at MMIO 0x1ffffff0 (irq = 3, base_baud = 0) is a Altera JTAG UART \n console [ttyJ0] enabled \n bootconsole [early0] disabled \n Freeing unused kernel memory: 176K (80204000 - 80230000) \n\n\n\n\n \n\n\n \n \n \n\n===== \n License =====\n\nMost of the files in this project are under the BSD license. All the Verilog code for the aoR3000 core is under the BSD license.\n\nA few files are under the GPL license. These files are:\n\n all files in the sim/vmips/ directory;\n all files in the linux/ directory;\n\n\nSee the LICENSE file for details." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - alfik name: aor3000 status: Beta svn-updated: Aug 12, 2014 updated: Aug 12, 2014 wishbone-compliant: 0 - category: Testing / Verification created: Apr 14, 2011 description: "===== \n Description =====\n\nProject was moved to 'Generic APB master stub'.\nThis is an obsolete project. Should be removed." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: apb_master status: Empty updated: Apr 17, 2011 wishbone-compliant: 0 - category: Testing / Verification created: Apr 14, 2011 description: "===== \n Description =====\n\nGeneric APB master stub. Based on an AXI master stub and an AXI2APB bridge. Supports both APB and APB3 protocols (APB3 is with pready and pslverr signals). The design is built according to input parameters: address bits, protocol type, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: apb_mstr status: Alpha svn-updated: Jul 3, 2011 updated: Aug 3, 2014 wishbone-compliant: 0 - category: Testing / Verification created: Apr 14, 2011 description: "===== \n Description =====\n\nGeneric APB slave stub. Support both APB and APB3 protocols (APB3 is with pready and pslverr). Supports slave error, random and fixed wait-states. The design is built according to input parameters: address bits, protocol type, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: apb_slave status: Alpha svn-updated: Jul 3, 2011 updated: Apr 22, 2011 wishbone-compliant: 0 - category: Communication controller created: Jan 19, 2014 description: "===== \n Description =====\n\nThe aim of this IP is to provide those who use it the possibility and reading and writing in an external interface for analog devices. Porting APB ARM, offering the possibility of integration with ARM processor in general." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - redbear name: apbi2c status: Alpha svn-updated: May 23, 2014 updated: Dec 15, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Sep 9, 2014 description: "===== \n Description =====\n\nThis is crypto core with AMBA support APB based on datasheet fom AES_SPEC If you liked our work is want to help contribute to the future progress of others who have seen help us by donating.\n\n\n\n\n\n\n\n\n\n\n\n\n\n GITHUB : git clone https://github.com/red0bear/AES128\n\n\n\n\n\n\n\n \nGLADIC is a group of people working with integrated circuits in Latin America that have done some work with integrated circuits or participated in training in the part of the digital flow. We hope that our IPs are also vital in any way the proposal for those who want to use it and it goes to silicon. We encourage anyone to make a donation to the OpenCores to offer this opportunity to people to disclose their work and promote the development of microelectronics area.\n\n\n\n\n\n\n\n About IP \n\n\n\n\n\n\nThis IP was developed in order to:\n\n\n\n\n\n Concepts acquired in training in the digital stream\n Integration with free software\n Different forms of functional verification\n Projects aimed at ASIC\n IP facing low density - average\n Promoting microelectronics interested people on Latin America\n Teamwork\n\n\n\n\n\nThis block consists of an encryption and decryption core that have the ECB mode, CBC, CTR. These modes have different types of jobs that are described in the above referenced manual. Each of these modes possesses other sub modes that are encryption / decryption / key generation / decryption with derivative of the original key. Also possesses configuration modes for switching / errors / DMA which is done through the configuration register. During processing in any way you can tell been reading another register that indicates the current state that the IP.\n\n\n\n\n\n\n\n Additional information \n\n\n\n\n\n FPGA MODEL USED\n \n xc3s500e-4ft256 OBS: This is only by software on ISE 14.7\n \n AMOUNT CELLS USED \n\n \n Logic Utilization\n Used\t\t\n Available\n Utilization\n \n \n Number of Slices\n 2383\n 4656\n 51%\t\n \n \n Number of Slice Flip Flops\t\n 2134\n 9312\n 22%\n \n \n Number of 4 input LUTs\n 3901\n 9312\n 41%\n \n \n Number of bonded IOBs\n 79\n 190\n 41%\n \n \n Number of GCLKs\n 1\n 24\n 4%\n \n\n MAXIMUM FREQUENCY\n \n Minimum period: 14.405ns (Maximum Frequency: 69.421MHz)\n \n\n\n\n\n IP verification \n\n\n\n\n\n\nAs the OpenCores encourages the use of free tools to check RTL so I decided to use the vpi / pli interface with C / C ++ in icarus verilog simulator to perform functional verification AES 128. The preparation of the verification environment was to plan test cases that validate each of the features developed by design. These cases mounted on the environment are individual tasks that enabled individually configure the DUT so that each cycle their outputs meet the rules set out in understanding the verifier.\n\n\n\n\n\n\n\n Finally a monitor to capture information and evaluate the result as the outputs are valid according the values already known. This environment does not have code coverage then there is no way to access how much code has been covered so far. We have the follow test cases:\n\n\n\n\n\n AES_WR_ONLY\n \n Checks for change in registers without the the bit that enabled the core to carry out a particular task is set.\n Only 1 type of test without variation of the configuration register.\n \n AES_WR_ERROR_DINR_ONLY \n \n Verifies that change in the status register and other signs depending on the value in the configuration register.\n There are 233 valid test possibility.\n \n AES_WR_ERROR_DOUTR_ONLY\n \n Verifies that change in the status register and other signs depending on the value in the configuration register.\n There are 233 valid test possibility.\n \n ECB_ENCRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for encryption and wait until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n There are 12 possible valid tests.\n \n ECB_DECRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for decryption and waits until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n There are 12 possible valid tests.\n \n ECB_KEY_GEN REGISTER / DMA / CCFIE \n \n Set the DUT for key generation and expects the status register / CCFIE is set. DMA has no effect as it is feature is only valid when it involves the DINR / DOUTR registers.\n There are 3 possible of valid tests.\n For configuration involving DATATYPE field is valid only DOUTR / DINR.\n \n ECB_DERIVATION_DECRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for decryption and derivation of the original key and wait until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n There are 12 possible valid tests.\n \n CBC_ENCRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for encryption and wait until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n Register IV is used in this mode.\n There are 12 possible valid tests.\n \n CBC_DECRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for decryption and waits until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n Register IV is used in this mode.\n There are 12 possible valid tests.\n \n CBC_KEY_GEN REGISTER / DMA / CCFIE\n \n Set the DUT for key generation and expects the status register / CCFIE is setados. DMA has no effect as it is feature is only valid when it involves the DINR / DOUTR registers.\n Register IV is used in this mode.\n There are 3 possibilities of valid tests.\n For configuration involving DATATYPE field is valid only DOUTR / DINR.\n \n CBC_DERIVATION_DECRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for decryption and derivation of the original key and wait until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n Register IV is used in this mode.\n There are 12 possible valid tests.\n \n CTR_ENCRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for encryption and wait until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n Register IV is used in this mode.\n There are 12 possible valid tests.\n \n CTR_DECRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for decryption and waits until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n Register IV is used in this mode.\n There are 12 possible valid tests.\n \n CTR_KEY_GEN REGISTER / DMA / CCFIE\n \n Set the DUT for key generation and expects the status register / CCFIE is setados. DMA has no effect as it is feature is only valid when it involves the DINR / DOUTR registers.\n Register IV is used in this mode.\n There are 3 possibilities of valid tests.\n For configuration involving DATATYPE field is valid only DOUTR / DINR.\n \n CTR_DERIVATION_DECRYPTION REGISTER / DMA / CCFIE\n \n Set the DUT for decryption and derivation of the original key and wait until the status register / DMA / CCFIE is set. Once the operation is finished reading the result and sets the block to reset it to wait for the next operation.\n Register IV is used in this mode.\n This mode is forbidden for CTR and this configuration is setted the configuration register must be changes for decryption.\n There are 12 possible valid tests.\n \n SUFLE_TEST\n \n This is to be used to check all cases tests with random data only.\n There are 233 valid test possibility\n \n RESET\n \n Implements random resets at certain times during the execution of any BFM.\n Reset entire environment.\n \n\n\n\n\n TOTAL TESTS : 583 tests made till now. Obs: im not counting resets and sufle yet." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - redbear - julioamerico name: apbtoaes128 status: FPGA proven svn-updated: Apr 6, 2015 updated: Mar 9, 2015 wishbone-compliant: 0 - category: Processor created: Jul 12, 2003 description: "===== \n Document =====\n\nAquarius Brochure (40KB)\nAquarius Detail Document (1.1MB)\n \n\n\n \n \n \n\n===== \n Description =====\n\nAquarius is a Core IP (Intellectual Property) of pipelined RISC CPU and can execute SuperH-2 instructions. Follows are SuperH characteristics. \n\n- SuperH is a very popular CPU core. The software development environments such as C compiler have been well prepared. The GNU C compiler for SuperH is very famous and easy to get. The SuperH had been developed by Hitachi, Ltd. Now, semiconductor group of Hitachi has merged with same group of Mitsubish and new semiconductor company ?gRenesas Technology Corp.?h has established in April, 2003. \n- SuperH-2 is a CPU for MCU (Micro Controller Unit). Then the CPU need not handle complex exception recovering such as memory fault exception from MMU (Memory Managing Unit). This means SuperH-2 has simple structure, easiness to design, and it does not consume many logic gates and power. \n- All SuperH-2 instructions have 16bit length. It also makes the hardware very simple. And most important aspect from 16bit fixed length of instructions is that the object code size compiled from C source programs becomes very small. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Instruction set is compatible with SuperH-2. \n- Bus interface is compatible with WISHBONE. \n- Aquarius is written in Verilog RTL codes. \n- Aquarius has verified on a test bench by vector simulation and FPGA implementation with GNU Assembler and C Compiler. \n- Interrupts and Exceptions are fully supported. \n- Low Power Mode (SLEEP) is supported. \n- Some small applications are provided including debugging monitor for a FPGA board. \n- A complete Document with over 100 pages, describing Usage of Aquarius, FPGA Implementation and Inside Aquarius, is provided. \n \n\n\n \n \n \n\n===== \n IMAGE: cpublock.gif =====\n\nFILE: cpublock.gif\nDESCRIPTION: CPU Block Diagram\n\n \n\n\n \n \n \n\n===== \n Inside CPU =====\n\nTop layer of Aquarius is ?gCPU?h which has WISHBONE compliant bus signals and accepts interruption related signals. The most important system signals such as clock and reset are not shown in this figure.\n\nThe Memory Access Controller handles instruction fetch and data read/write access. The operations of Memory Access Controller are fully controlled by Decoder unit. Memory Access Controller sends fetched instruction bit fields to the Decoder unit, and interchanges read/write data and its address with Data Path unit. Aquarius assumes the Wishbone bus is a Non-Harvard bus, then the simultaneous instruction fetch and R/W data access makes bus contention. Memory Access Controller handles such contention smoothly and informs the pipeline stall caused by the bus contention to Decoder unit. Also, the Memory Access Controller can sense each boundary of bus cycles (with wait state) from WISHBONE ACK signal. In Aquarius architecture (may be in SuperH-2 architecture as well), such bus cycle boundary corresponds to the pipeline?fs slot edge. So the Memory Access Controller produces the most important pipeline control signal ?gSLOT?h indicating pipeline slot edge.\n\nThe Data Path unit has registers you can see in programmer?fs model in SuperH-2 manual such as General Registers (R0 to R15), Status Register (SR), Global Base Register (GBR), Vector Base Register (VBR), Procedure Register (PR) and Program Counter (PC). The Multiplication and Accumulate Registers (MACH/MACL) are found in Multiplication unit. The Data Path unit also has necessity operation resources such as ALU (Arithmetic and Logical operation Unit), Shifter, Divider, Comparator, temporary registers, many selectors, interfaces to/from Memory Access Controller and Multiply unit, and several buses to connect each resource. The Data Path is fully controlled by control signals from Decoder unit. \n\nMultiplication unit has a 32bit x 16bit multiplier and its control circuits. A 16bit x 16bit multiplication operation is executed in one clock cycle. A 32 bit x 32bit multiplication operation is done in two clock cycles. Multiplication unit also has the Multiplier and Accumulate Registers (MACH/MACL). The MACH/MACL are not only the final result registers of multiply or multiply-and-accumulation but also the temporary registers to hold the 48bit partial multiply result from 32bit x 16bit multiplier for 32bit x 32bit operation. The multiply instruction, for example MULS.L, clears the contents of MACH/MACL in early stage of the instruction operation. However the multiply and accumulate instruction, for example MAC.L, does not clear MACH/MACL before the operation. The MAC.L accumulates its own partial multiply result to initial MACH/MACL and then finalize the operation result. The major difference between multiply (MULS.L) and ?gmultiply and accumulate?h (MAC.L) is whether to clear or not to clear the MACH/MACL before the operation. And also, for MAC.L and MAC.W instruction, the accumulation adder in this unit has saturating function.\n\nThe Decoder unit is the fundamental CPU controller. It orders Memory Access Controller fetch instructions and then receives the instruction. The Decoder Unit decodes the instruction bit fields and judges the followed operations. Basically, the Decoder unit plays the role only for the instruction ID stage. But it throws many control signals for following EX, MA and WB stages toward Data Path unit, Multiplication unit, and Memory Access Controller. These control signals are kept and shifted with its pipeline flow at each slot edge until reaching to the target stage of the instruction. The Decoder unit detects every conditions of pipeline stalling, and makes each unit of CPU be controlled properly. Also, it controls not only simple 1 cycle instructions but also multi cycle instructions and exception?fs sequences such as interrupt and address error. \n \n\n\n \n \n \n\n===== \n Status =====\n\n- RTL coding and verifying have already been finished. \n- FPGA (Xilinx VirtexE) implementation with LCD, Matrix Keyboard and RS-232C interfaces has also finished using GNU Assembler and C Compiler.\n- Some small Applications using FPGA and its interface board have finished.\n- Detail Design Document has finished.\n \n\n\n \n \n \n\n===== \n Deliverables =====\n\n- Verilog RTL codes for CPU, and Test Bench including modules comprising MCU, such as UART, System Controller, Parallel I/O Interface, and Internal Memories (ROM/RAM). \n- Verification Resources, such as Converter from S-format to Verilog format for ROM coding, and Assemble Source Programs for Vector Simulation. \n- FPGA Resources, such as Circuit Schematics of Interface Board, Converter from S-format to Xilinx BlockRAM INIT statements for RAM initialization, and a sample of User Constraints File. \n- Small Applications written in C Sources including LCD Test Program, Clock using interval interrupt, Debugging Monitor, and Calculation of Circular Constant (Pi). \n \n\n\n \n \n \n\n===== \n IMAGE: rtl.gif =====\n\nFILE: rtl.gif\nDESCRIPTION: Tree of RTL\n\n \n\n\n \n \n \n\n===== \n Download =====\n\nDocuments, RTL Source codes and related Tools can be downloaded from the OpenCores CVS; the directory is \"Aquarius\".\n \n\n\n \n \n \n\n===== \n Performance =====\n\nAquarius CPU core and related peripheral modules have been configured in both Xilinx and Altera. Following table shows their performance.\n\n\n \n \n \n\n\n FPGA Device\n \n \n\n\n Performance(cpu.v)\n \n \n \n \n Xilinx VirtexE (XCV300E)\n \n \n \n 2753 slices @21MHz\n \n \n \n \n Altera Stratix (EP1S10)\n \n \n \n 7499 cells @31MHz\n \n\n \n\n\n \n \n \n\n===== \n Links =====\n\nAquarius has adpoted as a showcase of Soc Emulator developped by Edaptability ! \nhttp://www.edaptability.com/emulator.htm \nhttp://www.edaptability.com/home.htm \n\nRenesas Technology Corp.\nhttp://www.renesas.com/ \n\nSuperH Family\nhttp://www.renesas.com/eng/products/mpumcu/32bit/sh/index.html \n\nHuMANDATA Ltd.\nhttp://www.hdl.co.jp/home.html \n\nSchematic of FPGA Board\nhttp://www.hdl.co.jp/ftpdata/xsp-009/XSP009.sch.pdf \n\nSUNLIKE Displays Tech Corp.\nhttp://www.lcd-modules.com.tw/ \n\nLCD SC-1602B Datasheet\nhttp://www.lcd-modules.com.tw/data/SC/SC1602B.pdf \n\nLCD Timing\nhttp://www.lcd-modules.com.tw/data/SU/P32.pdf \n\nLCD Display Commands\nhttp://www.lcd-modules.com.tw/data/SU/P33.pdf \n\nLCD Initialization\nhttp://www.lcd-modules.com.tw/data/SU/P34.pdf \n\nAnalog Devices Inc.\nhttp://www.analog.com/ \n\nRS-232C PHY\nhttp://www.analog.com/UploadedFiles/Data_Sheets/452317841ADM222_32A_42_a.pdf \n \n\n\n \n \n \n\n===== \n IMAGE: fpgaboard.gif =====\n\nFILE: fpgaboard.gif\nDESCRIPTION: FPGA Board" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - thorn_aitch name: aquarius status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 6, 2012 wishbone-compliant: 1 - category: Processor created: Mar 31, 2014 description: "===== \n Description =====\n\nThis processor, done as an university project, is a functional clone of the ARM processor, is almost entierely compatible with the ARMv3 instruction set and can be targetted by the GCC toolchain if the proper options are used during the compilation process.\n\nThe processor uses a classical 5-stages RISC pipeline and an instruction cache. It was made to connect to the Altera Avalon bus, as a Q-Sys compatible component. It should however be simple to retarget it for other similar buses.\n\nWe made it run at 50 MHz on a Cyclone IV FPGA.\nFull VHDL sources, schematics and documentation is included." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - Bregalad name: arm4u status: FPGA proven svn-updated: May 2, 2014 updated: May 2, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jan 22, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: SystemC license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: arm_virtual_platform status: Empty updated: Jan 23, 2011 wishbone-compliant: 0 - category: Prototype board created: Nov 4, 2008 description: "===== \n Planned Features =====\n\n- LPC ROM(RAM?)\n - Flash regions Memory read, Firmware hub read, (IO read and write)\n - PSRAM regions Memory read and write, Firmware hub read, (IO read and write)\n- SPI ROM\n - Flash regions read\n - PSRAM regions read\n- 8 bit ROM\n - read (with standard CS, OE, WE, DATA, ADDR interface on the 32 extension pins)\n- Post code trace\n- Boot trace (list all memory cycles possible at least on LPC)\n- Simple Logic Analyzer with 32 pins and 32 pin GPIO python module support\n- VHDL Firmware update trough USB data cable\n\n \n\n\n \n \n \n\n===== \n IMAGE: Dongle_II_board_small.JPG =====\n\nFILE: Dongle_II_board_small.JPG\nDESCRIPTION: board image\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nDONE\n\n- code transfer from Dongle I\n- PSRAM support added to memory interface and USB interface (4MB write time is 4 sec under Linux read is 10 sec)\n- New jumper block with LED indicators\n- dongle.py updated for initial features\n- dev_present signal switching from PC by default is low (has strong pull down 330 ohm for backward compatibility)\n- removed the need for reset after programming to free memory bus lock (lock is now controlled by the dongle.py software) \n- Added UART 16550 support over LPC with selectable base addresses\n\nTODO\n\n- Write multi-clock domain scalable memory bus arbiter (firmware)\n- SPI boot support (firmware)\n- 8 bit parallel ROM support code (firmware)\n- write GPIO support (firmware) and supporting Python module (software)\n- boot trace feature (save all accessed addresses and data and send to PC) (firmware)\n- write new update.py to work trough FTDI D2xx bit bang feature (software)\n- write 16 bit to 8 bit FIFO bridge to further speed up USB transfer on PSRAM regions (firmware)\n- try to rewrite Uspp read() in linux implementation to support more than word read at a time from OS (software)\n- write EPROM support code (firmware)\n- write software jumper support with settings stored/restored from EPROM (firmware)\n- write or port Analyzer code (firmware) \n \n\n\n \n \n \n\n===== \n Description =====\n\nProject to create generic emulator/debugger/analyzer with\non-the-fly reprogrammable firmware on Artec Dongle II board (containing Altera Cyclone III, Flash 16MB, PSRAM 16MB (UltraCap for image retention), FTDI usb, 32 GPIO pins, 4 segment LED, 8 green LEDs, 1 green/red LED, 8 pins for LPC/SPI bus, 6 pin extension header, EPROM 1024 bytes)." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - nuubik - mraudsepp name: artec_dongle_ii_fpga status: Stable svn-updated: Mar 5, 2012 updated: Mar 5, 2012 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/artificial-intelligence-system-r3.tar category: Other created: Mar 31, 2012 description: "===== \n Description =====\n\nThe Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time celullar and sub-cellular biological processes." language: VHDL license: custom licensetext: "The AISystem files have a dual license depending on its intended use: \n- LGPL for research and all other non-commercial applications\n- special license for commercial applications\n\nIf you would like to incorporate this work into a commercial applications please contact the developers. \n\nThe reason for dual license is to ensure that the work done will not find its way in a commercial system\nwithout a company paying royalties to the developers for the hard work done. \n" maintainers: - oviang name: artificial-intelligence-system status: Alpha svn-updated: Apr 4, 2012 updated: Mar 31, 2012 wishbone-compliant: 0 - category: Processor created: Dec 13, 2002 description: "===== \n Description =====\n\nThe ASPIDA project has implemented an asynchronous IP of the DLX Instruction Set Architecture (ISA) with incorporated support for ISA conversion so it can be easily converted to any RISC ISA. The DLX architecture, is well-supported by existing software development tools (compiler, assembler, loader, instruction set simulator and debugger).\n\nThe synchronous single-pipeline architecture, which is standard for the basic synchronous DLX implementations, is identical to the architecture of the asynchronous version. A suitable Open IP interface (WISHBONE) is embedded onto the processor to enable it to be integrated into any Open IP SOC system. In addition, the ASPIDA project issues a new Open IP interface standard based on asynchronous technology (CHAIN), and support for this new Open IP interface is also embedded onto the processor core.\n\nA design flow that is based as much as possible on existing EDA tools for all design steps, and which is part of the background technology brought in by the partners, has been used in order to produce a portable netlist, and to distribute all the intermediate HDL files used for high-level and gate-level design. The final product is technology-independent and timing-independent and in a form suitable for integration using only standard, industrial tools and flows, with no dependence on asynchronous tools and specific knowledge of asynchronous design for potential end users.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Technology-portable processor core\n- Fully-asynchronous core for low-power, low-EMI\n- Industrial-quality testability (internal scan)\n- WISHBONE interface\n- Core includes additional novel asynchronous bus, CHAIN (CHip Area INterconnect)\n- Targetted for ASIC EDA flows\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Project is completed\n- Fully Working FPGA Implementation is available on Xilinx Spartan 2E device\n- ASIC Implementation completed and tested\n- Download FAQ and all the sources and scripts from the project download section\n- Visit our ASYNC group web page at http://www.ics.forth.gr/carv/async" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - sotiriou name: aspida status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Communication controller created: Dec 19, 2010 description: "===== \n Description =====\n\nUsually, 8b/10b codec is required with using a fibre-optic SERDES interface.\nA SERDES converts fast serial optic-stream into less fast 10bit parallel electric-signals.\nEven though less fast electric-signals, that has almost or more 100Mhz speed.\nso the FPGA logic processing 8b/10b must have capable to terminate processing encode and decode with minimal delay.\nThis project provide you the VHDL code, processing 8b/10b enc/dec asynchronously.\nIt is implemented by a large lookup-table for better performance.\na lookup-table implementation can offer you with minimal deterministic inter delay.\nit can be used with clocked signals also, if you want.\nI tested this project with Xilinx XC3S50AN.\nXilinx tools produced the result using just two block-memory within XC3S50AN.\none block-memory is used for an encoder. another block-memory is used for a decoder each.\n\n************************************\n\nOh!. I find my bad..\nThis project can offer async 8b/10b enc/dec, but not use a block-memory.\na block-memory is needed to shrink logic-gates.\nI will change the title of this project soon.\n\n*************************************" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - redblue2000 name: async_8b10b_encoder_decoder status: Planning svn-updated: Apr 23, 2011 updated: Dec 1, 2011 wishbone-compliant: 0 - category: System on Chip created: May 9, 2011 description: "===== \n Description =====\n\nAsynchronous Spatial Division Multiplexing Router for On-Chip Networks\n\nVersion: 0.2 \n\nOn-chip networks or networks-on-chip (NoCs) are the on-chip communication fabric for\ncurrent and future multiprocessor SoCs (MPSoCs) and chip multiprocessors (CMPs).\nCompared with synchronous NoCs, asynchronous NoCs have following benefits:\n * Tolerance to all kinds of delay variations caused by process, power and temperature\n variations.\n * Low transmission latency.\n * Zero dynamic power when idle.\n * Unified sync/async interface and easy clock domain integration.\n\nMost NoCs use the wormhole flow control method. Many complex flow control methods are\nbuilt upon the wormhole method, such as virtual channel (VC), TDMA, and SDM. VC is the\nmost utilized flow control in both sync and async NoCs. However, it is found VC\ncompromises the throughput performance of asynchronous NoCs. This project provides a new\nasynchronous router structure which use SDM rather than VC. It has been shown that SDM\nachieve better throughput than VC in the same router configuration.\n\nThis project provide a reconfigurable asynchronous SDM router which can be configured\ninto a basic wormhole router or an SDM router with multiple virtual circuits in every\ndirection. \n\nFeatures:\n * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)\n * The dimension order routing (XY routing)\n * Available flow control methods: wormhole, SDM, VC\n * Reconfigurable number of virtual circuits, buffer size, data width\n * Fully synthesizable router implementation\n * SystemC testbench provided\n\nLanguages:\n * Routers are written in synthesizable SystemVerilog\n * Test benches are provided by SystemC \n\nSoftware requirements:\n * The open source Nangate 45nm cell library\n * Synopsys Design Compiler (Synthesis)\n * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - wsong0210 name: async_sdm_noc status: ASIC proven svn-updated: May 31, 2013 updated: Jun 8, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Nov 29, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - BSGSOMANATH name: asynchronous_fifo status: Empty updated: Nov 30, 2013 wishbone-compliant: 0 - category: System controller created: Sep 25, 2001 description: "===== \n Description =====\n\nATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface.\nThe ATA interface provides a simple interface to (low cost) non-volatile memories, like harddisk drives, DVD players, CD(ROM) players/writers and CompactFlash and PC-CARD devices.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Three cores are available in VHDL and Verilog from OpenCores CVS via cvsweb or via cvsget. \n- ToDo: \n - Write documentation \n - Start development of OCIDEC-4, featuring UltraDMA support\n \n \n\n\n \n \n \n\n===== \n Development goals =====\n\nThe development of a range of software and function backward compatible cores with a growing set of features. Software can detect which version of the core is implemented by reading the Device-ID and Revision-Number from the status register, thus making it possible to use a single device driver to handle all cores. This gives designers/system integraters the ability to trade off complexity/resource usage to available feature set/performance. All cores are designed according to the latest ATA/ATAPI specs.\n\n\n\nCurrently three cores are available:\n\n\n\n\n\nDevice\n\nOCIDEC-1\n\n\nFeatures\n\nSmallest core.\nPIO transfer support only.\nSingle timing register for all accesses to the connected devices.\n\n\nIntended use\n\nSingle PIO only devices (PC-CARDs, CompactFlash).\nDesigns requiring ATA capabilities, without the need for a complex feature set.\n\n\nGate usage\n\nAltera ACEX EPF1k100FC484-1 262lcells@111MHz.\n\n\n\n\n\n\n\n\n\n\nDevice\n\nOCIDEC-2\n\n\nFeatures\n\nSmall core.\nPIO transfer support only.\nCommon timing register for all compatible accesses to the connected devices.\nSeparate timing register per device for fast DataPort accesses.\n\n\nIntended use\n\nDual PIO only devices (PC-CARDs, CompactFlash).\nDesigns requiring fast ATA capabilities, without DMA transfers.\n\n\nGate usage\n\nAltera ACEX EPF1k100FC484-1: 439lcells@111MHz.\n\n\n\n\n\n\n\nDevice\n\nOCIDEC-3\n\n\nFeatures\n\nPIO, Single-Word DMA and Multi-Word DMA transfer support.\nCommon timing register for all PIO compatible accesses to the connected devices.\nSeparate timing registers per device for fast PIO DataPort accesses.\nSeparate timing registers per device for DMA transfers.\nPIO write access ping-pong.\nWISHBONE Retry cycles for PIO accesses while controller busy.\n\n\nIntended use\n\nHigh speed ATA devices (Hard disks, CDROMs)\nDesigns requiring full featured ATA capabilities.\n\n\nGate usage\n\nAltera ACEX EPF1k100FC484-1 916lcells@84MHz.\n\n\n\nAll cores feature a WISHBONE rev.B2 compliant interface, but can be adapted to any other kind of bus.\nSee the on-line documentation for more information. \nNote: This is a preliminary version. Not an official release." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rherveille name: ata status: Stable svn-updated: Mar 10, 2009 updated: May 6, 2015 wishbone-compliant: 1 - category: Processor created: Mar 13, 2013 description: "===== \n Description =====\n\nWelcome to the Atlas Processor Core project!\n\n\n\n\nThe Atlas 2k Processor is intended to be a small 16-bit RISC general purpose processor for all kind of applications, that require minimal hardware resources while providing a maximum functionality and processing power. The instruction set was inspired by famous architectures like the ARM and AVR ISAs and many of you, who worked with these architectures, will see the resemblance. However, the CPU features a lot of additional nice features and functionalites, which - at least from my point of view - make a cool processor. ;)\nThe processor supports a flexible memory layout (with paging) and features several common communication interfaces (like SPI, UART and a Wishbone bus adapter) and peripheral devices like timer, interrupt controller and LFSR.\nAn integrated bootloader (2kB ROM) allows to select between several boot options (configuration via 2 external pins): \n\nBoot from UART (send image stream via serial console)\nBoot from / program external SPI EEPROM (Microchip 25LC512)\nBoot from internal memory (last image in RAM)\nBoot from Wishbone network device (only via bootloader console)\n\nThe Basic Setup (left image) provides a basic implementation of the processor together with an internal memory. The layout of the memory system can be individually configured via two VHDL constants to adapted to the needs of the application. This setup ist the perfect starting point for your design - just synthesize it, download it to your FPGA and begin exploring the Atlas 2k processor! :D\n\n\n\n\n\n\n\nFor more information about this project, take a look at the processor documentary: Atlas 2k Processor Documentary\n\n\n\n \n\n\n \n \n \n\n===== \n Processor Features =====\n\n\nTrue 16-bit RISC open source soft-core processor, 16-bit processing data, 16-bit memory addressing\nSmall outline\nCompletely written in behavioral, platform-independent VHDL\nPipelined instruction execution in 5 stages with full forwarding and hazard detection\nSingle cycle execution of all instructions (except for branches and multi-cycle (memory) operations)\nPowerful memory access and indexing instructions\nTwo different operating modes with unique register sets (8x 16-bit registers each) and privileges\nFull hardware support for emulating privileged-mode programs in unprivileged-mode\nTwo software interrupts/exceptions (system call, command error (instruction access violation))\nPowerful bit-manipulation operations\nIntegrated bootloader providing several boot options and functionalities\n\nBoot from UART / SPI EEPROM / internal memory / Wishbone device\nProgram SPI EEPROM\nRAM dump of any memory page\nDump words from Wishbone network\n\nInterface for external coprocessors to extend the processor's functionality\nSimple memory and coprocessor interface\nAssembler program to easily create and assemble application code\nIntegrated peripheral controller:\n\nHigh precision timer (32-bit)\nMemory management unit (supports paging) - 32 bit address space\nFlexible linear-feedback shift register (taps configurable) for pseudo random data\nInternal interrupt controller for up to 8 channels\n16+8 bit parallel input and 16+8 bit parallel output ports\nGeneral purpose SPI controller with variable transfer frame size, 8 individual channels\nConfigurable universal asynchronous receiver/transmitter (UART)\nWishbone bus master adapter (32-bit address, 16-bit data, pipelined burst transfer, packet size 1..32 16-bit words)\n\n\n\n\n \n\n\n \n \n \n\n===== \n Programmer Model =====\n\n\n\n\n\n\n\n\nARM thubb-like instruction set. All instructions are 16 bit wide. Arithmetical instructions use 3-register-addressing.\nThe CPU provides two different privilige modes: A privileged one (system mode) and an unprivileged one (user mode). Each mode has access to a register bank of 8x 16-bit register. When operating in system mode, data can also be transfered from or to the user register bank. R7 of each bank is used as link register to store the return address when calling subroutinesUser mode and system mode programs can access the program counter (PC) and the machine status register (MSR). The PC can be altered by both operating modes. System mode programs have full access to the MSR, but user mode programs can only alter the user ALU flags of the MSR, so an user mode program cannot alter the state of the host system. Both operations mode have also private sets of ALU status flags, so no context store at all is necessary when changing modes.When in system mode, the internal coprocesor and the optional external user processor can be accessed. When in user mode, only the external user processor can be accessed, but however, this access privilege can be deactivated, allowing only system mode programs to have access to the two coprocessor.Five interrupt/execption vectors are supported: 0: Hardware reset, 1: interrupt via the critical IRQ pin, 2: interrupt from the internal IRQ controller (supports another 8 IRQ channels), 3: command error trap, 4: software interrupt (system call).All instructions, that require system privileges, will cause an software interrupt when executed in user mode, allowing hardware-based emulation of system-mode programs in restricted user mode environment.\n\n\n\n\nI have tried to design the instruction set architecture as orthogonal as possible.All data processing instructions (arithmetical, logical, bit manipulation, transfer, ...) can be applied on any of the current mode's 8 data registers. All instructions of these classes feature three operand slots, making the Atlas CPU a three address-machine. For all arithmetical/logical instructions, the update of the status flags is optional.Data memory accesses can be performend unsig any register as pointer/data and as source/destination. Immediate and register-based offset addition/subtraction before or after the actual memory access is possible (pointer indexing). Also, a write back of a modified base address can be enabled.An application-specific coprocessor (EXTernal USER coprocessor) can be connected to the CPU to extend the core's functionality and processing power. Dedicated coprocessor transfer and data processing instructions are supported.The CPU features a power-saving sleep mode. Any enabled interrupt signal will wake up the CPU again (single cycle response time).Single cycle 32-bit multiplier. Instructions to get upper/lower 16-bit multiplication result.Conditional/unconditional immediate branch/call instructions can jump to a location within +255 and -256 instructions. Also, conditional relative/absolute register-based branches are implemented. The newest version also includes conditional register move instructions to accelerate conditional data transfer.For more details about the implemented instructions, see the Atlas 2k Processor Documentary.\n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Synthesis Results =====\n\nSynthesis (speed optimized) results for a Xilinx Spartan XC3S400A FPGA:\n\nXilinx Spartan XC3S400A\nAtlas 2k Processor Base Setup*\n\n\nNumber of Slices:\n1347 / 3584 = 37%\n\nNumber of 4 input LUTs:\n2406 / 7168 = 33%\n\nNumber of Slice Flip Flops:\n1091 / 7168 = 15%\n\nNumber of IOs:\n18\n\nNumber of BRAMs:\n11 / 20 = 55%\n\nNumber of MULT18X18SIOs:\n1 / 20 = 5%\n\nMaximum Frequency:\n81.252 MHz\n\n\n\n\nFull implementation (balanced optimization, slow 1200mV 0C model) results for an Altera Cyclone IV EP4CE22F17C6N FPGA:\n\nAltera Cyclone IV EP4CE22F17C6N\nAtlas 2k Processor Base Setup*\n\n\nTotal logic elements:\n2967 / 22320 = 13%\n\nTotal combinational functions:\n2692 / 22320 = 12%\n\nDedicated logic registers:\n1364 / 22320 = 6%\n\nTotal pins:\n18\n\nTotal memory bits:\n297984 / 608256 = 49%\n\nEmbedded Multiplier 9-bit elements:\n2 / 132 = 2%\n\nMaximum Frequency:\n99.11 MHz\n\n\n\nSynthesis results correspond to the project version from April 17th, 2014\n*) The default Base Setup includes 2kB bootloader ROM and 16kB (divided into 4 pages) internal RAM; for this synthesis\nI've added a 256-byte Wishbone RAM (directly connected) and reduced the number of IO pins (1x SPI (4), UART(2), SYS_IO (10), clk & reset (2))\n\n\n\n \n\n\n \n \n \n\n===== \n Application Software =====\n\nCurrently the Atlas 2k project includes only some example programs for the core:\n\nA simple blinking LED to get into the basics of the Atlas 2k assembler\nA random numbe rgenerator to play with the internal LFSR\nA Fast Fourier Transformation to impress you with the processing power... ;)\n... more to come\n\n\nYou have written some cool program for the Atlas 2k?\nGet in touch so we can add your code to the examples collection to share it with the community!\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n\nThe main processor rtl modules are completed and tested - maybe additional coprocessor modules will be added\nSome of the rarely used special options of some commands need a little bit more verification... ;)\nThe bootloader works fine can successfully boot an image from any source\nAll example programs run without problems\nProcessor specification completed, but might be updated with additional information in future\nAssembler program is working and will be further improved\nThe 'Atlas 2k Base Setup' features a ready-to-start implementation of the processor - FPGA proven\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Contact =====\n\nIf you have any questions about the Atlas project or if you want to give any kind of feedback, feel free to drop me some lines ;)\n\nStephan Nolting: stnolting@gmail.com" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - zero_gravity name: atlas_core status: FPGA proven svn-updated: Dec 18, 2014 updated: Dec 20, 2014 wishbone-compliant: 1 - category: Arithmetic core created: Apr 1, 2010 description: "===== \n Description =====\n\nAudio Codec(ADPCM 1-Bit) \nThe code is ready for Altera Cyclone-II DE1 Starter board and it is tested, you can modify codes and use them in any project. \n\nCore Description: \nSampling Frequency: 44100Hz \nChannels: Stereo \nBit-rate: 1 Bit Per Sample(So it is: 44.1 * 2 = 88.2kbps) \nCompression Ratio: 16:1 \n\nVHDL code consists: \n1-bit ADPCM Decoder(x2), I2S Driver(x1), I2C Driver(x1), Flash Memory Driver(x1), Keyboard Driver(x1), LED Bar(x1), Volume and Config Engine(x1). \n\nCodec(Encoder/Decoder) is available in Win32 application that you can use it to encode PCM RAW wave files, then burn the *.DJ file into the flash, make sure the flash is already clear(you can use the EDK control panel to clear and program the flash) and run the code on FPGA. \n\nThere is no patent or copyright, it's free for everyone to use in any project. \n\n(if you need the Encoder in VHDL, contact me by e-mail.)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ashematian name: audio status: Stable svn-updated: May 12, 2010 updated: May 22, 2011 wishbone-compliant: 0 - category: Communication controller created: Sep 17, 2002 description: "===== \n Description =====\n\nThis module scans an incoming stream of rs232 serial characters. It constantly looks for a new character, which it detects by seeing the \"start\" bit. When a condition resembling a start bit is detected, the module then begins a measurement window, to try and determine the BAUD rate of the incoming character. Since many different characters have different bit transitions because of their different data content, this module actually only \"targets\" a single character -- in this case the \"carriage return\" character (0x0d). How can it tell if the character is the carriage return?\n\nWell, once it finishes the measurement interval (first 2 bits of the received character) then it uses the measurement to produce a BAUD rate clock. The module uses this BAUD rate clock internally to verify the remaining 8 bits in the serial character (total of 10 bits per received character, including start/stop bits. Parity is supported, but has never been tested.)\n\nIf the remainder of the character verifies correctly to be a carriage return character, the measurement is accepted as valid, and the module then produces the BAUD rate clock externally, and flags that it has \"locked\" onto the BAUD rate of the incoming characters.\nThere are two versions of this module: One for a single lock at the beginning of the session, which is then maintained for the entire duration of the session (this one is called \"auto_baud.v\"). And another version constantly tracks the incoming characters, which allows for changes in the clock rate and/or BAUD rate of incoming characters to happen at any time, and the BAUD rate will adjust as soon as the carriage return character is detected (this one is called \"auto_baud_with_tracking.v\") Because of the extra logic needed to produce a BAUD rate while checking a possible new BAUD rate at the same time, the tracking version is slightly larger than the \"single lock\" version, and it will work with faster clock speeds.\n\nThe auto_baud generator is intended for use in \"human interface\" rs232 serial applications. It has also been tested with \"text file transfer\" in hyperterm and SecureCRT terminal programs, to see if it would function during higher speed character transfer, and it worked just fine.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Tested in Xilinx XC2V200 hardware, no simulation available.\n- Test results, and documentation given in code header comments.\n- A PC using \"hyperterm\" and \"SecureCRT\" was used for testing.\n- \"auto_baud.v\" consumes 59 slices and works up to 87 MHz (no constraints.)\n- \"auto_baud_with_tracking.v\" consumes 93 slices, operates up to 102 MHz (no constraints.)\n- Code is written in Verilog and VHDL. Both versions have been tested.\n- Default parameter settings work from 300 BAUD up to 115200 BAUD with any FPGA board clock between 30 MHz and 100 MHz.\n- Clock speeds lower than 30 MHz support lower BAUD rates, like 9600. See code for details.\n- The new VHDL version is a package file in the SVN repository trunk.\n- Fully parameterized module.\n- Will operate just fine with \"non standard\" BAUD rates -- such as MIDI (musical instrument digital interface.) No calculations required.\n- Works with \"rs232_syscon\" for an easier bring up of debugging sessions." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jclaytons name: auto_baud status: Stable svn-updated: Mar 11, 2013 updated: Mar 11, 2013 wishbone-compliant: 0 - category: Processor created: Jul 30, 2010 description: "===== \n Description =====\n\nThis CPU project does not implement fully AVR compatible core. \nInstead it realizes very minimal functionality.\nTask was to make kind of CPU that can fit into very small CPLD (Altera's EPM240T100C5) and still leave some space for other logic.\nDevelopment platform was choosed opensource \"Marsohod\" board. About this board You can read more on http://www.marsohod.org/index.php/howtostart/plata but it is Russian idea and pages. This board is dedicated for education, hobbies, creating electronic toys etc.\n\nBoard has 4 buttons, 8 LEDs, 2 step motor control sockets.\n\nIn AVR8 project we had implemented:\n\t1) only four general purpose registers r16..r19;\n\t2) general purpose register r20, bits connected to 8 LEDs of board\n\t3) general purpose register r21, bits connected to 6 step motor output pins\n\t4) read only register r22, low 4 bits read status of 4 board buttons.\n\nThus, no i/o ports, no timers, interrupts and other AVR features.\nAnyway somehow this core is partly compatible to real microcontroller.\nAltera's CPLD has User Flash Memory, so called UFM. It is organased as 512 words 16 bits each.\nSo AVR program can be stored there.\n\nProject implements following AVR instructions:\n-----------------------------------------------\nADD 0000 11rd dddd rrrr\nSUB 0001 10rd dddd rrrr\n\nAND 0010 00rd dddd rrrr\nEOR 0010 01rd dddd rrrr\nOR 0010 10rd dddd rrrr\nMOV 0010 11rd dddd rrrr\n\nCP 0001 01rd dddd rrrr\nLSR 1001 010d dddd 0110\n\nSUBI 0101 KKKK dddd KKKK\nANDI 0111 KKKK dddd KKKK\nORI 0110 KKKK dddd KKKK\nCPI 0011 KKKK dddd KKKK\nLDI 1110 KKKK dddd KKKK\n\nBREQ 1111 00kk kkkk k001\nBRNE 1111 01kk kkkk k001\nBRCS 1111 00kk kkkk k000\nBRCC 1111 01kk kkkk k000\n-----------------------------------------------\nLetter \"d\" encodes destination register.\nLetter \"r\" encodes source register.\n\"k\" encodes immediate values.\n\nCore also inmpelemnts only two flags \"Z\" and \"C\".\nCorresponding conditional jumps BREQ, BRNE, BRCS, BRCC were realized.\nNo real jumps of subrotine calls, no memory.\n\nAs resources are extremelly limited, \nseems this cannot work, but test program was written in ATMEL AVRStudio.\nTest application polls board buttons and blinks board LEDs accordingly.\n\nTest application is that:\n\n.include \"1200def.inc\"\n.device AT90S1200\n\n.cseg\n.org 0\n\nstart:\n\n;initial one bit in register\nldi r16,$80\n\nrd_port:\n\n;read port (key status)\nmov r17,r22\ncpi r17,$0f\n;go and blink one LED if no key pressed\nbreq do_xor\n\ncpi r17,$0e\n;go and right shift LEDs if key[0] pressed\nbreq do_rshift\n\ncpi r17,$0d\n;go and left shift LEDs if key[1] pressed\nbreq do_lshift\n\n;jump to read keys\nor r16,r16\nbrne rd_port\n\ndo_rshift:\ncpi r16,1\nbreq set80\nlsr r16\nmov r20,r16\nbrne pause\nset80: \nldi r16,$80\nmov r20,r16\nor r16,r16\nbrne pause\n\ndo_lshift:\ncpi r16,$80\nbreq set1\nlsl r16\nmov r20,r16\nbrne pause\nset1: \nldi r16,$01\nmov r20,r16\nor r16,r16\nbrne pause\n\ndo_xor:\neor r20,r16\n\npause:\nldi r18,$10\ncycle2:\nldi r19,$FF\ncycle1:\nor r19,r19\nor r19,r19\nsubi r19,1\nbrne cycle1\nsubi r18,1\nbrne cycle2\n\nor r16,r16 \nbrne rd_port" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - marsohod name: avr8 status: Beta svn-updated: Jul 30, 2010 updated: Aug 29, 2010 wishbone-compliant: 0 - category: Processor created: Nov 5, 2002 description: "===== \n Description =====\n\nMicrocontroller core compatible with one used in AT mega 103 and written in VHDL. It has the same instruction timing and the same instruction set (with a few exceptions).\n \n\n\n \n \n \n\n===== \n Features =====\n\n\xE2\x80\xA2 Core features:\n\xE2\x80\x93 32 x 8 general purpose registers\n\xE2\x80\x93 Twenty three interrupt vectors\n\xE2\x80\x93 Supports up to 128 Kb of program and up to 64 Kb of data memory\n\n \xE2\x80\xA2 Peripheral features:\n\xE2\x80\x93 Programmable UART\n\xE2\x80\x93 Two 8-bit Timer/Counters with separate prescalers and PWM\n\xE2\x80\x93 Eight external interrupt sources \n\xE2\x80\x93 Two parallel ports\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe core was tested with several ASM and C programs.\nIt was implemented in Altera EPF10K50ETC144-3 device and \ntested with AVR port of uC/OS-II The Real-Time Kernel, written by Ole Saether.(I used special version of the design with external SRAM for both program and data memories).\nUpdate 22.12.12. Verilog version of the project is uploaded." language: Verilog license: unknown maintainers: - lepetenokr name: avr_core status: Stable svn-updated: Oct 28, 2012 updated: Nov 22, 2014 wishbone-compliant: 0 - category: Processor created: Oct 15, 2010 description: "===== \n Description =====\n\nThe project is based on OpenCores' AVR project by Ruslan Lepetenok.\n\nThe core is now hyper pipelined. It is a technique to multiply the functionality\nof a design by adding registers (called pipeline stage registers) to the core logic\nin order to multiply its functionality. If you are interested in the technology, go to www.cloudx.cc\n\nThe functional behavior of the AVR remains the same, the hyper pipelined version\nis used when multiple, equal AVR cores (2, 3, ...) are instantiated in the\ndesign (multicores).\n\nThe main benefit is the multiplication of the core's functionality by only\nimplementing registers. This leads to a reduced size compared to the\nindividual instantiation of the cores. This is a great advantage for ASICs\nbut obviously very attractive for FPGAs with their already existing registers.\n\nAnother issue is the performance of the resulting hyper pipelined AVR core.\nThe pipeline stage registers are timing driven placed to partition the critical\npath into equal parts, which leads to an almost multiplied performance of the\ndesign. The timing is optimized for a Spartan 3 and a Virtex 5 device from Xilinx.\n\nThe modifications are done on RTL, so that the project can be used in an\nRTL based testbench.\n\nThe project shows the modified RTL code with 2, 3 and 4 times multiplied\nfunctionality. It is delivered with a testbench and a detailed documentation. \n\n\nEnjoy ..." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tobil name: avr_hp status: Stable svn-updated: Oct 17, 2010 updated: Dec 22, 2012 wishbone-compliant: 0 - category: Processor created: Sep 14, 2008 description: "===== \n Description =====\n\nThis is a Atmel AVR ATtiny261/461/861 compatible core.\nIt should be (more or less) fully code compliant, but it is not clock-cycle compliant.\n\nThe reason it was developed was to have a simple core to develop C-code to.\nThe implementation is rather strait forward without any pipelining.\nOne reason was also to see how hard it was to implement a standard mcu in vhdl and make it run on gcc-generated code.\nThe implementation is a bit quick-n-dirty, I spent about 15h coding the core and about 15h to writing test bench and simulate the core.\n\nI must also say that I'm an AVR fan, if designing hardware where you don't need a complete FPGA, just buy the AVR mcu directly from Atmel! http:\\\\www.atmel.com\\avr\n\nPlease note, you should not use the AVRStudio for development to this core, the files generated by AVRStudio is compatible with the core, BUT, if you don't buy the mcu from Atmel, you shouldn't use their software!\n\nThe test bench uses code (C and Asm) compiled only with the help of gnu-tools.\n\nAtmel, AVR, AVRStudio and other names above may be trademarks of Atmel corporation.\n\n \n\n\n \n \n \n\n===== \n Info =====\n\n- Features:\n - Fully instruction compliant\n - Can address up to 64kword of instructions and 64kbyte of sram\n - Hex-file from a standard avr-gcc compile will work in this core\n- Difference to standard core:\n - The core is slow compared to original mcu, an instruction takes 3-6 cycles to execute\n- Tested:\n - With simple asm-code that tests all instructions\n - With a XTEA encryption/decryption algorithm to test math\n- Non tested:\n - Not all combinations of instructions, registers and constants are tested\n - hex2vhdl converter (may give wrong addresses)\n- Not implemented:\n - Writing of registers with ST, STS and STD (writing of sreg and sp might work)\n - Reading of registers with LD , LDS and LDD\n - SLEEP, WDR, SPM\n - IRQ\n- Future:\n - If you miss something in the core please just send me an email avmcu@opencores.org\n - My future plans is to optimize the core mostly for size but also for speed\n - Add generic to control number of address lines for PM and DM.\n - Add generic to skip SPH register\n - IRQ may be implemented in the future as a generic option if anybody requests it\n - Some simple io-units e.g. io-port, spi, uart, pwm and input-capture units\n - Add a wishbone bride for those who want to use wishbone components (if possible due to core clocking restrictions)\n - Some documentation of the core implementation\n - Add an example project that is ready to compile to an FPGA\n - Fixed in 2008-10-08 release: Add detection of unimplemented usage of LD/LDS/LDD/ST/STS/STD to indirect read or write register map (when X, Y or Z points to 0-0x1F). (Does gcc really use this anywhere?)\n- Wishes from me:\n - Please send me an email if you intend to test or use this core, send some information about your project or product. It would be nice to know if it will be used in any product.\n - Please don't forget to send me bug-reports, any bug fixes you do in the core must be released on the web anyway due to the lgpl license.\n- Comment about the testbench:\n - Fixed in 2008-10-08 release: tb_pm_hex is by default configured for max 2048 words (4096 bytes) of pm space, change generic g_pm_size to be able to use larger programs.\n - Fixed in 2008-10-08 release: the rjmp/rcall directly addresses the hole memory of up to 8 kBytes with \"negative\" addresses, this could give a error in the tb_pm_hex but does not effect real world applications. To fix simulation just use the lower 12 bits of the PM_A in tb_pm_hex/pm. \"a_int := CONV_INTEGER(PM_A(11 downto 0));\". If you use less then 4kBytes of pm code, then this problem will not be visible.\n- Other comments:\n - If you use this core in a project then please send me an email with a link to the projects home page so I could add a link to your project on this page.\n - If you modify the core you must make the changes available according to LGPL, just send me the link and I will add the link to this page or just send me a zip file that I could add to this page.\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Mcu is ready and tested\n- Tb (with tb-source for core) is ready and tested\n- Extensive testing of core in real world not done\n- Synted (and par) for Xilinx Spartan3-400 with Ise 8.1, final results after place-and-route:\n - Optimized for speed: about 83 MHz, 150 ff, 1700 lut\n - Optimized for area: about 70 MHz, 130 ff, 1600 lut\n- Reported: Synted (and par) with Quartus, about 80% of a for Altera EP1C3.\n- Reported: One person have tested to implement a complete function with advanced mathematics in a Virtex E, no issues found so far with the core, in his application this core seems to run about 3.7-4 times slower (in cycle count) then a standard AVR.\n- The new release (2008-10-08) might be slightly larger (0.x%) but works better in simulation. There is no change to the cores instruction handling between first and this release." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - avmcu name: avrtinyx61core status: Design done svn-updated: Mar 10, 2009 updated: Nov 10, 2008 wishbone-compliant: 0 - category: Crypto core created: May 17, 2009 description: "===== \n General Description =====\n\nI know there are plenty of AES (Rijndael) implementations around. I created my own anyway because I was unhappy with either the implementation language (I don't know Verilog and I think its an ugly language), the documentation or the performance/resource usage of the ones I found on the net. \n\n\n\nHere are the key parameters for this core:\n- strictly modular design \n- generics for the keylength (128,192,256 Bit) and enabling and disabling of decrypt datapath.\n- Avalon Interface tested with niosII (can be adapted to match wishbone (I have no whishbone CPU so I didn't test)) \n- Interrupt or polling behaviour \n- The ressource usage is IMHO ok for 128 Bit encrypt only version (797 LE on a CylconeII). (There is work to do to achieve better f_max and ressource usage for the cores with both encrypt and decrypt datapath) \n- documentation available : Datasheet \n\n \n\n\n \n \n \n\n===== \n TODO =====\n\n1.) @anybody with Wishbone experience: can you write an interface or adapt it to whishbone? It should be no problem for the standard signals, however I found no clue how to handle IRQ for wishbone.\nPossibly check it with openrisc?\n2.) Write a VHDL configuration for choosing the architectures used in the generate statements. especially to switch between Altera M4K-Block bases sbox-ROMs and generic ones.\n3.) Increase performance for configurations with both encrypt and decrypt datapath. currently keyexpansion is shared and result signals are multiplexed which leads to drastic decline of f_max. (95MHz for encrypt vs. 65MHz for encrpyt+decrypt)." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - ruschi name: avs_aes status: FPGA proven svn-updated: Apr 19, 2014 updated: Apr 20, 2013 wishbone-compliant: 0 - category: System on Chip created: Jul 14, 2009 description: "===== \n Description =====\n\nHere is proposed a method to implement short structured programs inside an FPGA. The novelty of the proposed method resides in that the commands that constitute the executable program are defined directly by the user in VDHL code. Applying this method, the resolution of a problem can be partitioned in two: on the one hand, the complex hardware functions can be implemented by the VHDL definitions, while, on the other hand, the higher level take of decisions, loops, iterations and conditional branching or testing can be assumed by the executable program.\nThe user has to follow two steps: first, to define, using VHDL, the commands that form the language, and second, to write the program using the commands that have been defined before.\n \n\n\n \n \n \n\n===== \n Future improvements =====\n\nImplementation of predefined commands call and return, making possible the use of subroutines. This should come with the creation of a simple stack." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - fblanco name: avuc status: Design done svn-updated: Nov 13, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: May 14, 2002 description: "===== \n Description =====\n\nMicrocontroller core compatible with 90S1200 and 90S2313.\n\nSame instruction timing as in the original MCUs. Both MCUs use the configurable AX8 core. Other MCUs using one of the two instruction sets the core supports can easily be implemented by creating a new top level.\n\nThere are utilities included that can create VHDL ROMs for simulation and synthesis. The utilites create generic ROMs that can be used for simulation and for synthesis with Leonardo and also Xilinx specific ROMs that can be used for XST synthesis.\n\nBatch files for runnning XST and Leonardo synthesis can be found in syn/xilinx/run/.\n\nBefore you can run the scripts you need to compile hex2rom and xrom or download binaries from here.\nYou must also replace one of the hex files in sw/ or change the batch files to use another hex file.\nIf you need to change target device and settings you need to edit the batch files and some of the files in syn/xilinx/bin/.\n\nThe Leonardo batch file also creates the VHDL ROMs you need to run the Modelsim compile script in sim/rtl_sim/bin/.\n\nIf you want to create ROMs without running the scripts use the following parameters for 90S1200:\nhex2rom [-b] inputfile.hex ROM1200 9l16s > ROM1200.vhd\nAnd these for 90S2313:\nhex2rom [-b] inputfile.hex ROM2313 10l16s > ROM2313.vhd\nHex2rom can read intel/motorola hex and binary files.\n\nBrowse source code here.\nDownload latest tarball here.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- High performance, > 30 MIPS in Spartan 2 -5\n- Except for the watchdog, the analog comparator and the EEPROM all peripherals and interrupts are implemented\n- Supports synchronous ROM/RAM (Xilinx Block RAM compatible)\n- Parametric\n- Technology independent\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Not yet tested in hardware" language: VHDL license: 3-clause BSD licenselink: http://opensource.org/licenses/BSD-2-Clause maintainers: - jesus name: ax8 status: Stable svn-updated: Mar 10, 2009 updated: Feb 16, 2010 wishbone-compliant: 0 - category: System on Chip created: May 27, 2013 description: "===== \n Development Status =====\n\nThis core has been verified with ModelSim and Quartus SignalTap II, using basic directed testcases as well as coverage-driven constrained random verification techniques. I would like to increase the test coverage in future. I also plan to add hardware results from Xilinx ChipScope, as well as simulation results from other simulators as well. If you have simulated or verified this core, please let me know how this core works with your toolchain. I believe Aldec ActiveHDL/Riviera Pro and Synopsys Synplify should have no problems, but I have yet to try them out.\n\n\n\n\n\n\n\nModelSim simulation of AXI4-Stream Master write operations:\n\n\n\n\n\n\n\n\nAcquired measurements from Quartus SignalTap II embedded logic analyser, showing AXI4-Stream Master write operations:\n\n\n\n\n\n\n\n\nI plan to implement AXI4-Stream Slave read operations as well. Currently, the testbench emulates a simple AXI4-Stream slave which responds to write requests from our AXI4-Stream Master, however, it does not latch and save the data. In future, I will design the Slave also as a TLM/BFM model, which will then replace the existing testbench code that emulates the Slave. The Master will connect directly to the Slave, and both Master and Slave models will validate each other. To ensure reliable data transfer, I plan to implement transmit and receive FIFOs, and verify the design with separate clock domains for the Master and Slave. Stay tuned!\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nUsability and readability:\n- Designed in simple and elegant VHDL-2008, with conversions to VHDL-93 for synthesis.\n- Transactor and BFM designed using synthesisable VHDL procedures and VHDL records.\n- I/O ports are grouped into VHDL records.\n- Very simple to use. For a design unit to communicate with another design unit having the same interface, communications is done via a very simple procedure call. For a Master to send data to the Slave, one would just do the following:\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0write(streamData);\nwhere streamData is the data which the master peripheral wishes to transfer to the slave peripheral.\n- Functional verification using OS-VVM's coverage-driven constrained random verification techniques.\n\n\n\n\n\n\n\nDesign characteristics:\n[Note that some of these characteristics reflect the current state of development of this project, and may change as this project evolves.]\n- Synchronous and pipelined logic, with asynchronous resets.\n- Huge chunks of combinatorial logic will also be synchronously reset.\n- Design is very generic, flexible, and scalable. Data widths can be easily adjusted, and the design was created with readability and scalability carefully thought out from the beginning.\n- Efficient and very small (77 LEs for Altera) AXI4-Stream Master if using a 32-bit data interface.\n- Quartus reported an Fmax of 277.47 MHz, for a 32-bit data bus under 85C temperature.\n\n\n\n\n\n\n\nAs of current status, this is the post-place-and-route summary. To produce similar results, compile this project with SignalTap tester removed, and use 32-bit bus-widths for both the data bus (axiMaster_out.tData:t_msg) and the symbolsPerTransfer:t_cnt testbench stimulus.\nNote that these results may be different if you use different bus widths, or Quartus settings, etc.\n\n+--------------------------------------------------------------------------------+\n; Fitter Summary ;\n+------------------------------------+-------------------------------------------+\n; Fitter Status ; Successful - Mon Mar 10 16:27:39 2014 ;\n; Quartus II 32-bit Version ; 12.1 Build 177 11/07/2012 SJ Full Version ;\n; Revision Name ; axi4-tlm ;\n; Top-level Entity Name ; user ;\n; Family ; Cyclone IV E ;\n; Device ; EP4CE115F29C7 ;\n; Timing Models ; Final ;\n; Total logic elements ; 77 / 114,480 ( < 1 % ) ;\n; Total combinational functions ; 44 / 114,480 ( < 1 % ) ;\n; Dedicated logic registers ; 75 / 114,480 ( < 1 % ) ;\n; Total registers ; 75 ;\n; Total pins ; 125 / 529 ( 24 % ) ;\n; Total virtual pins ; 0 ;\n; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;\n; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;\n; Total PLLs ; 0 / 4 ( 0 % ) ;\n+------------------------------------+-------------------------------------------+\n\n\n\n\n\n\n\n\n\nHere are the corresponding timing summaries for the same compilation:\n\n+-----------------------------------------------------------------------------------------------------------+\n; Slow 1200mV 85C Model Fmax Summary ;\n+------------+-----------------+------------+---------------------------------------------------------------+\n; Fmax ; Restricted Fmax ; Clock Name ; Note ;\n+------------+-----------------+------------+---------------------------------------------------------------+\n; 277.47 MHz ; 250.0 MHz ; clk ; limit due to minimum period restriction (max I/O toggle rate) ;\n+------------+-----------------+------------+---------------------------------------------------------------+\n\n+-----------------------------------------------------------------------------------------------------------+\n; Slow 1200mV 0C Model Fmax Summary ;\n+------------+-----------------+------------+---------------------------------------------------------------+\n; Fmax ; Restricted Fmax ; Clock Name ; Note ;\n+------------+-----------------+------------+---------------------------------------------------------------+\n; 302.66 MHz ; 250.0 MHz ; clk ; limit due to minimum period restriction (max I/O toggle rate) ;\n+------------+-----------------+------------+---------------------------------------------------------------+\n\n\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis project implements the AXI4 transaction-level model (TLM) and bus functional model (BFM) in VHDL. Currently, only the AXI4-Stream Master protocol is supported, but I also have plans to support AXI4-Lite and the full AXI4 protocols.\n\n\n\n\n\n\n\nThis enables sub-components of an SoC system to easily communicate with one another through the AXI4 bus. Communications is achieved simply by having a procedure-call statement in your sub-component. The high-level transactions encapsulate the AXI4 protocol details in a lower-level layer known as the bus functional model. This separation between the high-level and low-level implementations results in a more modular and manageable design.\n\n\n\n\n\n\n\nI have included OS-VVM verbatim from their website, so you will need to uncompress the file (you may uncompress using GUI as well):\n\n$ cd rtl/packages\n\n$ tar xvf OSVVM_2013_05.tar.gz\n\n\n\n\n\n\n\n\nI do not adapt nor make any changes to the OS-VVM packages. To find out more about the cool features of OS-VVM, or to contribute to the project, visit the OS-VVM website.\n\n\n\n\n\n\n\nAfter unpacking OS-VVM, we can now simulate the design with Mentor Graphics Questa/ModelSim. Simply cd into the testbench/questa folder, and execute simulate.sh from the Unix prompt:\n\n$ ./simulate.sh\n\n\n\n\n\n\n\n\nIf you have ModelSim/QuestaSim installed, the GUI will appear immediately after you run the script.\n\n\n\n\n\n\n\nCurrently, I provide only the simulation script for Linux/Unix. Email me at daniel.kho@opencores.org if you need help with simulating this project on Windows, and I will send you separate instructions.\n\n\n\n\n\n\n\nI tried simulating this on Synopsys VCS-MX, but the tool didn't like the VHDL-2008 constructs I was using very much. If you are using this simulator, or any other simulator, kindly let us know.\n\n\n\n\n\n\n\nAltera and Xilinx tools failed to synthesise this core as is, as they do not yet support many of VHDL-2008 and VHDL-2002 language constructs. However, I believe Synopsys Synplify should be able to synthesise this. If you are using Synplify, or any other synthesis tool, let us know how well this core works with your toolchain.\n[Note: if this core synthesises well with Synplify, it could very well work for Lattice FPGAs without much hassle. Let us know if you would like to try this on Lattice, so I can post up your results here.]\n\n\n\n\n\n\n\nUpdate [11 Sept 2013]:\nDesign debugged on Altera Quartus. I had to hack Quartus synthesis by changing some VHDL-2008 constructs to VHDL-93. Design verified on an Altera FPGA, and hardware measurements matches well with ModelSim simulations. To use the synthesis sources, look under the rtl/quartus-synthesis folder. You can run the Quartus synthesis flow by supplying the following at the Unix prompt (assuming you are in \"trunk\"):\n\n$ cd workspace/quartus\n\n$ ./synthesise.sh\n\n\n\n\n\n\n\n\nHere's an explanation of what the synthesis script (synthesise.sh) does:\n\n$ quartus_sh --flow compile axi4-tlm\n\n- Runs the whole Quartus synthesis, place-and-route, and design assembly flow.\n\n$ quartus_pgm -c 'USB-Blaster [1-1.6]' -m jtag -o 'p;./output_files/axi4-tlm.sof'\n\n- Programs your board. You may need to change your cable name to the one that's connected to your machine. Enter \"quartus_pgm -l\" to find out your cable name.\n\n$ quartus_stpw ./waves.stp &\n\n- Brings up the Quartus SignalTap II Embedded Logic Analyser's GUI for signal acquisition and viewing.\n\n\n\n\n\n\n\nI have tested this to be working on an Altera DE2-115 kit, the Nios II Embedded Evaluation Kit (NEEK), and also the Altera-Arrow BeMicro Kit. Essentially, this design should work on any other Altera board as well. You just need to assign a clock and reset, and perhaps tweak the SignalTap II core for other boards (if needed), and you're set.\n\nNote that although I used the NEEK, I did not use Nios (or any processor) in this design. You could however use this core to interconnect between processors and other peripherals that are AXI4-Stream compliant. The place-and-route results above was taken from the compilation on the BeMicro Kit (which uses the Cyclone IV E FPGA).\n\n\n\n\n\n\n\nI am trying to make this core to be as vendor independent as possible. To do this, I plan to write a script that works around several vendor tools, including conversion of some VHDL-2008 language constructs to VHDL-93 synthesisable forms. If you'd like to volunteer writing this script (or like to help in any other way), feel free to let me know, and we'll see how we could collaborate.\n\n\n\n\n\n\n\nStay tuned for our Xilinx Vivado version of this core.\n\n\n\n\n\n\n\nComments and feedback are surely appreciated and welcomed. Feel free to write to me (daniel.kho@opencores.org / daniel.kho@tauhop.com).\n\n\n\n \n\n\n \n \n \n\n===== \n To Do =====\n\n1. More comprehensive directed, constrained random, and functional coverage testcases.\n2. Documentation: design specification write-up, verification plan write-up, verification results.\n3. AXI4-Stream Slave, and optional features defined by AMBA AXI4 specification.\n4. Verify + debug design on more tools: Cadence (Encounter RTL, ncvhdl, ncsim), Mentor Graphics (Precision RTL), Synopsys (VCS-MX, Design Compiler, Synplify), Aldec (Riviera, ActiveHDL), Xilinx (Vivado, ISE, ISim).\n5. Bash/Python script to perform automatic VHDL-2008 to VHDL-93 conversion to workaround different tools.\n \n\n\n \n \n \n\n===== \n Contact Us =====\n\nTauhop Solutions - Penang, Malaysia\nFacebook: https://www.facebook.com/tauhop\nsite: http://www.tauhop.com\nemail: info@tauhop.com\ntel.: +60 16 333 0498 (daniel)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: axi4_tlm_bfm status: FPGA proven svn-updated: Mar 29, 2015 updated: Apr 19, 2014 wishbone-compliant: 0 - category: Testing / Verification created: Apr 3, 2011 description: "===== \n Description =====\n\nGeneric AXI master stub. Supports multiple internal masters (multiple AXI IDs), 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: ID number, data bits, AXI command depth, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: axi_master status: Alpha svn-updated: Jul 3, 2011 updated: Oct 21, 2013 wishbone-compliant: 0 - category: Testing / Verification created: Apr 5, 2011 description: "===== \n Description =====\n\nGeneric AXI slave stub. Supports 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: address bits, data bits, AXI command depth, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: axi_slave status: Alpha svn-updated: Jul 3, 2011 updated: Apr 19, 2011 wishbone-compliant: 0 - alternate-download: https://github.com/funningboy/uvm_axi/archive/master.zip category: Arithmetic core created: Jun 23, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this).\nproject : https://github.com/funningboy/uvm_axi" homepage: https://github.com/funningboy/uvm_axi language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - funningboy name: axi_uvm status: Empty updated: Jun 26, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nBit-serial multiplication on the NIST B-163 curve. \n\nThis implementation utilizes DSP481E blocks (Artix-7 FPGA)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: b163arith status: Stable svn-updated: Sep 28, 2013 updated: Sep 28, 2013 wishbone-compliant: 0 - category: Communication controller created: Dec 23, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ultra_embedded name: basic_peripheral_pack status: Empty updated: Dec 23, 2012 wishbone-compliant: 0 - category: Crypto core created: Oct 13, 2003 description: "===== \n Description =====\n\nThe BasicDES Cryptography Core is a small, fast implementation of the DES-56 encryption standard. It perfoms single DES encryption and decryption functions in ECB mode, and can accept a new key for each operation without performance cost. With additional wrapper logic, CBC, CFB and Triple DES modes can also be supported. \n \n\n\n \n \n \n\n===== \n Operation =====\n\nThe DES-56 cypher is a block cypher operating on 64-bit blocks. A 64-bit key is used, of which every eighth bit is ignored, giving an actual key size of 56 bits. Using a predetermined convolution pattern, 16 round keys are generated from the cypher key. In ECB mode, each block is processed without reference to the preceding or succeeding block, as follows:\n\n- An initial data convolution swaps the bits of the message block in a specific pattern. \n- 16 identical rounds of encryption processing are performed. For each round: \n- The 64-bit input block is considered as two 32-bit blocks, called left and right. \n- The right block is output without further processing as the left block for the next round. \n- The right block is expanded from 32 to 56 bits, and exclusive-ored with the current round key. \n- The resulting 56 bit string is substituted in 6-bit groups with 4-bit S-boxes, giving a 32-bit result. \n- The bits of this string are swapped according to a fixed convolution pattern, and the result is exclusive-ored with the left block. \n- The resulting 32-bit block is output as the right input block for the next round. \n\nAfter 16 rounds have been completed, a final data convolution swaps the bits of the output block in a fixed pattern to produce the cyphertext. \n\nDecryption is simply the encryption process with the round keys applied in reverse order.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- ECB mode encryption/decryption\n- Each operation is independent. Encryption and decryption operations can be interleaved as required. \n- Zero time key processing. A new key can be specified for each operation without affecting performance. \n- Each 64-bit encryption or decryption operation is completed within 17 clock cycles, from rising edge of DS to rising edge of RDY.\n- Maximum clock rate is approximately 179MHz.\n- Maximum sustainable throughput is approximately 670 Mbps. \nDevice Utilization and Performance \nThe Virtex2 implementation of this core occupies approximately: \n- 789 slices \n- 1457 4-input LUT's \n- 17,047 equivalent gates \n \n\n\n \n \n \n\n===== \n Status =====\n\n- Documentation has been improved.\n\n\nPerttu Fagerlund has added the following:\n- Key handling has been improved by Perttu Fagerlund. The 1.2 core occupies less than half the logic cells that the 1.1 core occupied. The utilization statistics listed above are for the 1.1 version.\n- Optional functionality for the RDY signal in 1.2: The rdy signal will be set low at reset. Otherwise, it behaves as in version 1.1.\n- Optional signals in the interface: RDY_NEXT_CYCLE, when high, indicates that output data will be valid on the following clock. RDY_NEXT_NEXT_CYCLE, when high, indicates that output will be ready on the second following clock. These signals may be commented out or left unconnected depending on your requirements.\n\n\nNote: The test bench is for the 1.1 version. It does not use the optional signals defined in the 1.2 version.\n\n \n\n\n \n \n \n\n===== \n Pin Description =====\n\n- RST - The reset signal is used to set all internal signals to a known state and prepare the core for operation. It should be strobed high at least once after power on and before attempting the first cryptographic operation. \n\n- IKEY - part of the input data set, the 64-bit input cypher key must be presented with each input data block. The core expects this bus to be valid on the rising edge of the DS signal. \n\n- IMSG0 - part of the input data set, the 64-bit input message block must be presented for each cryptographic operation. The core expects this bus to be valid on the rising edge of the DS signal. \n\n- DECRYPT - part of the input data set, the DECRYPT signal indicates the direction of the cryptographic operation. When 0, the core expects the imsg0 bus to hold plaintext to be encrypted to cyphertext. When 1, the core expects the imsg0 bus to hold cypertext to be decrypted to plaintext. This signal must be valid on the rising edge of the DS signal. \n\n- DS - the DS signal is the data strobe. When momentarily strobed high, it indicates the input data set is valid, and signals the core to start a cryptographic operation. Only the rising edge of this signal has meaning: all other states are ignored. \n\n- ODATA - the 64-bit output data bus is used to export the result of the cryptographic operation from the core. This bus is guaranteed to carry valid data on the rising edge of the RDY signal. \n\n- RDY - the RDY signal has two purposes: first, when high, it indicates that the core is idle and ready to receive input data. Second, when this signal transitions from low to high it indicates that the result of the last cryptographic operation is valid and available on the ODATA bus. The ODATA bus retains its last assigned value until the next rising edge of RDY, or until RST is asserted." language: VHDL license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - srmcqueen name: basicdes status: Stable svn-updated: Mar 10, 2009 updated: Nov 6, 2010 wishbone-compliant: 0 - category: Crypto core created: Oct 13, 2003 description: "===== \n Description =====\n\nThis core is strictly an encryption/decription engine. No attempt has been made to incorporate key generation, and no plans exist to do so.\n\nThe core accepts a 1024-bit exponent, a 1024-bit modulus, and a 1024-bit message. After about 1 million clock cycles, it returns the encrypted or decrypted message on the output bus. There is nothing pretty, fast, or efficient about its operation. It simply uses a brute force approach to perform the required modular exponentiation. Operation is described in more detail in comments in the source.\n\nBasicRSA was written in VHDL using Xilinx's ISE 5.2i. It has been tested using ModelSim XE for 32-bit data, but has not been verified for larger bus widths, nor has it been tested in actual hardware. This core is intended primarily as a learning vehicle for me, and any comments or suggestions to make it better will be appreciated.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- It works for up to 1024-bit modulus (Tested at 32-bit modulus).\n- It fits in a Xilinx Virtex II XC2V8000.\n- Clock Rate at 32-bit modulus approximately 16MHz.\n- Clock Rate at 1024-bit modulus approximately 10MHz.\n- Cycles required to complete operation at n-bit modulus, slightly greater than n-squared clocks.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Long carry chains in adders and subtracters are the main reason for the low clock rates.\n- Experimentation has determined that carry lookahead adders automatically synthesized by ISE are about as good as it gets. Pipelining partial adders could improve throughput, but only at a tremendous cost in gate count.\n- Project status has been changed to \"Stable\" because no improvements have been discovered or suggested to the author." language: VHDL license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - srmcqueen name: basicrsa status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Dec 5, 2007 description: "===== \n Description =====\n\nEver needed a pulse at a given frequency ( period ).\n\nWell that is what BaudGen gives you.\n\nBy the use of parameters, you specify the frequency of the clock you wish to divide, the period ( baud rate ) you wish out, and optionally, how fast you want an over sample output.\n\nBaudGen works out the required count values, and outputs one clock wide pulses at the required rate." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - amulcock name: baudgen status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: ECC core created: Apr 26, 2011 description: "===== \n Description =====\n\nThe double error correcting (DEC) BCH encoder / decoder IP cores.\n\nFeatures :\n\xE2\x80\x93 allows to correct up to 2 errors.\n\xE2\x80\x93 supports 16/32/64/128 bit memories (typical memory word sizes).\n\xE2\x80\x93 operates on complete memory words in a single cycle.\n\xE2\x80\x93 pure combinational logic design." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lepetenokr name: bch_dec_enc_dcd status: Beta svn-updated: Apr 27, 2011 updated: Apr 29, 2011 wishbone-compliant: 0 - category: Other created: Dec 20, 2007 description: "===== \n Description =====\n\nUses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nDesigned for Xilinx FPGA's, with SRL's.\n\nAn efficient way of generating a divide by n**16 counter, where N can be very big.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nbasic counter in cvs" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - amulcock name: big_counter status: Beta svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Video controller created: Nov 20, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tesla500 name: bilinear_demosaic status: Design done svn-updated: Nov 20, 2012 updated: Nov 20, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Nov 26, 2003 description: "===== \n Description =====\n\nThese cores provide a simple means of converting between binary and BCD in hardware. Written in Verilog, with parameters for the input and output widths, these simple cores illustrate the use of functions in Verilog for performing operations that are not easy to do any other way in a fully parameterized (scalable) block of logic.\n\nThere are two conversions: binary_to_bcd and bcd_to_binary. These operate serially, requiring one clock per binary bit used in the conversion.\n\nThe method used for the conversion from base 2 to base 10 is what I call a \"binary coded decimal arithmetic shift right\" (bcd_asr) and \"binary coded decimal arithmetic shift left\" (bcd_asl). It is a special bit shift that involves checking for the magnitude of each 4-bit \"digit\" along the way. When the magnitude is too great, a subtraction is performed, and a carry is generated for the next digit, which is then propagated down the entire string of digits. This method seems to work well for arbitrary size input and output words. Since the subtract/carry is performed during the shifting process, a carry never propagates further than one digit... so there is no clock speed penalty for longer conversions.\n\nThe method used in these cores for conversion should easily work for converting between any two numbering systems with EVEN BASES. So, for example, it could be modified to output octal or base 14 instead of BCD. But then, on a more practical note, who really uses those number bases in hardware anyway?\n\nThere is also a 7-segment multiplexed type LED display driver, which was used in testing these modules.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Modules completed, debugged and tested in SpartanII hardware.\n- Hardware test environment source code provided.\n- Parameterized Verilog, shows use of functions.\n- Start and End signals used (easily Wishbone compatible.)\n- Fully registered input and output.\n- A lengthy commentary at the beginning of each Verilog source file describes how the particular module works, and what the parameters mean. This suffices for documentation, since no other design documentation is provided.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Project completed, debugged and tested in hardware, modules are considered stable and ready for use.\n- Binary to BCD conversion, 16-bit binary to 5-digit BCD, consumes 45 slices in Xilinx SpartanII, reported 136MHz maximum operating speed (over 8 Million conversions per second).\n- BCD to Binary conversion, 5-digit BCD to 16-bit binary, consumes 30 slices in Xilinx SpartanII, reported 116MHz maximum operating speed (over 7 Million conversion per second).\n- Hardware test environment consumes 532 slices in Xilinx SpartanII, 48MHz clock speed used in testing (includes two converters, 16 registers, auto-baud rate serial hardware debugger, 7-digit multiplexed LED display driver)." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jclaytons name: binary_to_bcd status: Stable svn-updated: Mar 10, 2009 updated: Dec 23, 2009 wishbone-compliant: 0 - category: DSP core created: Sep 25, 2001 description: "===== \n Specifications =====\n\n- IIR filter with two poles and two zeros \n- Data width set by user \n- Coefficient width set by user up to 16 bits \n- Wishbone interface for read and write of filter coefficient registers \n- Multiple filters can be combined to form filters with more than two poles and zeros\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe difference equation for the biquad filter is:\n\ny[n] = b10*x[n] + b11*x[n-1] + b12*x[n-2] + a11*y[n-1] + a12*y[n-2]\n\nThis equation is implemented as shown below: \n \n\n\n \n \n \n\n===== \n IMAGE: bquad_blk.gif =====\n\nFILE: bquad_blk.gif\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n Synthesis =====\n\nSynthesized with Synopsys FPGA Express version 2000.11-FE3.5.\n \n\n\n \n \n \n\n===== =====\n\nIf you use this core please let me know." language: Verilog license: custom licensetext: "Author & Maintainer: Chuck Cox (ccox at opencores.org)\nIf you use this core please let me know.\n" maintainers: - ccox name: biquad status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Jan 23, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hippo5329 name: bit_gpio status: Beta svn-updated: Apr 24, 2011 updated: Jan 23, 2011 wishbone-compliant: 0 - category: Processor created: Nov 22, 2009 description: "===== \n Description =====\n\nA 16-bit classical CPU based loosely on Caxton Foster's Blue CPU from the book \"Computer Architecture\". Includes a cross assembler and a very novel front panel for the Digilent Spartan 3 board. \n \n\n\n \n \n \n\n===== \n Main Documentation =====\n\nThe project has a wiki at Hotsolder.\n\n\n \n\n\n \n \n \n\n===== \n Video =====" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - wd5gnr name: blue status: Stable svn-updated: Dec 3, 2009 updated: Feb 6, 2010 wishbone-compliant: 0 - category: Communication controller created: Jun 26, 2008 description: "===== \n 802.11a Transmitter Baseband in BSV =====\n\nThis package implements a parameterized baseband hardware logic for an 802.11a\nTransmitter. This project has since been subsumed by the OFDM baseband project which can also be found on opencores. \n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nHandles Lowest 3 802.11a speeds.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Complete Version Committed" language: Bluespec license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ndave name: bluespec-80211atransmitter status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Video controller created: Jun 25, 2008 description: "===== \n H.264 Decoder supporting 1080p at 60 fps =====\n\nCode Summary\n------------\n\nThis module implements the baseline profile of the H.264 video codec standard.\nIt supports video resolution up to 1080p. It is capable of decoding video at 60 frames per\nsecond (typically more) at any supported resolution. The design has been \nsynthesized in 180nm technology. At 100 mHz it requires approximately 4\nsquare millimeters.\n\nLower resolution decoding (720p @ 30 fps) requires approxiamately half the implementation area.\n\nIt should be noted that there are some error resiliency features that are not implemented:\n* Flexible macroblock ordering\n* Arbitrary Slice Ordering\n* Redundant Slices\nThese are intended to be used when streaming video over unreliable\nchannels, but they don't seem to be commonly supported.\n\nDirectory layout\n----------------\nrelease - \n This directory contains the released H.264 source. \n\ntest - \n This directory contains the build and test infrastructure. Building the\n source requires that the Bluespec compiler (bsc) in your executable path.\n The code has been tested on the lastest 2007 release. Future releases may\n or may not build a functional version of the code. To build the \n code type in the test directory:\n\n make release\n\n Testing infrastructure is included in the release. The golden software code\n requires g++ 4.1. It will not compile with g++ 4.0 or earlier. Further, \n the included software model does not correctly decode 1080p resolution \n and possibly other smaller resolutions. Ignore reported decoding errors \n at this resolution. Alternatively, you could manually check against the \n orignal source image. If you want to run the included test cases, type the\n following command:\n\n ./test.pl \n \n This command will build the hardware and attempt to decode a number of \n sample encoded videos of various resolutions, reporting results as it \n decodes. The testbench takes several hours to run to completion.\n\n\nDocumentation\n-------------\nRefer to the source (kind of spotty) and the following URL:\n\ncsg.csail.mit.edu/pubs/memos/Memo-497/memo497.pdf\n\nThis document contains many useful diagrams and a good description of the \nbehavior of the system.\n \n\n\n \n \n \n\n===== =====\n\n\n \n\n===== \n Status =====\n\n- VGA@30fps decoding on FPGA \n- 1080p@60fps on FPGA coming soon" language: Other license: MIT licenselink: http://opensource.org/licenses/MIT maintainers: - kfleming name: bluespec-h264 status: FPGA proven svn-updated: Mar 10, 2009 updated: Nov 9, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Jun 26, 2008 description: "===== \n Description =====\n\nThis project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems.\n \n\n\n \n \n \n\n===== \n Features =====\n\nDecodes full length (n = 255, t = 16) and shortened Reed Solomon encoded data blocks.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Complete version submitted" language: Bluespec license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ndave - abhiag name: bluespec-reedsolomon status: Planning svn-updated: Jun 16, 2010 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Crypto core created: Aug 6, 2008 description: "===== =====\n\n\n \n\n===== \n Features =====\n\n- Latency insensitive design\n - Should be portable to most bus architectures/platforms\n - Easily amenable to multi-clock domain extension\n- Support for long burst transfers\n- Configurable number of compression cores, compression core parallelism\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis project is under on-going development as we seek to explore and to improve the architecture of the implementation.\n\nWe have demonstrated this architecture on the Xilink XUP board, on which we have obtained throughputs in excess of 233 MB/s for MD6-512" language: Other license: MIT licenselink: http://opensource.org/licenses/MIT maintainers: - kfleming name: bluespec_md6 status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Description =====\n\nThe Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device. The main objective for this standard is to provide a royalty free standard for such wireless protocol. \n\nThe objective of this project is to build an opensource free bluetooth baseband controller, LMP, HCI and higher layers software stacks.\n\nMy bluetooth documentation site\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Working on functional and design specifications. Check preliminary Baseband spec and architecture spec in Download section\n- Defining core architecture\n- Defining the system controller.\n- Link controller design \n- Coding small blocks. You can download the latest VHDL blocks from the cvs using the module name bluetooth_bb. \n \n\n\n \n \n \n\n===== \n Links =====\n\n- Bluetooth links\n \n\n\n \n \n \n\n===== \n Vote for us =====" language: VHDL license: custom licensetext: "This VHDL design file is an open design; you can redistribute it and/or\nmodify it and/or implement it after contacting the author\nYou can check the draft license at\nhttp://www.opencores.org/OIPC/license.shtml\n" maintainers: - khatib name: bluetooth status: Alpha svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Prototype board created: Sep 25, 2001 description: "===== =====\n\n===== Introduction =====\n\nAll electronics designers, students and researchers are always trying to test their ideas and check its performance before punishing it. Several kinds of test prototype boards are used for this purpose. Usually these boards are either very expensive and has either more or less features than what the designer need. For this reason the idea of designing a simple and open design board is going to be available for anyone for almost nothing and he/she can customize it for his/her specific needs. The design of this board is intended to be an open design and to use free and open design tools in order to make it available to large number of designers around the world.\n\n\nObjective\n This project is intended to:\n\n\n To prove the open hardware design concept.\n To make a simple and easy platform for testing small digital cores.\n To Implement, test and define free based tool design flow.\n To build simple generic prototype board for digital designs\n\n\n\n\n\n\n\nDesign License\n \n This project is going to be a free hardware design. It uses GNU license style for hardware. As a result this project is going to use the OpenIPCore license. You can check the draft copy of this license at OpenIPCore License page\n\n\n\n\n\n\n\nDesign Flow\n \n This project can be divided into two parts. The board design and the cores design.\nOf course, anyone can use the commercial tools to design and implement this project, but my objective is to build it using only free tools \"GNU and non-GNU\". so in this article I'll describe only the Free \"hopefully Open\" design flow.\n\nBoard design\n The board design flow can be done through four steps:\n \n Block Diagram design: This can be drawn either by Xfig or gimp or any other gnu graphic tool\n Schematic entry: gschem from gEDA tool is the best schematic design entry tool although it still need some extra features and lot of symbols that anyone can draw by himself\n Netlist extraction: Also the gnetlist from gEDA tool can be used to capture the schematic design and extract it into several netlist file format \"tango\" is one of them. This tool is still under development\n Layout design: The gpcb tool from gEDA does not reach a good level of development so it can not be used for now \"may be later\". PCB interactive printed circuit board design by Thomas Nau can be used instead.\n Board implementation: This is the final step in the design where the designer should work himself to produce his board\n \n\nCores design\n\n Design Flow\n \n Design Entry:\n \n VHDL or Verilog designs can use emacs or Xemacs VHDL or Verilog modes.\n Block diagram to HDL based designs can use VGUI\n VHDL state diagrams can use xfig and BRUSE Y20 tool\n \n\n Simulation:Simulate it using Savant\n Synthesis:Synthesis using Alliance or webfitter\n PPRusing Xilinx webfitter\n ProgrammingDownload the JEDC file through the PC parallel port ot the board using Xilinx tools\n \n \n\n\n\n\n\n\nTesting and Debugging the designn\nOne of the most important factors in hardware design is the testing and debugging of the design's physical implementation. Scopes, logic analayzers and DMMs are the most important devices that are used to debug hardware. In our project we are using the free approach, so we have to keep using this approach even in the debugging hardware.\n Xscope is a PC based open-design scope. The whole design -including documentation, schematics, layout and the software are available from the xscope site.\nSince the Xscope software is available, DMM can be easly implemented by enhancing the software and adding small circuits to measure the current and the impedance.\nLogic analayzer can be implemented by the designing a small core for the CPLD and download it to the board itself.\n \n \n\n\n\n\n\n\nSystem Description\n \n Board block diagram\nThe system is composed of 6 main blocs:\n \n JTAG interface: The JTAG interface is used to program the CPLD on-board. This interface is connected to the JTAG pins on the XC9500 CPLD. From the other side, it is connected to the computer parallel port through a special circuit and a cable. This circuit and cable are documented by Xilinx. The software programmer from xilinx communicates with the CPLD and program it over this cable. This cable is used only during the configuration of the chip. The JTAG circuit is going to be as the Xilinx parallel cable and is going to be implemented on board and connected only through wires to the PC parallel port.\n External Interfaces:The Board has about 64 IO \"TBD\" pins to the external world. These pins are mapped to two connectors, the standard PC parallel Port connector and the reset of the pins go to another connector. The parallel port interface connector is used to simplify the interface to the PC, yet available to any other applications. Each connector has dedicated reset and clock pins. May be we are going to use some kind of isolation between the system and external devices to increase the protection against ground loops. This may be achieved through opto-couplers\n On board IO pins: The board has also on board IO pins. 10 pins are connected to on-board LEDs and 10 pins are connected to on-board dip switch. The number 10 is chosen because most applications uses 8-bit data and we add 2 extra control pins. These pins share the same IO pins on the external interface through special circuit.For example the on-board display leds are connected directly between the I/O pad and the connector and they can be considered as output indicators. While the Dip switches are connected through circuit and these are considered as inputs to the system\n Clocks:\n Reset circuit:\n Power supply:The board requires 5 and 3.3v volt regulated power supply. This is going to be achieved by using a 5v DC supply via a power connector. The 3.3v supply is an optional for those designs that need 3.3 IO pins. In this case a jumper will be used to switch between 5v and 3.3 v that applied to CPLD pins no. 22 and 64. The maximum current that is going to be consumed is \"TBD\". \n \n\n\n\n\n\n\nCPLD Pin assignment\n\n Clocks\n \n GCK1: goes from the on board oscillator\n GCK2: goes from the external board interface\n GCK3: goes from the PC parallel port interface\n \n\nIO pins\n\n 17 IO pins go to the PC parallel Port interface, including CLK and Reset signsl\n 53 IO pins go to the External interface connector, including clk and reset signals\n 10 IO pins are shared with the External interface connector and connected to 10 LEDs\n 10 IO pins are shared with the External interface connector and connected to 10 DIP switches\n\n\nGlobal Reset\nGSR pin is connected to a reset source select circuit. This circuit selects the reset either from the the external interface line, PC parallel port line or on board push button switch.This circuit is a hard wired circuit and can be implemented by jumper select.\n Note: the real pin mapping (i.e. pin to pin ) is going to be determined later.\n\n\n\n\n\nSchematic Design\n TBD\n gschem symbols\n \n XC95108-pc84. Download Symbol\n \n\n\n\n\n\nBoard Mechanical Design\n TBD\n\n\n\n\n\n\nLayout Design\n TBD\n\n\n\n\n\n\n\nBill Of Materials\n \n DB 25 PC Parallel Port connector.\n XC95108-PC84 xilinx CPLD\n 11 LEDs 10 for data and one for power\n 10 Dip switches\n 5 volt power regulator :TBD\n\n \n \n \n \n\n\n\n\n\n\nComponent selection guide\n \n XC95108-PC84 xilinx CPLD\n\nMacro cells = 108 cells\nRegisters = 108 register\nUsable gates = 2400 gates\nI/O pins = 69 pins\nTotal Pins = 84 pins\nPackage = PLCC\nVoltage supply = 5v\nCost = 13$ \n\n \n\n\n\n\n\n\nContact us:\nYou can send your comments to:\n \n khatib@opeip.org\n m_tirhi@hotmail.com\n \n You can also send your comments toopenip@egroups.com\n \n\n\n\n\nReferences tools and links\n \n Xfig Home page\n gEDA tools home page\n PCB interactive printed circuit board design home page \n Xilinx Home page\n Xilinx Xpresso tools Home page\n XC9500 data sheet\n Xemacs Home page\n FreeHDL Home page\n Alliance Home page\n VGUI block to hdl converter home page\n brusey20 state machine to VHDL converter home page\n Savant VHDL simulator Home Page\n Xscope home page" language: other license: OHGPL licenselink: http://liberatedcontent.de/openhardware/OHGPL-0.20.html maintainers: - khatib name: board status: Planning svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Other created: Jul 2, 2004 description: "===== \n Description =====\n\nThis project is a collection of small designs involved with clock boundaries.\nThe clock_switch designs are based on an eetimes article.\nThe bc_fifo_basic design is based on ideas from generic_fifo_dc_gray.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- debouncer: debounce a mechanical switch.\n- clock_switch2_basic: select 1 of 2 clocks, no glitches.\n- clock_switch3_basic: select 1 of 3 clocks, no glitches.\n- clock_switch4_basic: select 1 of 4 clocks, no glitches.\n- clock_switch8_basic: select 1 of 8 clocks, no glitches.\n- oc_fifo_basic: a one-clock fifo\n- bc_fifo_basic: a boundary-crossing fifo\n- clock_detect: a clock-active detector\n- arbiter: a simple parameterized round-robin arbiter\n- random_ff: a ff simulation model for async boundaries\n \n\n\n \n \n \n\n===== \n Status =====\n\n- None of these designs have been verified in silicon." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - esquehill name: boundaries status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: ECC core created: Mar 20, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - aTomek132888 name: bpsk_spread_spectrum_modulator_demodulator status: Alpha svn-updated: Sep 20, 2010 updated: Sep 21, 2010 wishbone-compliant: 0 - category: Processor created: Sep 3, 2014 description: "===== \n Description =====\n\nBrainfuck CPU is a hardware implementation of Brainfuck programing language. It uses simple 2-stage pipelining and Harvard's architecture.\n\nThis CPU is very similar to Touring machine. It operates over linear memory space. Main difference is that the memory if finite.\n\nInstruction set is fairy simple. Opcodes are only 3-bit wide. This allows lower usage of resources over original coding (7 bit ASCII). Verion using original instruction set is available as well.\n\nCan't place oposite of > char for some reason, so I'll use \"(oposite of >)\" instead.\n \n\n\n \n \n \n\n===== \n Opcodes =====\n\nOpcodes:\n000 == (oposite of >) (move pointer left)\n001 == > (move pointer right)\n010 == + (add 1 to value of current memory cell)\n011 == - (subtract 1 from value of current memory cell)\n100 == , (read from I/O port)\n101 == . (write to I/O port)\n110 == [ (begining of loop)\n111 == ] (end of loop)\n\nASCII opcodes (7-bit):\n0x3C == (oposite of >)\n0x3E == >\n0x2B == +\n0x2D == -\n0x2C == ,\n0x2E == .\n0x5B == [\n0x5D == ]\nother == NOP\n \n\n\n \n \n \n\n===== \n Opcodes timing =====\n\nAt start it is necesary to reset all memory locations to 0. CPU does that automatically after reset.\n\nOperations '+', '-', ',' and '.' are always completed in one cycle. As it is necessary to load or store memory cell from/to memory, '>' and (oposite of >) takes two cycles to finish. Opcode ']' takes two cycles on loop finish and one on end, but '[' is a special case. If loop condition is not met (current cell is not 0) it takes one cycle. But in worst case scenario condition is meet at entry. It means that CPU has to find closing bracket ']'. This can waste many time, but it is situation that should not occur, if program is writen correctly. \n \n\n\n \n \n \n\n===== \n Files =====\n\nCPU is only one file: \"brainfuck_cpu.v\". It is CPU core and it requires addition of ROM and RAM.\n\nSecond file is testbench \"brainfuck_cpu_tb.v\". It demonstrates execution of \"Hello World!\" program writen in Brainfuck and compresed to 3 bits.\n \n\n\n \n \n \n\n===== \n Parameters =====\n\nbrainfuck_cpu.v accepts 3 parameters:\n\nDATA_ADDR_WIDTH - defines width of data memory address bus and in consequence size of this memory.\n\nROM_ADDR_WIDTH - defines width of program memory address bus and in consequence size of this memory. Note that Brainfuck language requires a lot of program memory. \"Hello World!\" program uses 115 cells.\n\nSTACK_DEPTH - defines depth of stack. Stack is used to keep track of execution of loops. It's depth imposes maximal level of loops nesting." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - akaminski name: brainfuckcpu status: Beta svn-updated: Sep 7, 2014 updated: Sep 7, 2014 wishbone-compliant: 0 - category: Memory core created: Aug 11, 2013 description: "===== \n Description =====\n\nThis module implements a synchronous FIFO using Block RAM resources such as those found in SRAM-based FPGAs. This module has been used in several products/projects based on Xilinx Spartan 3AN FPGAs. It can be adapted to other development environments and FPGAs, but only Xilinx ISE and Xilinx Spartan 3A/3AN FPGAs has been used to date.\n\nAll components used in this module are inferred, including the Block RAM. This allows the depth and width to be set by parameters. Furthermore, the state of the memory, the write pointer, and FIFO flags can be initialized. This allows FIFO to be preconditioned with a copyright notice, configuration data, etc.\n \n\n\n \n \n \n\n===== \n FPGA Implementation Summary =====\n\nThe BRSFmnCE has been used in several projects/products. It is generally used as a deep FIFO for UARTs. The following synthesis and Map/PAR results effectively summarize the resource utilization of the BRSFmnCE in a XC3S200A-4VQG100I FPGA. This FPGA is not the only one in which BRSFmnCE has been used, but it allows the characterization of the resource requirements of the BRSFmnCE.\n\n\nNumber of Occupied Slices: 30\nNumber of Slice FFs: 35\nNumber of 4-input LUTs: 32\nNumber of RAMB16BWE: 1\n\nReported Speed (Synthesizer): 167 MHz\nReported Speed (MAP/PAR): 187 MHz" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelA name: brsfmnce status: FPGA proven svn-updated: Aug 14, 2013 updated: Nov 1, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Aug 21, 2012 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lmchiesse name: bspline_generation status: Empty updated: Aug 21, 2012 wishbone-compliant: 0 - category: Crypto core created: Nov 4, 2013 description: "===== \n Description =====\n\nThe module is designed and optimized for Bitcoin hash work on FPGA or ASIC." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - nuxi1209 name: btc_dsha256 status: Design done svn-updated: Jan 23, 2014 updated: Nov 16, 2013 wishbone-compliant: 0 - category: Arithmetic core created: May 2, 2014 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - zeuscz name: btcfpgaminer status: Alpha svn-updated: May 15, 2014 updated: May 15, 2014 wishbone-compliant: 0 - category: Crypto core created: Nov 25, 2011 description: "===== \n Description =====\n\nBTCMiner is a Bitcoin Miner software which allows you to make money with your ZTEX USB-FPGA Module. Since these FPGA Boards contain an USB interface no additional hardware (like JTAG programmer) is required and low cost FPGA-clusters can be build using standard USB hubs. \n \n\n\n \n \n \n\n===== \n Features =====\n\n\n Supported FPGA Boards:\n \n Spartan 6 USB-FPGA Module 1.15b with XC6SLX75: 90 MH/s (typical)\n Spartan 6 USB-FPGA Module 1.15d with XC6SLX150: 215 MH/s (typical)\n Spartan 6 USB-FPGA Module 1.15x with XC6SLX150: 215 MH/s (typical)\n\n Spartan 6 USB-FPGA Module 1.15y with four XC6SLX150: 860 MH/s (typical)\n \n Dynamic frequency scaling / overclocking based on error measurement, i.e. BTCMiner automatically chooses the frequency with the highest rate of valid hashes. \n Cluster mode: one software instance can control many FPGA Boards (up to several hundreds, limited by the number of USB host controllers) \n Hot-plugging: new FPGA Boards can be added / removed during runtime \n\n Stale reduction by Long Polling and block monitoring \n Backup server / pools \n Possibility of enumeration of FPGA Boards and cluster partitioning using that numbers \n Power save mode after 5min inactivity of per command \n Temperature monitoring and overheat shutdown (USB-FPGA Module 1.15y rev. 2) \n\n Overheat protection by shutdown if error rate increase to much \n Logging \n Package is Open Source \n Ready-to-use Bitstream, i.e. no Xilinx Software or Licence required \n\n \n\n\n \n \n \n\n===== \n References =====\n\n\n BTC Miner Homepage" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ZTEX name: btcminer status: Stable svn-updated: Nov 28, 2012 updated: Nov 28, 2012 wishbone-compliant: 0 - category: Other created: Nov 14, 2008 description: "===== \n Description =====\n\nThis is for the final project of EC551 Advanced Digital Design using Verilog, a course offered in Boston University. It's basically the classic pacman game on Spartan3 FPGA dev board by Digilent. Team member: Huaxin Dai, Nael Musleh, Krishnan Nair.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- PS/2 Keyboard Input\n - WSAD direction control, with reset and pause function\n - Use standard PS/2 keyboard, no more pushbuttons or 4x4 mini keyboards.\n- VGA Output\n \n\n\n \n \n \n\n===== \n Status =====\n\n- PS/2 keyboard Interface basically done: may have problem when pressing multiple keys\n\n- Basic VGA display done: something shows up on the screen" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - soloist_huaxin name: bu_pacman status: Alpha svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Other created: Mar 28, 2014 description: "===== \n Description =====\n\nsimple fast bubble sort module in verilog" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - avramionut name: bubblesortmodule status: Stable svn-updated: Mar 30, 2014 updated: Mar 30, 2014 wishbone-compliant: 0 - category: Other created: Jun 18, 2012 description: "===== \n Description =====\n\nWhen more than one independent processor is connected to system, that they require access to same set of system resources for ex memory.\nDesigned a system that accept data from each independent processor and arbitrate which one is granted access to memory at any one time.\nEach independent processor will initiate a memory-required signal when it wants access to memory and will deactivate the same when the job is over. If more than one processor request for the bus at the same time , access should be granted on round robin basis.\nThis is in order to ensure that no one independent processor is locked out while another has continuous access. Continuous access is to be granted to any one processor for a period of time. This time period should be separately programmable from the data bus of one the period is not explicitly set, a 128 clock cycle delays should default.\nThe design is aimed at speed efficiency." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vivek223 name: bus-arbiter-with-bist-capability status: Empty updated: Jun 19, 2012 wishbone-compliant: 0 - category: Testing / Verification created: Mar 7, 2012 description: "===== \n TODO =====\n\nTo support Altera Qsys AXI4 Monitor IP integration.\n \n\n\n \n \n \n\n===== \n Tk GUI =====\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nA CPU-to-FPGA bus transaction monitor, captures the CPU write/read address/data to/from memory-mapped registers that resides in the FPGA, and transmits the captured information to PC through JTAG download cable attached to the FPGA.\n\nThe detailed information about this low-level firmware debugger is published by the author on EDN.com as a Design Ideas article: Debug a microcontroller-to-FPGA interface from the FPGA side.\n\nThe original source code accompanying this article is set as the code base. Enhancements and additional features will be added.\n\nRelease 2.5 Added enhancements:\n1. Capture address enlarged to 32bit.\n\nRelease 2.3 Added enhancements:\n1. Xilinx FPGA support with ChipScope VIO. (In addition to Altera FPGA support with Virtual JTAG.)\n2. AXI4-Lite Monitor as Xilinx Platform Studio IP.\n\nRelease 2.2 Added enhancements:\n1. Multiple capture filter selection in the Tk GUI.\n2. Read transaction capture.\n3. Adjustable pre-trigger capture.\n4. Capture content with transaction timing information.\n\nPlanned enhancements:\n1. Parameterized RTL code for flexible implementation.\n2. Comprehensive user guide for implementation and usage." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ash_riple name: bustap-jtag status: FPGA proven svn-updated: Sep 23, 2014 updated: Feb 8, 2014 wishbone-compliant: 0 - category: Prototype board created: Oct 22, 2009 description: "===== \n Description =====\n\nSummary\n\n\nThe Butterfly Light is an open source, modular FPGA development board. It is comprised of the USB Cocoon and the Spartan 3E Cocoon which paired together create the Butterfly Light FPGA development board. The Butterfly Light is best suited for developers who prefer to create their own daughterboards instead of utilizing the \"Wing\" peripheral system. The Butterfly Light exposes the maximum amount of I/O of all available Butterflies. It is also well suited for use with the Logic Analyzer software which implements a 100Mhz, 32 channel Logic Analyzer.\n\n\n\nEAGLE design files are released under the Creative Commons Attribution license.\n\n\n\xC2\xA0\nIncluded Modules\n\n USB Cocoon\n Spartan 3E Cocoon\n\n\xC2\xA0\nSpecifications\n\n USB Cocoon\n \n Three independent power rails at 3.3V, 2.5V, and 1.2V.\n Power supplied by a power connector or USB.\n High speed two channel USB connection for JTAG and serial communications implemented with FT2232.\n JTAG and USB connections are protected by high speed buffers.\n EEPROM memory to store configuration settings for FT2232 USB chip.\n Open Source design that includes Schematic and Board layouts in Eagle format.\n \n \n Spartan 3E Cocoon\n \n \n 8MHz oscillator that can be used by Xilinx's DCM to generate any required clock speed.\n VTQFP-100 footprint that supports Xilinx XC3S250E and XC3S500E parts.\n Bank 0/1 and 2/3 can be jumpered to support 1.2V, 2.5V, or 3.3V.\n JTAG, Serial, and power connections are routed to the the top header.\n Power and GPIO are routed to the side headers.\n Board can be used with Bread Boards if only the outside row of the side headers is populated.\n Open Source design that includes Schematic and Board layouts in Eagle format.\n \n \n\n\xC2\xA0\n\n===== License =====\n\nThe Butterfly Platform USB Cocoon and S3E Cocoon are released under the Creative Commons Attribution license. The goal is to support commercial and noncommercial scenarios such as the following:\n\n\n\n Using the design as the basis for a commercial or non commercial product. In this scenario all that is required is that \"Butterfly Platform\" and \"www.GadgetFactory.net\" is credited somewhere on the circuit board and on the webpage. We would like to see the design used as much as possible so we are open to granting licenses without the attribution requirement.\n Using the design as is or modifying it for a personal or educational project.\n Manufacturing boards for personal usage.\n Manufacturing boards for unique commercial products. We highly encourage using the design to derive unique products. What we discourage is manufacturing and selling boards for a product that is not unique from what someone else created. Let the original creator manufacture and sell the boards, unless of course they have no interest in doing so.\n\n\n\n \n\n\n\n\n\nThis work is licensed under a Creative Commons Attribution 3.0 License.\n\n\n\n\n \n\n\n\n\n\nResources\n\n Butterfly Loader - A software project to load FPGA bitstreams to the Butterfly Light.\n All resources for FPGA Developers.\n Purchase the Butterfly Light.\n\n\xC2\xA0\nPictures" language: Other license: CC BY 3.0 licenselink: http://creativecommons.org/licenses/by/3.0/ maintainers: - gassettj name: butterflylight status: Stable svn-updated: Oct 22, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Testing / Verification created: Apr 12, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - SmithBob name: buzzermusic status: Empty updated: Apr 14, 2014 wishbone-compliant: 0 - category: Video controller created: Nov 28, 2013 description: "===== \n Description =====\n\nThis project considers a hardware implementation of the CCITT group 4(also known as fax4 or tiff) compression algorithm written in vhdl. The design as it is available compresses camera data into tiff format and transmits over RS232 to a graphical client application developed in C++,Qt that stores the received tiff stream into a file and displays the image. The design is developed and tested on the Digilent Nexys2-1200(spartan-3E) and Atlys(spartan-6) board in combination with the Aptina MT9D131 Image Sensor Headboard.\n\nFuture extensions: Region of interest coding and change coding." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - amulder name: bw_tiff_compression status: FPGA proven svn-updated: Jan 7, 2014 updated: Jan 20, 2014 wishbone-compliant: 0 - category: Processor created: Apr 19, 2010 description: "===== \n Description =====\n\n===== Introduction =====\n\nThe aim of the project is to port and maintain Codezero microkernel to the OpenRISC 1000 family.\nL4 microkernel architecture\nCodezero is a new L4 microkernel that has been written from scratch, following the latest development and research principles on microkernel design. It is a modern microkernel implementation that provides capabilities for virtualization and implementation of native OS services.\n\nDesign principles\nCodezero and L4 line of microkernels are founded on a few fundamental design principles. The primary principle is that only the most fundamental and abstract software mechanisms are incorporated into the microkernel, ruling out any policy from the implementation. Codezero implements only the mechanisms to manage threads, address spaces, and the communication mechanisms between them.\n\nBenefits\nIn relation to its main founding principle, the microkernel becomes simple, abstract, and flexible. Due to its abstract nature, it may be used for multiple independent purposes, such as a Hardware Abstraction Layer, a Virtualization Platform, or as a basis for implementing new operating systems. By its simple and abstract design, L4 has a distinguished position among other real-time executives.\n\n\n\nThe microkernel is the only component that runs in privileged CPU mode. Therefore it is the central point of trust on the platform, responsible for the overall security and stable operation of the system. The microkernel is kept rigorously small, therefore making the system secure and stable.\n\n\n\nSince the microkernel has system-wide control, the division of components and resource partitioning are also managed by the microkernel. In this respect Codezero implements the notion of Capabilities to protect and safely multiplex all resources to its run-time components.\n\nCodezero microkernel technical features\n\nGeneral technical features of Codezero are listed below.\n\nGeneral features\n\nSystem partitioning with the concept of containers\nFully capability-checked kernel provides:\nFlexible and configurable resource management\nFine-grain security\nCML2-based kernel and system configuration interface\nWritten in C using a familiar open-source coding style\nSupport for the ARM architecture, including ARMv7, Cortex-A9\nMulticore enabled\nPortable design and structured layout\nFocus on embedded systems\nOpen-source license option and development model\n\n\nCodezero's system calls provide the following mechanisms on an embedded system:\n\n\nThread creation, destruction, and management of thread execution\nAddress-space creation, deletion, and manipulation\nInterprocess communication\nCreation of virtual-to-physical address mappings\nDynamic management of resource access via capabilities\nUserspace shared-memory synchronization\nCache and TLB control\nSystem-on-Chip security, power, and error-recovery management\n\n\nReal-time features\n\nThe microkernel supports kernel preemption, i.e., even tasks running inside the microkernel may be preempted if their timeslice expires.\nAll blocking operations are interruptible. A task sleeping on an IPC queue, a lock, or any waitqueue may be interrupted.\nCodezero has a priority-based scheduler. As such, timeslices are distributed based on the priorities.\nThere are very few locks in the microkernel; consequently concurrency conflicts are avoided and kernel preemption is enabled most of the time.\n\n\nGenerally, Codezero has been designed from the start to incorporate the necessary infrastructure for real-time performance." language: C/C++ license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - drasko - wallento name: c0or1k status: Planning svn-updated: May 6, 2010 updated: Jun 15, 2010 wishbone-compliant: 0 - category: Processor created: Sep 29, 2003 description: "===== \n Features =====\n\n800 Xilinx slices for CPU\n1000 Xililinx slices for complete SoC\nOptimized for exeution of C programs\nVHDL, Assembler, C Compiler, Simulator\n6 kByte RTOS\n \n\n\n \n \n \n\n===== \n Status =====\n\nDone. \nTo browse the SVN sources, or to fetch a tarball of the sources, click one of links above under Details\n \n\n\n \n \n \n\n===== \n Users =====\n\n Riccardo Cerulli-Irelli: http://ubceru.ifsi-roma.inaf.it/~cerulli/projects/c16/" language: VHDL license: unknown maintainers: - jsauermann name: c16 status: Stable svn-updated: Aug 5, 2012 updated: Sep 27, 2012 wishbone-compliant: 1 - category: Arithmetic core created: Aug 13, 2009 description: "===== \n Introduction =====\n\nA cellular automata (CA) is a discrete model that consists of a grid (1D, 2D, 3D ) with objects called cells. Each cell can be in one of a given set of states (on and off, different colours etc). Each cell has a set of cells in close proximity (neighbours). Given the current internal state of a cell, the states of the neighbour cells and a given set of update rules the next state of a cell can be determined.\n\n\n\n\nThe ca_prng IP-core implements a 1D binary cellular automata with wrap around at the edges (i.e. a ring). The default update rule used in the ca_prng is rule30 discovered by Stephen Wolfram. Rule30 is an update rule that when applied to the CA will produce a class III, aperiodic, chaotic behaviour.\n\n\n\n\nThe ca_prng core is a fast, compact pattern generator capable of providing user selectable patterns at GByte/s speed. The ca_prng core is suitable for FPGA-accelerated verification, on-chip testing as well as for applications that needs random patterns or specific sets of patterns generated.\n\n\n\n\nNOTE: The ca_prng is NOT a cryptographically strong PRNG and should not be used as a key generator or as a stream cipher." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - joachim name: ca_prng status: FPGA proven svn-updated: Aug 19, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Memory core created: Jan 5, 2010 description: "===== \n Description =====\n\nThis project is to develop a direct mapped cache controller for embedded applications.\n\nKey Design Features\n\n- Direct mapped with configurable address size, line size and number of cache lines\n- Non Pipelined architecture\n- No Cache flush\n\nSynthesis will be conducted using VirtexII Pro\n \n\n\n \n \n \n\n===== \n Progress =====\n\n7th January 2010\nMemory(RAM) implementation completed" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - chinthakaak name: cachecontroller status: Mature svn-updated: Jan 7, 2010 updated: Jan 7, 2010 wishbone-compliant: 0 - category: Crypto core created: Oct 17, 2007 description: "===== \n Description =====\n\nCamellia block cipher cores.\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe project is composed of different cores:\n\n\tPerformance optimized: exploits pipelining in order to maximize the throughput. There are two different versions: the first accept only 128-bit key in order to minimize area and the second accept all key sizes.\n\tArea optimized: exploits looping in order to minimize area.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nAll the cores are tested only at pre-synthesis stage and therefore cannot be considered stable." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - pfulgoni name: camellia-vhdl status: Mature svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Crypto core created: Oct 18, 2004 description: "===== \n Description =====\n\n( I still have problem to upload files to cvs.opencores......)\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\n- status1\n- status2" language: VHDL license: unknown maintainers: - mr_rifqi name: camellia status: Alpha svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Feb 11, 2003 description: "===== \n Description =====\n\nController Area Network or CAN is a control network protocol from\nBosch that has found wide use in Industrial Automation and the\nAutomotive Industry.\n\nMost of the patents of CAN are owned by Bosch and although there\nare no restictions on developing an opensource CAN IP but for any\ncommercial use the protocol license from Bosch is an indispensable prerequisite. \n\nSize is approximately 12k gates (930 flip-flops). \n \n\n\n \n \n \n\n===== \n Block Diagram =====\n\n\n \n\n===== \n IMAGE: CAN.gif =====\n\nFILE: CAN.gif\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Non-Destructive bit-wise arbitration (CSMA/CA)\n- Message Based Addressing/Filtering\n- Broadcast Communication\n- 1 Mbit/Sec Operation\n- WISHBONE SoC interface\n- 8051 interface\n- SJA1000 (Philips) compatible interface.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Verilog version finished (tested in HW and verified with the Bosch VHDL Reference System) (October, 27, 2004)\n\n \n\n\n \n \n \n\n===== \n Verilog version =====\n\n- Verilog version can be found here." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - igorm name: can status: Stable svn-updated: Mar 10, 2009 updated: Feb 17, 2015 wishbone-compliant: 1 - category: DSP core created: Jun 9, 2014 description: "===== \n Description =====\n\nCanny edge detector with a 9x9 mask (gradient + gaussian filtering with sigma = sqrt(2)). Able to produce a throughput of 1 pixel per clock cycle. Succesfully implemented on a Virtex4 up to 300Mhz clock frequency." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - angelobacchini name: canny_edge_detector status: FPGA proven svn-updated: Jun 9, 2014 updated: Oct 29, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Dec 28, 2010 description: '' language: SystemC license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gokulopencore name: capacitance_meter status: Empty updated: Jan 30, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Oct 21, 2011 description: "===== \n Description =====\n\nThis IP implements the CAVLC parsing process in ITU-T H.264 (05/2003)\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Compatible with ITU-T H.264 (05/2003), but it do not calculate nC and store TotalCoeff,\n you need to add a nC_decoder outside this core.\n\n- New structure for run_before decoder, the core doesn't save Runs in flip-flops and\n doesn't need the run_combine process, this feature reduces both cycle and resource.\n\n- this core has a simple interface\n\n- 9 cycles per cavlc block on average(including P frames)\n\n- Fully synchronous design, Fully synthesisable\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nDocumentation\n\n \n\n\n \n \n \n\n===== \n Synthesis results =====\n\nPush-button synthesis results for various targets.\n\nAltera:\n- Cyclone EP3C55F256C6 : 1085 LEs @ 114MHz\n- Stratix EP2S15F484C3 : 939 LUTs @ 128MHz\n\nXilinx:\n- Virtex XC4V1X200FF1513-10 : 1467 LUTs @ 96MHz" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qiubin name: cavlc status: Design done svn-updated: Nov 4, 2011 updated: Nov 20, 2012 wishbone-compliant: 0 - category: System on Chip created: May 20, 2011 description: "===== \n Description =====\n\nSoftware Defined Radio RX/TX.\n\nConsultative Committee for Space Data System (CCSDS) specifications compliant.\n\nThis is part of a larger project (EurySPACE) to implement Nasa Space Telecommunication Radio Systems (STRS) architecture for flexibility, reconfigurability and upgradability.\n\n=> developped and supported by Euryece Telecom: http://www.euryecetelecom.com\n \n\n\n \n \n \n\n===== \n Protocol Description =====\n\nOpen System Interconnection (OSI) philosophy : reduced to 5 layers as CCSDS Space Communications Protocols Reference Model\n\nEmitter (TX) description:\n- Application Layer: Lossless Data Compression or Image Data Compression + CCSDS File Delivery Protocol (CFDP) or Space Communications Protocol Specifications - File Protocol (SCPS-FP) / FTP\n- Transport Layer: CCSDS File Delivery Protocol (CFDP) or Space Communications Protocol Specifications - File Protocol (SCPS-TP) / FTP or User Data Protocol (UDP) + Space Communications Protocol Specifications - Security Protocol (SCSP-SP) or IPSEC\n- Network Layer: Space Packet Protocol or Space Communications Protocol Specifications - Network Protocol (SCPS-NP) or IP-v4 or IP-v6\n- Data Link Layer - Protocol Sublayer: Telemetry (TM) Space Data Link Protocol or Telecommand (TC) Space Data Link Protocol or Advanced Orbiting Systems (AOS) Space Data Link Protocol or Proximity-1\n- Data Link Layer - Synchronization and Channel Coding Sublayer: Telemetry (TM) Synchronisation and Channel Coding or Telecommand (TC) Synchronisation and Channel Coding or Proximity-1\n- Physical Layer: RF and Modulation Systems or Proximity-1\n\nReceiver (RX) description:\n- Physical Layer: Demodulation - implementation of \"Autonomous Software-Defined Radio Receivers for Deep Space Applications\" recommandations from Jon Hamkins and Marvin K. Simon" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - zguig52 name: ccsds_rxtxsoc status: Empty updated: Sep 14, 2012 wishbone-compliant: 1 - category: Other created: Dec 2, 2010 description: "===== \n Description =====\n\nClock Domain Crossing micro FIFO (Verilog/SystemVerilog):\n cdc_ufifo provide an minimalist fifo. Most advantage - not use RAM blocks.\nit can be 4 buffer data cells minimum.\nby default used implementation without ram, only standart register cells used, and it can be selected if need. most slowest stage is the output multiplexor\nShadowed outputs: provide an register after multiplexer to remove data unsynchronized changes from outputs when skiped some cycles.\n\n \n\n\n \n \n \n\n===== \n tested: =====\n\nCycloneII project works on up to 50 MHz data transfers" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - AlexRayne name: cdc_ufifo status: FPGA proven svn-updated: Dec 2, 2010 updated: Jan 28, 2011 wishbone-compliant: 0 - category: Library created: Aug 17, 2013 description: "===== \n Description =====\n\nCommon Design Environment (CDE) is a library of modules that usually require replacement with specific hard \nmacros when the design is retargeted to a IC process. By using modules from the CDE library it will be possible\nto easily make this substitution with an ip-Xact enabled tool flow without having to touch the original rtl code." language: Verilog license: Apache License Version 2.0 licenselink: http://opensource.org/licenses/Apache-2.0 maintainers: - jt_eaton name: cde status: Stable svn-updated: Aug 18, 2013 updated: Aug 18, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Dec 31, 2002 description: "===== \n Description =====\n\nCores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See www.confluent.org for more info.\n\nCordics (COordinate Rotation DIgital Computers) perform arbitrary phase rotations of complex vectors and are often used to calculate trigonometric functions and vector magnitudes.\n \n\n\n \n \n \n\n===== \n Features =====\n\nEach file is stand-alone and represents a specific configuration.\nThe 4 parameters are:\n - Rotation or Vector Mode\n - Vector Precision\n - Angle Precision\n - Number of Cordic Stages\n\nAll designs are pipelined with a synchronous enable and reset.\nThe pipeline latency equals 2 clock cycles plus the number of cordic stages. \n\nThe configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v\n - r : Cordic Mode. 'r' = Rotation, 'v' = Vectoring\n - 32 : Precision of the individual vector components.\n - 16 : Precision of the angle.\n - 12 : Number of cordic stages.\n\nCurrent configurations:\n - cf_cordic_r_8_8_8\n - cf_cordic_v_8_8_8\n - cf_cordic_r_16_16_16\n - cf_cordic_v_16_16_16\n - cf_cordic_r_18_18_18\n - cf_cordic_v_18_18_18\n - cf_cordic_r_32_32_32\n - cf_cordic_v_32_32_32" language: VHDL and Verilog license: 2-clause BSD licenselink: http://opensource.org/licenses/BSD-3-Clause maintainers: - tomahawkins name: cf_cordic status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Jan 5, 2003 description: "===== \n Description =====\n\nCores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info.\n\nThe Fast Fourier Transform converts time or spacial information into the frequency domain and is one of the most popular DSP algorithms.\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe FFT architecture is pipelined on a rank basis; each rank has\nits own butterfly and ranks are isolated from each other using\nmemory interleavers. This FFT can perform calculations on\ncontinuous streaming data (one data set right after another).\nMore over, inputs and outputs are passed in pairs, doubling the\nbandwidth. For instance, a 4096 point FFT can perform a transform\nevery 2048 cycles.\n\nEach file is stand-alone and represents a specific configuration.\nThe 2 parameters are:\n - Number of Points\n - Component (Real/Imag) Precision\n\nAll designs are pipelined with a synchronous enable and reset.\n\nThe configuration parameters are coded in the file names: cf_fft_4096_18.v\n - 4K point FFT.\n - 18 bit precision, real and imaginary. Total is 36 bits.\n\nCurrent configurations:\n - cf_fft_256_8\n - cf_fft_512_8\n - cf_fft_1024_8\n - cf_fft_2048_8\n - cf_fft_4096_8\n - cf_fft_256_16\n - cf_fft_512_16\n - cf_fft_1024_16\n - cf_fft_2048_16\n - cf_fft_4096_16\n - cf_fft_256_18\n - cf_fft_512_18\n - cf_fft_1024_18\n - cf_fft_2048_18\n - cf_fft_4096_18" language: VHDL and Verilog license: 2-clause BSD licenselink: http://opensource.org/licenses/BSD-3-Clause maintainers: - tomahawkins name: cf_fft status: Stable svn-updated: Mar 10, 2009 updated: May 18, 2012 wishbone-compliant: 0 - category: DSP core created: Mar 30, 2003 description: "===== \n Description =====\n\nCores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info.\n\nFinite impulse response (FIR) filters are common in DSP applications and consist of a delay bank (filter taps) and a sum-of-products.\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe filter architecture consists of a delay bank and a pipelined sum-of-products network. All arithmetics are lossless -- multipliers produce precision with the sum of the operands and each adder extends precision by 1 bit.\n\nThe filter has a synchronous reset to reinitialize the filter taps. The reset does not affect the pipeline registers in the sum-of-products network.\n\nThe filter includes ports for the filter coefficients; typically hardwired to constants.\n\nEach file is stand-alone and represents a specific configuration.\nThe 3 configuration parameters are:\n - Filter Order (# of delay taps)\n - Input Precision\n - Coefficient Precision\n\nThe configuration parameters are coded in the file names: cf_fir_3_16_8.v\n - 3 : Filter order.\n - 16 : Input precision.\n - 8 : Coefficient precision.\n\nCurrent configurations:\n - cf_fir_3_8_8\n - cf_fir_7_16_8\n - cf_fir_7_16_16\n - cf_fir_12_16_10\n - cf_fir_16_16_16\n - cf_fir_24_8_8\n - cf_fir_24_16_16\n - cf_fir_33_16_16" language: VHDL and Verilog license: 2-clause BSD licenselink: http://opensource.org/licenses/BSD-3-Clause maintainers: - tomahawkins name: cf_fir status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Mar 13, 2003 description: "===== \n Description =====\n\nCores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe floating point representation follows the IEEE-754 bit format:\n\n{SignBit, Exponent, Mantissa}\n\nEach file is stand-alone and represents a specific configuration.\nThe 3 configuration parameters are:\n- Combinatorial or Pipelined ('c' or 'p')\n- Exponent Precision\n- Mantissa Precision\n\nNote the total width = 1 + Exponent Precision + Mantissa Precision.\nFor pipeline configurations, pipeline latency is 4 + Mantissa Precision.\n\nThe configuration parameters are coded in the file name.\nFor example, cf_fp_mul_p_11_52 has the following configuration:\n- Pipelined\n- 11-Bit Exponent\n- 52-Bit Mantissa\n\nCurrent configurations:\n- cf_fp_mul_c_3_4\n- cf_fp_mul_p_3_4\n- cf_fp_mul_c_5_10\n- cf_fp_mul_p_5_10\n- cf_fp_mul_c_8_23 (IEEE-754 Single)\n- cf_fp_mul_p_8_23 (IEEE-754 Single)\n- cf_fp_mul_c_11_52 (IEEE-754 Double)\n- cf_fp_mul_p_11_52 (IEEE-754 Double)" language: VHDL and Verilog license: 2-clause BSD licenselink: http://opensource.org/licenses/BSD-3-Clause maintainers: - tomahawkins name: cf_fp_mul status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Memory core created: Apr 1, 2003 description: "===== \n Description =====\n\nCores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info.\n\nMemory interleavers are common components often found in signal processing applications. They are useful for buffering and reordering data and typically form the separation between design stages. Interleavers can be used for:\n\n- Transposing Images for Image Processing\n- Buffering Noncontinuous Input Data \n- Data Shuffling Between FFT Ranks\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe memory interleaver consists of 2 interleaving memories: one memory loads input data, while the other dumps output data -- On a swap signal the 2 memories switch roles.\n\nThe interface to an interleaver is:\n- Inputs\n - clock : Main clock.\n - swap : Pulse to swap memories (input become output, output becomes input).\n - write : Write enable to input memory.\n - addr : Address to input memory.\n - data : Data to input memory.\n- Outputs\n - sync_primary : Pulse to indicate an interleaver swap.\n - sync_secondary : Pulse to indicate address 0 is output.\n - data : Data dumped from output memory.\n\nInput data to the interleaver is addressable. Output data is dumped one memory location after another starting at address 0.\n\nEach file is stand-alone and represents a specific configuration. \nThe 2 configuration parameters are: \n- Address Width (Memory Depth)\n- Data Width\n\nThe configuration parameters are coded in the file names: cf_interleaver_8_32.v \n- 8 : Address Width \n- 32 : Data Width\n\nCurrent configurations: \n- cf_interleaver_6_8\n- cf_interleaver_7_8\n- cf_interleaver_8_8\n- cf_interleaver_9_8\n- cf_interleaver_10_8\n- cf_interleaver_11_8\n- cf_interleaver_12_8\n- cf_interleaver_6_16\n- cf_interleaver_7_16\n- cf_interleaver_8_16\n- cf_interleaver_9_16\n- cf_interleaver_10_16\n- cf_interleaver_11_16\n- cf_interleaver_12_16\n- cf_interleaver_6_32\n- cf_interleaver_7_32\n- cf_interleaver_8_32\n- cf_interleaver_9_32\n- cf_interleaver_10_32\n- cf_interleaver_11_32\n- cf_interleaver_12_32\n- cf_interleaver_6_64\n- cf_interleaver_7_64\n- cf_interleaver_8_64\n- cf_interleaver_9_64\n- cf_interleaver_10_64\n- cf_interleaver_11_64\n- cf_interleaver_12_64" language: VHDL and Verilog license: 2-clause BSD licenselink: http://opensource.org/licenses/BSD-3-Clause maintainers: - tomahawkins name: cf_interleaver status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: ECC core created: May 13, 2003 description: "===== \n Description =====\n\nCores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent.org for more info.\n\nThe core is provided in Verilog, Vhdl, C, and Python.\n\nLow-density parity-check (LDPC) codes are forward error correction codes invented by Robert Gallager in the early 60's. LDPC codes have record breaking error correction performance and approach Shannon's limit for channel capacity.\n \n\n\n \n \n \n\n===== \n Features =====\n\nThis LDPC error corrector implements Gallager's \"A\" algorithm: an iterative, hard-decision decoder that opts for simplicity over performance. The architecture elaborates all logic required to implement the message-passing algorithm from message nodes, to check nodes, then back to message nodes -- one iteration occurs every clock cycle.\n\nThe core is primarily meant as an LDPC evaluation platform, as the fully parallel architecture may be inappropriate for synthesis of large block length LDPC decoders.\n\nThe Confluence source code generates an LDPC error corrector given an arbitrary parity-check matrix. This core implements Gallager's (20, 3, 4) parity-check matrix:\n\n1 1 1 1 . . . . . . . . . . . . . . . .\n. . . . 1 1 1 1 . . . . . . . . . . . .\n. . . . . . . . 1 1 1 1 . . . . . . . .\n. . . . . . . . . . . . 1 1 1 1 . . . .\n. . . . . . . . . . . . . . . . 1 1 1 1\n1 . . . 1 . . . 1 . . . 1 . . . . . . .\n. 1 . . . 1 . . . 1 . . . . . . 1 . . .\n. . 1 . . . 1 . . . . . . 1 . . . 1 . .\n. . . 1 . . . . . . 1 . . . 1 . . . 1 .\n. . . . . . . 1 . . . 1 . . . 1 . . . 1\n1 . . . . 1 . . . . . 1 . . . . . 1 . .\n. 1 . . . . 1 . . . 1 . . . . 1 . . . .\n. . 1 . . . . 1 . . . . 1 . . . . . 1 .\n. . . 1 . . . . 1 . . . . 1 . . 1 . . .\n. . . . 1 . . . . 1 . . . . 1 . . . . 1" language: VHDL and Verilog license: 2-clause BSD licenselink: http://opensource.org/licenses/BSD-3-Clause maintainers: - tomahawkins name: cf_ldpc status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Coprocessor created: Aug 20, 2003 description: "===== \n Description =====\n\nCores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent.org for more info.\n\nSeveral cores are provided in Verilog, Vhdl, and C. If you don't see the configuration you need, chances are we can easily generate it for you.\n\nThe Reconfigurable Computing Array (RCA) is a platform for dynamic reconfigurable computing. RCA consists of a fine-grained array of reconfigurable \"square\" logic tiles. Similar to an FPGA CLB, a tile can be programmed to perform a wide variety of functions.\n \n\n\n \n \n \n\n===== \n Features =====\n\nOverview\n\nUnlike FPGAs, RCA has no routing fabric. Rather, all tiles\ncommunicate directly with their nearest neighbor, i.e., north, south, west, east.\nBecause a tile's inputs are registered, the lack of routing fabric\nprevents end-to-end combinatorial logic design that is possible with general\npurpose FPGAs.\n\nHowever, the advantage of \"hard-wiring\" tiles is 2 fold: greater logic density\nand improved speed. FPGAs consume 80-90% of their area on routing; only 10%\nyields useful logic in the form of CLBs. Without the routing fabric, it is possible RCA\ncan increase logic density by a factor of 10.\n\nSecondly, because signals are registered across tile boundaries, timing is\ndeterministic and constant. Further more, since tiles are fine-grained, clocks rates\ninto the GHz should be possible.\n\nThe goal of this project is to develop an understanding of optimal tile architecture\ntrade-offs and RCA compiler technology.\n\n\nTile Structure\n\nA tile is square, having four 1-bit inputs and four 1-bit outputs named\nnorth, south, west, and east. An array is a collection of tiles organized\nlike a checkerboard, each side connecting to an adjacent tile. For instance, the east output of\na tile of the left plugs into the west input of a tile on the right.\n\nIn terms of tile architecture, there are several possibilities.\nThe initial architecture is based on 3-to-1 look-up tables (LUTs).\nThere are four LUTs per tile -- one for each direction -- each LUT with three\n8-to-1 multiplexers for input data selection.\n\nThe following illustrates the tile architecture (only the north datapath shown):\n\n\n\nTop Level Interface and Array Configuration\n\nAt the top level, RCA has 4 input data buses and 4 output data buses;\nand input and output bus for each side of the array (N, S, W, E).\nBit 0 of \"north_i\", \"north_o\", \"south_i,\" and \"south_o\" corresponds to the western most tile.\nLikewise, bit 0 of \"west_i\", \"west_o\", \"east_i\", and \"east_o\" corresponds to\nthe northern most tile. All tile interconnection registers are synchronized\non the \"clock_main_c\" clock.\n\nIn addition to the data busses, the configuration bus handles the programming and\nreconfiguration of the array. Configuration is synchronized on the \"clock_config_c\" clock.\nEach data path within each tile is addressable.\nConfiguration addressing is as follows (msb on the left):\n\n- ConfigAddr = {RowSelect, ColSelect, DirSelect}\n - RowSelect of 0 corresponds to the northern most row.\n - ColSelect of 0 corresponds to the wester most column.\n - DirSelect: 00=north, 01=south, 10=west, 11=east.\n\nThe configuration data is 18-bits. It defines the LUT function,\nthe input MUX selection, and the output MUX selection, for a specify tile\ndatapath. The follow defines the configuration data format:\n\n- ConfigData[17] : Output Select (0=direct, 1=registered)\n- ConfigData[16:14] : Input Select 2\n- ConfigData[13:11] : Input Select 1\n- ConfigData[10:8] : Input Select 0\n - 000=north_in\n - 001=south_in\n - 010=west_in\n - 011=east_in\n - 100=north_state\n - 101=south_state\n - 110=west_state\n - 111=east_state\n- ConfigData[7:0] : LUT data {f(7), f(6), f(5), f(4), f(3), f(2), f(1), f(0)}\n\nRouting and Function\n\nWith the lack of routing fabric, data routing is performed in the configuration of each tile.\nBecause every tile input is registered, designs on RCA are micro-pipelined.\nTo simplify pipeline data aliment, each tile output can come directly from the LUT\nor delayed 1 cycle though an output register.\n\nWith each tile having 4 independent datapaths (N, S, W, E), function and routing can be\ngrouped onto the same tile. For instance, a function can be performed from West and South to East,\nwhile at the same time data is routed from North to South. Note the South input and South output are\nseparate datapaths.\n\nEmbedded Extensions\n\nAs with platform FPGAs, RCA can benefit from specialized embedded components,\nsuch as block ram, hardware multipliers, and processors. Implementing embedded\ncomponents is possible by replacing internal tiles groups with hard IP." language: VHDL and Verilog license: 2-clause BSD licenselink: http://opensource.org/licenses/BSD-3-Clause maintainers: - tomahawkins name: cf_rca status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Apr 15, 2003 description: "===== \n Description =====\n\nCores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent.org for more info.\n\nSeveral cores are provided in Verilog, Vhdl, and C. If you don't see the configuration you need, chances are we can easily generate it for you.\n\nThe State Space Processor is used for implementing discrete linear systems, such as finite and infinite impulse response filters, multiple input and output systems, and general state space equations common in control and DSP applications. Its simple instruction set and efficient architecture has a very low logic footprint.\n \n\n\n \n \n \n\n===== \n Features =====\n\nArchitecture:\n\nThe processor requires two external memories: one for program instructions and the other for constants (coefficients) used in calculation. The processor maintains a register file of 16 N-bit registers used to retain state information and for processing intermediate results. The register file is also used for handling input and output; registers can be written from an external source and all registers are available as outputs. For convenience, register 0 is wired to ground and instructions updating r0 have no effect on the register file.\n\nThe processor runs calculations on a cycle basis:\n 1. The external environment writes inputs into the register file.\n 2. The external environment signals a \"Cycle\" to run the program and calculate a cycle.\n 3. The external environment waits for \"Done\", then reads output from the register file.\n\nInstruction Set:\n\nThere are 4 instruction types and a total of 8 instructions. Each instruction is 16-bits. The types include:\n- Unary Operation\n - OpCode [15:12], Operand A Reg [11:8], Not Used [7:4], Result Reg [3:0]\n- Binary Operation\n - OpCode [15:12], Operand A Reg [11:8], Operand B Reg [7:4], Result Reg [3:0]\n- Constant Load\n - OpCode [15:12], Constant Memory Address [11:4], Result Reg [3:0]\n- Halt\n - OpCode [15:12], Not Used [11:0]\n\nUnary Operations (OpCode):\n- ShiftLeft (0000)\n - RegX - Flag - ShiftRight (0001)\n - RegX - Flag - ShiftClip (0010)\n - RegX - RegX - RegX - Flag - Performs a limited/clipped multiplication by 2.\n\nBinary Operations (OpCode):\n- Add (0011)\n - RegX - Flag - AddCond (0100)\n - RegX - Flag - Sub (0101)\n - RegX - Flag - Switch (0110)\n - RegX - Flag \nConstant Load Instruction (OpCode):\n- Constant (0111)\n - RegX - Flag \nHalt Instruction (OpCode):\n- Halt (1---)\n - Halts processor (prevents further register updates).\n\nBooth multiplication can be performed using ShiftRight and AddCond with an accumulation register.\n\nEach file is stand-alone and represents a specific configuration.\nThe 2 parameters are:\n- Data Width\n- Instruction Memory Address Width\n\nThe configuration parameters are coded in the file names: cf_ssp_32_5.v\n- 32 : Data Width\n- 5 : Instruction Memory Address Width\n\nCurrent configurations:\n- cf_ssp_8_6\n- cf_ssp_16_6\n- cf_ssp_32_6\n- cf_ssp_64_6\n- cf_ssp_8_7\n- cf_ssp_16_7\n- cf_ssp_32_7\n- cf_ssp_64_7\n- cf_ssp_8_8\n- cf_ssp_16_8\n- cf_ssp_32_8\n- cf_ssp_64_8\n- cf_ssp_8_9\n- cf_ssp_16_9\n- cf_ssp_32_9\n- cf_ssp_64_9\n- cf_ssp_8_10\n- cf_ssp_16_10\n- cf_ssp_32_10\n- cf_ssp_64_10" language: VHDL and Verilog license: 2-clause BSD licenselink: http://opensource.org/licenses/BSD-3-Clause maintainers: - tomahawkins name: cf_ssp status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Oct 29, 2002 description: "===== \n Description =====\n\nThis is synthesizeable radix 4 complex fft processor. Input data width and points are configurable. Output data width = Input data width + 2. Some necessary limited and shift have been done at every butterfly.\n\nA sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144 registers (about 47%) of the device.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Data width configurable\n- Point configurable\n- Input data during data output\n- Simulation result has compare with Matlab result\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Design is available in VHDL from OpenCores CVS via cvsweb or via cvsget \n- ..." language: VHDL license: unknown maintainers: - sradio name: cfft status: Stable svn-updated: Mar 10, 2009 updated: Sep 30, 2010 wishbone-compliant: 0 - category: Memory core created: Oct 22, 2011 description: "===== \n Description =====\n\nCFI flash controller IP. \n\nProvides two modes of operation - simple (Wishbone bus straight through to flash bus, essentially, but with 32-bit word read capability, allowing XIP - execute in place - for 32-bit processors) and a \"CFI engine\" mode, which aims to simplify interfacing with a CFI flash.\n\nOnly implements asynchronous flash bus interface.\n\nSystem bus interface is Wishbone, or CFI engine module can be used stand-alone and provides a generic bus interface.\n\nBoth modes tested with Intel P30 Strataflash part on Xilinx ML501 board.\n\nIs implemented in the ORPSoC ml501 board port. A software driver for, and programming utility using this core can also be found in ORPSoC. XIP has been tested and works for OR1200 processor in ORPSoC.\n\nSimple mode has been found to work fine with Strataflash drivers found in u-boot and Linux.\n\nSee the README under the doc/ path for further information." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - julius name: cfi_ctrl status: Alpha svn-updated: Oct 23, 2011 updated: Oct 23, 2011 wishbone-compliant: 0 - category: Communication controller created: Aug 31, 2012 description: "===== \n Description =====\n\nCheap Ethernet interface\nRealization of Ethernet interface and protocols optimized for minimal external components and FPGA resources.\nFPGA may connecting through transformer or directly to twisted pairs (on your own risk).\n\nFeatures\n- 10BASE-TX interface (10 MBit/sec) full-duplex (thanks to fpga4fun.com).\n- Base functional of ARP (reqest, reply), ICMP (reply), UDP protocols (server, client).\n- Maximum packet size is 1 kb (fragmentation not supported).\n\nRequired 50MHz/48Mhz and 20MHz clocks, 8kbit block memory, ~800 slices.\nTested on Spartan 3E 500 with transformer and direct connection to twisted pair." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - graver name: cheap_ethernet status: Beta svn-updated: Aug 31, 2012 updated: Aug 31, 2012 wishbone-compliant: 0 - category: DSP core created: Jun 6, 2012 description: "===== \n Description =====\n\nThis is a structural model for cascaded integrator comb (CIC) decimation filters. The filter consists of integrator, downsampler and comb stages. Each block is developed in behavioral manner, however, the top-level is developed in structural hierarchal manner. A test-bench is included for each single block and for the top-level entity as well." language: SystemC license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: cic status: Stable svn-updated: Jun 8, 2012 updated: Jun 8, 2012 wishbone-compliant: 0 - category: DSP core created: Feb 21, 2011 description: "===== \n Description =====\n\nCascaded integrator-comb (CIC) digital filters are computationally efficient implementations of narrowband lowpass filters and are often embedded in hardware implementations of decimation and interpolation in modern communications systems.\n\nNB: core is written in SystemVerilog." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vadimuzzz name: cic_core status: FPGA proven svn-updated: Mar 7, 2011 updated: Nov 4, 2014 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/clefia-fpga-r2.tar.gz category: Crypto core created: Mar 16, 2014 description: "===== \n Description =====\n\nThe main goal on this research work was to provide a compact hardware CLEFIA structure, while still being able to achieve implementations with adequate throughput and performance, even on low cost devices. Two hardware The structure allow for the cipher and decipher computations with all three Key sizes specified in the algorithm, also the key generation." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - joaocarlos name: clefia-fpga status: FPGA proven svn-updated: Mar 17, 2014 updated: Mar 17, 2014 wishbone-compliant: 0 - category: Video controller created: Aug 28, 2006 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - michland - vv_gulyaev name: color_converter status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 23, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Oct 18, 2011 description: "===== \n Description =====\n\nGaussian Pseudo-random Number Generator is a fix-point entity implemented with VHDL, used for generating complex Gaussian pseudo-random numbers. The generator can be further divided into two stages. The first stage is a uniform pseudo-random number generator called Mersenne Twister, and the second is a conversion stage. Mersenne Twister provides uniform pseudo-random number sequence with an astronomical period of 2^19937-1 up to 32-bit accuracy, using only 624 words working area [1]. A conversion model was built upon Mersenne Twister to filter valid pairs of numbers and convert uniform pseudo-random numbers into complex Gaussian pseudo-random numbers. The motivation of the project is to generate massive numbers of complex Gaussian random numbers in parallel to simulate AWGN (Additive White Gaussian Noise) channels for mobile communication MIMO (Multiple Input, Multiple Output) systems." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - cowboyor - omega675 - chasky name: complex-gaussian-pseudo-random-number-generator status: Planning svn-updated: Dec 21, 2011 updated: Dec 21, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Apr 10, 2009 description: "===== \n Definition =====\n\nA Complex arithmetic library for arithmetic operations is needed in many signal processing applications. This project will present a complex operations library for SystemC based designs. Some of the operations like multiplication, division and square root are based on Cordic algorithms in order to reduce the resources needed for implementation. Eventhough the library is based on the complex library of the Agility Compiler Software but nearly all of the operations were modified and improved. The operations included within this project are;\naddition (done)\nsubtraction (done)\nmultiplication (done)\ndivision (done)\npolar to cartesian representation conversion (done)\ncartesian to polar representation conversion (done)\nconjugate (done)\nsquare root (done)" language: SystemC license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tamero name: complexarithmetic status: Alpha svn-updated: May 29, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Sep 14, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - iloveliora name: complexise status: Alpha svn-updated: Sep 14, 2010 updated: Sep 14, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Sep 6, 2010 description: "===== \n download =====" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - yanzixuan name: configurable_crc_core status: Alpha svn-updated: Sep 7, 2010 updated: Sep 9, 2010 wishbone-compliant: 0 - category: Other created: Jul 17, 2011 description: "===== \n Description =====\n\nThis application parses a Verilog define file and presents a GUI to the user" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback - linus name: configurator status: Beta svn-updated: Aug 30, 2011 updated: Aug 24, 2011 wishbone-compliant: 0 - category: Other created: Oct 17, 2011 description: "===== \n CONNECT-6 SOLVER =====\n\nConnect-6 is usually played on a 19 \xC3\x97 19 GO Board, with each player having either black or\nwhite pieces. The Black starts the game with only one move, and after that each player makes\ntwo moves at a time. The game stops when one of the player forms a vertical, horizontal or\ndiagonal line connecting six pieces of his color, or the board is full.\n\n\n The fact that makes this game more interesting, is that each player makes two moves at a time, \nexcept for the first move. This considerably increases the search space for moves and end-games. \nBecause of these reasons, Connect-6 has gained popularity in the AI community, and has been included \nin the Computer Olympiad. \n\nIn this project we synthesize an open source connect-6 program( available at http://risujin.org/connectk/)\ninto hardware using HLS tools.\n \n\n\n \n \n \n\n===== \n README =====\n\nREADME:\n-------------------------------------------------------------------\nDEMO:\n\nBefore you begin exploring the project you can find demo files in the DEMO folder, which contains the original connect-k player, the bitstream for DE2 Board from ALTERA.\n\nDownload DE2.sof into the altera DE2 board, and connect it to your PC with RS232 cable.\n\nLaunch connectk and choose \"serial port \" in the drop down menu for players.\n\nit should be able to play with the DE2 board now.\n-------------------------------------------------------------------\nBUILD_SCC:\n\nIn this folder you can run the complete build flow for synphonycc.\n\nInstall SYNPHONYCC, and QUARTUS, change the MaKefile so that the variable SCC point to your installation.\n-------------------------------------------------------------------\nMake Targets:\n\nmake: This will compile the golden \"C\" code (synthesizable) and run a test.\n\nmake synth: This will run the SCC flow, and generate RTL(verilog) which can be found in the folder rtl_package.\n\nmake altera_synth: This will generate the bitstream for DE2 board \"DE2.sof\". it depends on the previous target.\n\nmake fpga: This runs the complete flow downto testing the board.\n-------------------------------------------------------------------\nfolders:\n\nBUILD_SRC/synth_src: contains the synthesizable \"C/C++\" code, which is a modified version of original source code found in\nCONNECTK folder.\n\nBUILD_SRC/scc_scripts: contains the scripts for scc, whic are used when you do make synth.\n\nDE2: Contains the wrapper code, pin assignments etc. for the DE2 board.\n-------------------------------------------------------------------" language: C/C++ license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: connect-6 status: FPGA proven svn-updated: May 17, 2012 updated: Feb 14, 2012 wishbone-compliant: 0 - category: ECC core created: Dec 1, 2001 description: "===== \n Description =====\n\n\n \n\n===== \n Features =====\n\n- feature1\n- feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\n- ...\n- ..." language: VHDL license: unknown maintainers: - sushanta name: const_encoder status: Planning svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Other created: May 23, 2009 description: "===== \n Description =====\n\nThe Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two specific words to its control registers. The intention of the module is to bring an embedded system back to a \xE2\x80\x9Cgood\xE2\x80\x9D state after the software program has lost control of the system." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - rehayes name: cop status: Design done svn-updated: Sep 17, 2011 updated: Jan 27, 2010 wishbone-compliant: 1 - category: Processor created: Nov 17, 2011 description: "===== \n Description =====\n\ncopyBlaze is a from-scratch synthesizable & behavioral VHDL clone of Ken Chapman's popular 8bit PicoBlaze embedded microcontroller.\nIt support wishbone interface.\nAssembler and C Compiler are used in the developpement.\n \n\n\n \n \n \n\n===== \n STATUS =====\n\nThe developpement is still in progress.\n* All the PicoBlaze III instructions have been tested.\n* Actually the wishbone instructions are in test validation\n* PBCC Compiler is in test.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\ncopyBalze have the followings features:\n\n'''SET INSTRUCTION'''\n* picoblaze III instruction compatible + specific wishbone instructions\n* 1k x 18bits code ROM capability\n* portable (no vendor specifique optimisation)\n\n'''I/O INTERFACE'''\n* picoblaze III compatible\n* + wishbone I/O\n* + sleep input signal I\n\n'''CONFIGURATION'''\n* ScratchPad size\n* Stack size\n* Interrupt Vector address\n* Data width size (8bit default. not tested with others values)\n\n'''WISHBONE (Not finished yet)'''\n* only 8bit single Read/Write capability is supported\n* two new instructions have been added to support wishbone\n* wait states is integrated \n \n\n\n \n \n \n\n===== \n Design =====\n\nThe design of copyBlaze is based on this documents:\n* [[http://www.xilinx.com/support/documentation/ip_documentation/ug129.pdf | PicoBlaze\xE2\x84\xA2 8-bit Embedded Microcontroller User Guide]]\n* ieee.numeric_std library\n \n\n\n \n \n \n\n===== \n Wishbone =====\n\nThe principe of the wishbone copyBlaze interface is :\n* develop a hardware wishbone compatible interface\n* develop 2 instructions for acsess the wishbone interface from copyBlaze.\n* wait states is supported (but need more tests)\n\nActually only two instructions have been added to the copyBlaze instructions (picoblaze III instruction set).\nTheese two instruction can perform a \"single 8 bit Read/Write\"\n\n* WBWRSING\tsX,\t(sY); 8 bit Single Write : DAT_O = sX, ADR_O = sY\n* WBRDSING\tsX,\t(sY); 8 bit Single Read : sX = DAT_I, ADR_O = sY\n\nfutur wishbone Burst access can be developped for copyBlaze ScrachPad access.\n\nthe wishbone interface have been tested with the followings wishbone cores:\n* wb_gpio\n* wb_timer (with interrupt)\n* wb_uart (with interrupt)\n \n\n\n \n \n \n\n===== \n Software Dev =====\n\n'''ASSEMBLER'''\n* [[http://code.google.com/p/pblazasm | pBlazeASM]] from mediatronix (modified for specific wishbone instructions)\n* KCPASM3.EXE\n\n'''COMPILER'''\n* [[http://www.fit.vutbr.cz/~meduna/work/doku.php?id=projects:vlam:pbcc:pbcc | \"PicoBlaze C Compiler (PBCC)\"]]\n* the PBCC version 2011-10-24 have been updated to be based on sdcc-src-3.1.0 release\n* the port for picoblaze processor is organised as a patch : sdcc-3.1.0-pblaze_[-NaurbB].patch\n\n* complete tool chain is used to generate VHDL code ROM from *.c file\n* the process is : *.c => (PBCC) => *.psm => (pBlazASM) => *.hex => (cpBlazeMRG) *.vhd\n\n'''ENVIRONEMENT'''\n* cygwin\n* makefiles for assembler\n* automatically VHDL synthetisable Code ROM. \n \n\n\n \n \n \n\n===== \n Test =====\n\n'''VALIDATION'''\n* all the UG129 doc instruction have been tested ok\n* the wishbone instruction are still in developpement \n \n\n\n \n \n \n\n===== \n Integration =====\n\n'''SYNTHESE'''\n- Actel\n* Target : ProASIC3 A3P250_VQFP100_Std\n* Tools : Libero v9.1 SP3\n* result : Estimated Frequency : 32.4 MHz | Core Cells :2653\n\n- Other\n* other vendor integration are encouraged \n \n\n\n \n \n \n\n===== \n TODO =====\n\n'''WISHBONE'''\n* finish the wishbone bus integration (single Octet Read/Write)\n* forbideen interruption during wait states\n\n'''ALU'''\n - change the carry ahead adder\n\n'''DOCUMENTATION'''\n* commentaire\n* documentation\n* results of synthese \n \n\n\n \n \n \n\n===== \n Futur Evolution =====\n\n* Picoblaze-6 core compatibility\n* Hardware debug tools" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ameziti name: copyblaze status: Mature svn-updated: Dec 25, 2011 updated: May 23, 2013 wishbone-compliant: 1 - category: Arithmetic core created: Sep 25, 2001 description: "===== \n Description =====\n\nThe CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.\n\n \n\n\n \n \n \n\n===== \n Core Description =====\n\nAs the name suggests the CORDIC algorithm was developed for rotating coordinates, a piece of hardware for doing real-time navigational computations in the 1950's. The CORDIC uses a sequence like successive approximation to reach its results. The nice part is it does this by adding/subtracting and shifting only.\n\nSuppose we want to rotate a point(X,Y) by an angle(Z). The coordinates for the new point(Xnew, Ynew) are:\n\nXnew = X * cos(Z) - Y * sin(Z)\nYnew = Y * cos(Z) + X * sin(Z)\n\nOr rewritten:\n\nXnew / cos(Z) = X - Y * tan(Z)\nYnew / cos(Z) = Y + X * tan(Z)\n\nIt is possible to break the angle into small pieces, such that the tangents of these pieces are always a power of 2. This results in the following equations: \n\nX(n+1) = P(n) * ( X(n) - Y(n) / 2^n)\nY(n+1) = P(n) * ( Y(n) + X(n) / 2^n)\nZ(n) = atan(1/2^n)\n\nThe atan(1/2^n) has to be pre-computed, because the algorithm uses it to approximate the angle. The P(n) factor can be eliminated from the equations by pre-computing its final result. If we multiply all P(n)'s together we get the aggregate constant.\n\nP = cos(atan(1/2^0)) * cos(atan(1/2^1)) * cos(atan(1/2^2))....cos(atan(1/2^n)) \n\nThis is a constant which reaches 0.607... Depending on the number of iterations and the number of bits used. The final equations look like this:\n\nXnew = 0.607... * sum( X(n) - Y(n) / 2^n)\nYnew = 0.607... * sum( Y(n) + X(n) / 2^n)\n\nNow it is clear how we can simply implement this algorithm, it only uses shifts and adds/subs. Or in a program-like style:\n\nFor i=0 to n-1\n\nIf (Z(n) >= 0) then\n\nX(n + 1) := X(n) \xE2\x80\x93 (Yn/2^n);\nY(n + 1) := Y(n) + (Xn/2^n);\nZ(n + 1) := Z(n) \xE2\x80\x93 atan(1/2^i);\n\nElse\n\nX(n + 1) := X(n) + (Yn/2^n);\nY(n + 1) := Y(n) \xE2\x80\x93 (Xn/2^n);\nZ(n + 1) := Z(n) + atan(1/2^i);\n\nEnd if;\n\nEnd for;\n\nWhere 'n' represents the number of iterations.\n \n\n\n \n \n \n\n===== \n Implementation =====\n\nSee the on-line documentation for the theory behind and information about the available CORDIC cores.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Design is available in VHDL from OpenCores CVS via cvsweb or via cvsget \n- ToDo: finish documentation" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - rherveille name: cordic status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 8, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Apr 17, 2014 description: "===== \n Description =====\n\none way to make cordic faster is to use redundant arithmetics which would allow constant and low carry propagation delay. However, it's difficult to evaluate the sign of redundant number, some methods has been proposed for rotation mode, but to my knowledge no one has tried to build a redundant number based cordic core that can work in all 4 modes. This cordic core extended existing methods for circular mode so that it can also work in hcrm and hcvm modes with some restrictions on x(x must belong to a range of [1/4,1])" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ghostincircuit name: cordic_signed_digit status: Empty updated: Apr 18, 2014 wishbone-compliant: 0 - category: System on Chip created: Apr 8, 2004 description: "===== \n Description =====\n\nA open source ARM vhdl model. \nThe annotated vhdl source can be browsed here:\nhttp://cfw.sourceforge.net/build_html/vhdl/index.htm\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nNote: This version (0.8) is still beta. Until we switch to release the arm iu will not be fully functional. Until then you are welcome to join development. Testers, coders, moderators, freaks, jobless and nerds are welcome (professionals are tolerated). \n\n- ARM instruction set\n- Processor framework\n\n \n \n\n\n \n \n \n\n===== \n Status =====\n\n- Version 0.8 Beta" language: VHDL license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - eiselekd - meesisto - tarookumichi name: core_arm status: Beta svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Nov 20, 2013 description: "===== \n Description =====\n\nCortex M3 compatible CPU. \n\nUsed for the Arduino Due compatible Cortex M3 SoC.\n\nPlaying field to demonstrate the power of C-Slow Retiming and System Hyper Pipelining.\n\nMore to come soon,\n\nCheers, Tobias" language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tobil name: cortex_m3 status: Empty updated: Nov 21, 2013 wishbone-compliant: 0 - alternate-download: http://thebeekeeper.net/hw/cowgirl.zip category: Processor created: Mar 27, 2006 description: "===== \n Status =====\n\n- Initial tests and debugging have been performed.\n- Initial code revision is 80-90% complete\n- Initial cvs commit (27 Mar 2006)\n \n\n\n \n \n \n\n===== \n Features =====\n\nLogical and arithmetic operations have been tested and are functional.\n\nPretty much everything works, as far as my test have shown. I've also writen some software that generates a ROM in VHDL from assembly source code. It's available at my website. Plus, there's an assembly simulator!\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis is an implementation of an instruction set that I created. It's not a particularly useful thing to do, but it's something I've always been interested in. The instruction set bears a strong resemblance to the MIPS R3000, but this wasn't exactly deliberate. It's really the only instruction set I've been heavily exposed to.\n\nI'm keeping design documents and software I've written for this project on my website if anybody's interested. There's also a copy of the source and the modelsim project that I use, but it will most likely be updated less than the cvs version here." homepage: http://thebeekeeper.net/hardware language: VHDL license: unknown maintainers: - thebeekeeper name: cowgirl status: Design done svn-updated: Mar 10, 2009 updated: May 31, 2007 wishbone-compliant: 0 - category: Communication controller created: Jul 19, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Other license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - vinogradov name: cpri_core status: Empty updated: Jul 19, 2011 wishbone-compliant: 0 - category: Processor created: Jan 23, 2008 description: "===== \n Description =====\n\nThis is a VHDL/Verilog IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetch. The ready signal is usable for DMA operations or multiprocessing. Signal sync can be used for software/hardware debugging via single stepping (single cycles or complete op codes) the 6502.\nThis core was successfully tested in an APPLE ][+ SoC (completely designed into a FPGA with Z80 Softcard, DISK2 System, 80C Card, Language Card and 48kB of main memory).\n\nPlease feel free to contact me for any reasons like ideas or error messages.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- true cycle timing for all official opcodes \n- unknown op's decoded as \"NOP/0xEA\" \n- one clock source \n- input signal \"rdy_i\" for generating waitstates (see original documentation of R6502) \n- output signal \"sync_o\" to indicate an op fetch (see original documentation of R6502) \n- input signal \"so_n_i\" sets the internal OV Flag (see original documentation of R6502) \n- fully synthesizable VHDL and Verilog\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nCORE: Ready for use and downloadable via SVN\nLICENSE: Puplished under GPL V3\nDOCUMENTATION: \"on working\"\nTESTBENCHES: \"on working\"\nTESTSOFTWARE: \"on working\"\n\nQUALITY:\n- all op codes: simulated and approved under real working conditions (APPLE ][plus SoC)\n- irq_n_i: simulated and run in real environment\n- nmi_n_i: simulated and run in real environment\n- so_n_i: only simulated\n- all other signals: simulated and approved under real working conditions (APPLE ][plus SoC)\n\nHistory:\n(Mar-15-2010)\n- Correct interrupt sequences for NMI and IRQ\n\n(Feb-25-2009)\n- Correct \"RTI\" (wrong: use of stack pointer)\n- Rename all states of \"FSM Execution Unit\" for better reading\n- Update HTML documentation\n- (90%) Finish working for Specification of cpu6502_tc\n\n(Jan-09-2009)\n- Phaze 2: Remove unused nets, registers and modules\n- Added Verilog source files on demand by customers (for trial use)\n\n(Jan-04-2009)\n- Remove unused nets, registers and modules\n- Update HTML documentation to visualize the Execution unit\n\n(Apr-17-2008)\n- State of project\n- CVS loaded with new core and HTML documentation\n- correct the handling of the stack while BRK, IRQ and NMI\n- correct the handling of \"B\" flag while BRK\n- correct the alignment between addresses and data while BRK, IRQ and NMI when writing onto the stack" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - fpga_is_funny name: cpu6502_true_cycle status: FPGA proven svn-updated: Mar 15, 2010 updated: Jul 24, 2013 wishbone-compliant: 0 - category: Processor created: Apr 12, 2008 description: "===== \n Description =====\n\nThe 65C02 by Rockwell is the upgraded version of the legendary Rockwell's R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the R65C02. This soft core was generated in VHDL and was designed with Mentor's HDL Designer.\nIt comes also with graphical views formatted in HTML to show and explain very clearly the hierarchy of the whole design.\n\nPlease feel free to tell me any ideas, errors or some thing else like special functions, test benches or documentation. Use the \"Tracker\" link to do this.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- true cycle timing for all official opcodes \n- unknown op's decoded as \"NOP/special op codes\" \n- one clock source \n- input signal \"rdy_i\" for generating waitstates (see attached specification of R65C02) \n- output signal \"sync_o\" to indicate an op fetch (see attached specification of R65C02) \n- input signal \"so_n_i\" sets the internal OV Flag (see attached specification of R65C02) \n- fully synthesizable VHDL\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Based on the cpu6502_tc core\n- This version will support Rockwell's 65C02 (other variants are planed for future)\n- Core is running in a APPLE //e SoC and tested under ProDOS V2.0.3 and\n Klaus Dormann's 6502/65c02 test suite written in assembler.\n\nCORE: \"READY - RELEASE CANDIDATE\"\nLICENSE: Puplished under GPL V3\nDOCUMENTATION: \"on working\"\nTESTBENCHES: \"on working\"\nTESTSOFTWARE: \"ready\"\n\nQUALITY:\n- all of the new R65C02 op codes are tested under real working conditions with\n Klaus Dormann's 6502/65c02 test suite written in assembler (included in /asm now)\n- irq_n_i: not fully tested on real hardware yet\n- nmi_n_i: not fully tested on real hardware yet\n- so_n_i: not fully tested on real hardware yet\n\nHistory\n\nAug-02-2013\nRevision 1.5 RC 2013/07/31 11:53:00 (RELEASE CANDIDATE)\n- Bug Fix CMP (IND) - wrongly decoded as function AND\n- Bug Fix BRK should clear decimal flag in P Reg\n- Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address\n- Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) - new NOPs created\n- Bug Fix DECIMAL ADC and SBC (all op codes - \"C\" flag was computed wrong)\n- Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed\n- Bug Fix RTI - should increment stack pointer\n- Bug Fix \"E\" & \"B\" flags (Bits 5 & 4) - should be always \"1\" in P Reg. Change \"RES\", \"RTI\", \"IRQ\" & \"NMI\" substates.\n- Bug Fix ADC and SBC (all sub codes - \"Overflow\" flag was computed wrong)\n- Bug Fix RMB, SMB Bug - Bit position decoded wrong\nRevision 1.4 2013/07/21 11:11:00 (internal copy only - not published)\n- Changing the title block and internal revision history\n- Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH)\n\nFeb-25-2009\n- Correct \"RTI\" (wrong: use of stack pointer)\n- Correct \"RMBx\" & \"SMBx\" (wrong: bit translation)\n- Rename all states of \"FSM Execution Unit\" for better reading\n- (85%) Finish working for Specification of cpu65C02_tc\n- Correct timing for addressing mode \"ABS,X\" for \"INC\" (wrong: 6 cycles instead of 7)\n- Optimize end states of \"STA\" (s197,s207,s200,s213)\n\nJan-04-2009\n- Deleted unused/duplicated nets, registers and modules. Renamed some blocks. Synthesis run now without warnings.\n\nDec-01-2008\n- CVS loaded with updated finite state machine (bug fixes for interrupts)\n- Include an example for specification (copied from cpu6502_tc - on working)\n\nAug-05-2008\n- CVS loaded with BETA source files (VHDL)" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - fpga_is_funny name: cpu65c02_true_cycle status: FPGA proven svn-updated: Aug 2, 2013 updated: Aug 2, 2013 wishbone-compliant: 0 - category: Processor created: Oct 4, 2006 description: "===== \n Description =====\n\nThis is an 8080 core I created as a project to get to know Verilog. \n\nThe 8080 was the second in the series 8008->8080->Z80. It was the second\ncommercially available single chip CPU (disregarding the required\nclock and demultiplexor chips), after the 4 bit 4004. Besides being an interesting\nproject, it also can serve as a very compact core, suitable for a supervisor role on an\nFPGA with other blocks. It has extensive support, all freely available, including\nassemblers, compilers, an operating system (CP/M).\n\nAlthough the Z80 is a more popular core due to being a superset of the 8080, the Z80\ntakes considerably more chip real estate. Its likely that more than 50% of available\nsoftware is 8080 only, since the Z80 was often used to run 8080 code. For example,\nthe CP/M OS itself was 8080 only code.\n\nThis means that the 8080 can be an attractive core if you want the great support of\nthis processor series, but need it to fit in less space.\n\nThe core is fully instruction compatible with 8080, but not signal compatible. The\noriginal 8080 was a multiplexed nightmare. one of the original selling points of the Z80\nwas its cleanup of the signals, and the 8080 itself had a companion chip that\ndemultiplexed it.\n\nThere are a few other similar chips on opencores. This one is a bit different because\nit is only 8080, and is in native Verilog (not a translation). Further, the goal was to\nget it down to the minimum in both source size and synthesized size.\n\nI also suspect there is a preverse advantage to running this core: its original\nmanufacturer no longer makes it, or any compatible chip, and it has probally passed\nfrom any IP protection long ago. However, as usual, Should warn that I have not\nverified any legal status on this processor and do not speak from any knowledge or\nauthority on the matter.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nInstruction set: 8080\nData size: 8 bit\nAddress: 16 bit\nInstruction: 8 bit\nLanguage: Verilog\nLicense: None (public domain)\nCreated under: Xilinx ISE, free webpack edition\nDevice: xc3c1000-4ft256\nSlices: 1104\nSlice flip flops: 296\n4 input LUTs: 2082\nBonded IOBs: 33\nGCLKs: 1\n\nThe CPU works entirely on positive clock edges and signals, but could be reconfigured\neasily. It has wait state ability, and simple interrupt request/acknowledge structure.\nThe original 8080 method of fetching an external instruction to satisfy the interrupt is\npreserved, and it is left up to an external interrupt controller to provide vectoring.\n\nI have no problem with, and in fact encourage, commercial use, modifications (public\nand private), etc.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nNotice:\n\nThe CPU8080 project has passed a very complete CPU instruction test, and has run\na medium (but not large) piece of code, the SCS1 monitor, this morning. I have marked\nthe project as complete.\n\nTonight, after consideration, I think I will call it complete, at least for a while. I was\nplanning to take the design to a CP/M boot, but I think I have accomplished my\noriginal purpose, and more. I have high confidence in this core, and I hope you all can\nfind uses for it. In the meantime, I have other projects, and my paid work calling.\n\nFeel free to email me questions. Good luck, and good success with your projects.\n\n2006/11/20 Status:\n\nThe SCS1 monitor/assembler signs on!\n\nhttp://www.moorecad.com/fpga2.jpg\n\nHere it is shown signing on, and executing a \"dump 0 30\" command to dump the first\n30h bytes in the system.\n\nThe wires trailing off the XESS board are the Intronix USB analyzer wires.\n\nNote that I added the sign on message to SCS1, normally it has no sign on.\n\nThis marks the first major piece of original 8080 software CPU8080 has run. I am\npromoting the project status because of it.\n\n2006/11/18 Status:\n\ncpu8080 passes the Kelly Smith test, both in simulation and in hardware. There were\n8 different cpu bugs solved by my count, so this is a very important series of updates.\nKelly Smith is an 8080 CPU test created in 1980 under the Microcosm Associates\nbrand name, and donated to the \"SIG/M\" CP/M user's group.\n\nIts a very complete CPU test for all flags, modes and instructions, so passing that is\nvery good for the design.\n\nChris Strahm's modifications were incorporated, which include the following:\n\n1. All constants that are not a single bit have their bit width specified. This was\nrequired to remove Quartus errors.\n2. Wait state ability is now optional. See cpu8080.v.\n3. I/O instructions are now optional. See cpu8080.v.\n\nThe last two are part of the \"super compact\" core concept that Mr. Strahm is\nfollowing. See the section below for more details on this.\n\n2006/11/15 Status:\n\nThe ADM 3A terminal emulation is very complete now. There are only a few modes\nmissing, reduced intensity and graphics. There are still a few issues with the\nemulation, but they are minor, and should not impact any software.\n\nGoing forward, I have hooked up with Rich Cini's excellent Altair website and project\npage at:\n\nhttp://www.altair32.com\n\nAnd the material there is really going to help me speed up this work.\n\nI want to emphasize that I am not creating a \"computer history\" project here. The\nlogic is simple: The most complete test of a CPU is to run an extensive suite of\nexisting software, and that means existing operating systems, compilers and utilities,\nof which the 8080 has quite a large supply. With the 8080 being more than 30 years\nold, any such systems are going to look like a history project. The reason it's useful\nto me is that a popular computer has a lot of preexisting software available for it.\n\nIn fact, Rich's site has already taken care of a large peice of work I had yet to do,\nthere is a full CPU test suite available there, 8080test.asm. The code is dated 1980,\nand I'll bet the author never would have imagined it would be used to proof a new\nimplementation of the 8080. I'll post the result when that runs, which should be\nshortly.\n\nMoving forward from there, the only piece of hardware left to emulate is the Altair\nfloppy disc controller, which looks pretty simple. After that, I will be able to use\nRich's rich catalog of disc images including CP/M 2.2, Microsoft Basic and others to\ndo a full 8080 checkout without so much as performing an assembly.\n\nThere is a Altera/Quartus version of the CPU being developed by a user who has been\nemailing me of late. I hope to have more news on this later.\n\nPrevious status:\n\nThe design runs, abet with a simple program, on an XESS 1000 board. It prints\n\"Hello, FPGA world\" on a VGA display. Here is a picture:\n\nhttp://www.moorecad.com/fpga.JPG\n\nThere have been a lot of improvements since the last version. First, I switched to the\n50 mhz clkb, which gets divided down from the 100 XESS board clock. There are a\ncouple of reasons for this. The CPU core appeared to be deeply unhappy about running\nat the top speed of the FPGA, and was showing internal failures. Second, the raw\n100 mhz clock was coming direct from the oscillator, which I believe has a non-50/50\nduty cycle. Since I have been using both edges, that's bad.\n\nSecond, I switched most clocking to positive edges. In fact, there is only one negedge\nleft, and that's because I haven't had time to test it.\n\nThird, all of the read and write signals from the CPU, I/O and memory, were extended\nby a cycle. This was required to get the single edge clocking going, and relaxes the\ntiming all around.\n\nWith these changes, the design is now running quite well. The \"hello, FPGA world\"\nexample now runs a terminal emulator loop, and the ADM 3A dumb terminal is fairly\ncomplete. It features shift, caps, and control keys on input, and obeys the ADM 3A\ncontrols, most of them, on output. See vgachr.v for details on what is and is not\nimplemented.\n\nBy entering various characters in the terminal mode, I have tested all the usual\ncontrol characters, line up, down, left, right, clear screen, etc.\n\nFor anyone who has got far with trying this design out, I'll apologize in advance for\nthe character font. It was banged out in about 2 hours, I just wanted something\nfor test. I'll be cleaning it up later.\n\nI'm currently using a Intronix 34 channel USB logic analyzer to verify the design on\nhardware. Chipscope was just out of reach for me, it not only takes about $800 for\na full version, but requires you also to purchase the full, not free, version of ISE,\nbringing the total cost to about $3000. I have all of the CPU signals brought out to\nthe analyzer, plus you'll notice an 8 bit \"debug\" bus that replaces the top 8 bits\nof the address lines. This technique allows me to attach various signals to the \"bus\"\nto be routed out to the external analyzer, and I can swap this to and from the debug\nbus by modifying the pin assignments at the top level.\n\nWhat's next is the Imsai monitor/assembler discussed below. I'm going to run that\nunder a simulator first, so that is 1 to 2 weeks off. I'll post a new picture when that\nruns.\n\nThe testbench so far on the hardware consists of the following:\n\n8080 core\nROM to store test program (\"hello\"/terminal emulator)\nRAM\nSelect controller\nInterrupt controller (no plans to use this on the hardware)\nADM 3A Dumb Terminal emulator\n\nThe wait state capability, as of this writing, has not been verified. For anyone curious,\nthe \"select controller\" has bits reserved for this, bits 0 and 1 of the mask register\nwill select from 0 to 3 wait states for that select.\n\nI plan to add a bus hold (tristate) and acknowledge pins and mode, this will allow\nconnection of an external DMA. I don't plan to actually create a DMA, since this\nproject needs to end (da' wife is getting annoyed). I'll just activate the hold pin and\nwatch for high-z on all outputs.\n\nI also plan to add a NMI (non maskable interrupt) pin. That will get a simple test\nas well.\n\nI placed an assembler file in the source that I will use for first tests with the core:\n\nscs1.asm - An IMSAI monitor/assembler\n\nThis is a famous old program for the 8080. It preceeds CP/M. It's interesting\nas first test because it only uses a single I/O port to the console.\n\n \n\n\n \n \n \n\n===== \n Development systems =====\n\nThere is TONS of software available for the 8080. The best way to go about it is to run\na CP/M simulator on your host machine. Here are a few:\n\nhttp://www.schorn.ch/cpm/intro.html\nhttp://www.moria.de/~michael/yaze-cpm3/\n\nFor development systems, try these forums:\n\nhttp://www.retroarchive.org\nhttp://www.cpm.z80.de/\n\nThis includes CP/M, assemblers, a basic compiler, the original Microsoft Basic interpreter,\nFortan compilers, Cobol, C (of course), Pascal, Modula, Algol, and Ada.\n\nYou can find a lot more with a simple search.\n\nCP/M itself is a good, small operating system to run on your target if you wish. It can be\nadapted to your target hardware with a very simple BIOS, which can run using a flash\nmemory as the \"disk\" for it. The entire system fits in less than 256kb (yes, actually less\nthan a meg), which was the common size of a floppy disk back when this CPU was\npopular.\n\nIf you choose to run CP/M, the amount of software available is truly amazing. Try\nthese sections of the retroarchive:\n\nhttp://www.retroarchive.org/cpm/cdrom/\nhttp://www.retroarchive.org/cpm/cdrom/SIMTEL/SIGM/\n\nCP/M was a popular system from the start of the home computer revolution to well\ninto the 1980's, and continues to have a following today.\n\nI use a proprietary development system, the IP toolset, at my web site. This is not\nmeant as a plug for that system (the 8080 version is not even for sale), but simply to\nexplain why you will see a lot of the support files for the assembly code configured\nfor that system. There is nothing I have here that you cannot find for free at the\nabove sources. The main advantage I get from the IP toolset is that it runs natively\nunder Windows/XP.\n \n\n\n \n \n \n\n===== \n Legal notice =====\n\nThe 8080 CPU implemented here was created as a not for profit student project. I don't\nknow if its use will violate patents, copyrights, trademark rights or other rights. The\nsource files were created entirely by me, but their use, commercial or otherwise, and\nany legal, consequences that arise, are entirely the responsibility of the user. I\nspecifically deny that this core is usable for life support systems, or any other system\nthat can or will cause, directly or indirectly, any harm to persons or property.\n\nTHESE SOURCE FILES ARE PROVIDED \"AS IS\" AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT\nLIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND\nFITNESS FOR A PARTICULAR PURPOSE. \n \n\n\n \n \n \n\n===== \n CVS Format =====\n\nThe CVS repository is under cpu8080.\n\nI'll apologize in advance, but repository is basically a dump of my Xilinx ISE directory. This\nis not the clean way to do it, but it does have the advantage that if you are running\nISE, you can download the entire thing and just go. Here is a list of the important files\nin the directory:\n\nreadme.txt - A copy of this text\ncpu8080.txt - The documentation for the project, in plain ASCII.\ncpu8080.v - The 8080 core\ntestbench.v - The testbench for the core. Also contains the peripherals for the core,\nsuch as the peripheral select controller, the interrupt controller, the test ROM, RAM, and\nanything else required.\nvgachr.v - The ADM 3A dumb terminal emulator, keyboard interface, and MITS Serial\nI/O emulator.\nvga.vhd - The stripped XESS vga timing generator/pixel shift register.\nps2_kbd.vhd - The XESS keyboard interface.\n\nThe other files are the testbench running files, like the stimulus package. I don't even\nknow what half of them are, sorry, I only started using the system 2 weeks ago!\n \n\n\n \n \n \n\n===== \n Shameless plug =====\n\nFor people who want ask me questions, or find out more about what I am doing, my\ninformation is:\n\nEmail: samiam@moorecad.com\nWeb page: http://www.moorecad.com\n\nDisclaimer: The above web page does include commercial content, ads, rants, etc.\n \n\n\n \n \n \n\n===== \n Documentation =====\n\nHere are some locations that have the original 8080 documentation:\n\nhttp://vt100.net/mirror/harte/Intel%208080%20Manual/\nhttp://www.hartetechnologies.com/manuals/Intel%208080%20Manual/\nhttp://www.imsai.net/whatsnew.htm\nhttp://www.classiccmp.org/dunfield/heath/index.htm\n\nThat last link contains the \"8080 Assembly language programming manual\", which is the\nbook that I used to construct cpu8080, from my original coffee stained edition, bought in\n1977.\n\nFor people interested in the difference between the 8080 and its predecessor, the 8008,\nthe following site is available:\n\nhttp://www.bitsavers.org/pdf/intel/MCS8/\n\nYou can find the User's reference manual for the ADM 3A dumb terminal, which was used\nto produce the emulation used in this design, at:\n\nhttp://www.bitsavers.org/pdf/learSiegler/\n\nYou can find a copy of the manual for the REALLY elementary MITS Serial I/O card used\nto construct the serial port emulation on the design at:\n\nhttp://www.classiccmp.org/dunfield/s100c/mits/88sio_1.pdf\n \n\n\n \n \n \n\n===== \n The super compact core =====\n\nChris Strahm has been working on a \"super compact\" 8080 core. The idea is to strip out\nfeatures that are not absolutely required for most designs.\n\nHe's been reporting cell counts (LUTS) of below 1500." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - samiam95124 name: cpu8080 status: Stable svn-updated: Mar 10, 2009 updated: Mar 6, 2012 wishbone-compliant: 0 - category: System on Chip created: Jan 4, 2010 description: "===== \n Overview =====\n\nThis is a lecture about designing a SoC in VHDL.\n\nEverything runs under Linux - no more Windows!\n\nCheck it out and then start at the file named index.html.\n\nEnjoy!" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: cpu_lecture status: Stable svn-updated: Apr 1, 2010 updated: Apr 13, 2011 wishbone-compliant: 0 - category: Processor created: Sep 3, 2003 description: "===== \n Description =====\n\nCpugen (TM) generates customizable RISC cpu cores. \nIt allows direct customization of address/data/instruction bus size, \ninterrupt handling, indirect addressing, data/instruction latency \ntimings and custom instructions definition.\nIt is targeted to low size FPGAs, easy to use and getting started with.\nGNU VHDL source code provided.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n1) Portability:\n\nvendor dependent blocks (ex. memory blocks) are kept separate from vendor independent logic. \nCustomizable built-in assembler with data/instruction memory files generation; output file formats for the following environments:\n\t\n\t- Altera\n\t- Xilinx\n\t- binary\n\t- testbench\n\n2) Configurability: \n\nIn order to optimize logic resources and take advantage of FPGA flexibility; targeted to low size FPGAs; it permits to define: \n\n\t- address/data/instruction bus size \n\t- stack type/depth \n\t- interrupt \n\t- indirect address \n\t- data/instruction variable latency\n\t- custom instructions support\n\t\n3) Graphical user interface:\n\n \n\n\n\n4) Easy to use and getting started with: \n\n\t- Tutorial and example files are supplied with the package\n\t- Xilinx/Altera 4/8/16/32 bit cpu applications samples\n\t- GNU VHDL source code\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Current release 2.0\n- VHDL simulations \n- Tested on Altera and Xilinx evaluation boards \n- Test/debug currently in progress\n\nPlease contact me for bugs reporting or for obtaining technical support." language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - gferrante name: cpugen status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Dec 31, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - huxiaokai2005 name: cpuh status: Empty updated: Dec 31, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Feb 12, 2013 description: "===== \n Description =====\n\nThis core is a low latency divider that works by caching reciprocal values, then using a multiply to perform the divide rather than the usual divide operation. On first encountering a divide operation the reciprocal of the divisor is calculated, this takes the same amount of time as a normal divide. The next time the same divide is encountered the pre-calculated reciprocal is used. Reciprocals are stored in a small cache similar to a processor data cache.\n\na/b is the same as a * 1/b\n\nIn many cases the divisor 'b' remains the same within a loop. 1/b can be calculated to be essentially a constant; then all that's required is a multiply operation. As in the example, divides are performed using only three clock cycles when the reciprocal can be found in the cache." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: cr_div status: Alpha svn-updated: Feb 12, 2013 updated: Feb 12, 2013 wishbone-compliant: 0 - category: Communication controller created: Sep 28, 2013 description: "===== \n Description =====\n\nVHDL implementation of the CRC check in IEEE 802.15.4 (MAC layer)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: crc802154 status: Stable svn-updated: Sep 29, 2013 updated: Sep 29, 2013 wishbone-compliant: 0 - category: Processor created: Feb 24, 2011 description: "===== \n CRISC CPU Overview =====\n\nThe CRISC CPU is a Complex Reduced Instruction Set CPU. The CPU has 4 data registers 16 bit, 7 data registers 32 bit and 4 address registers 16 bit and 20 opcodes. Top execution speed is one instruction per clock cycle. The CPU can perform simple precision IEEE754 floating point calculations in software. A good compromise between FPGA real estate and (relative) high CPU speed is the top design goal. The first implementation is on Altera Cyclone II EP2C20. The floating point functions sin(), cos(), ... use the CORDIC algorithm. The CPU registers are designed to allow CORDIC implementation with minimum memory access, all CORDIC relevant data is kept in registers.\n\nThe opcode fetch and parameter fetch bus interface translates between the CRISC outer world of instructions with different length and the CRISC inner world of instructions with fixed length. The memory read interface needs 1 to 2 memory cycles to read the opcode and 0 to 3 memory cycles to read the optional parameter. The memory fetch can work independent of the ALUs, a limited pipelining is possible. The memory write interface can output 8 Bit data in 1 memory cycle, 16 Bit data in 1 or 2 memory cycles and 32 Bit data in 2 or 3 cycles. The memory write can work parallel to the ALUs, too. The larger number of cycles is needed if the data is not aligned, that is data starts at an odd memory address.\n\nThe three different types of CPU registers have three different ALUs. The address ALU can work in parallel to the data ALUs, the both data ALUs can not work in parallel. The 16 bit data ALU can perform logic operations like NOT, AND, OR, XOR, but can not perform shift operations. The 32 bit data ALU can perform shift operations but can not perform logic operations. All ALUs can perform arithmetric operations and sign extend operations. The address ALU can only perform ADD, the other ALUs can perform SUB and NEG, too.\n\nThe CRISC CPU has some constant registers with the values 0, 1 and 2. The value 0 is used for the NEG opcode. The values 1 and 2 are used to increment or decrement the program counter PC, A and R registers. The OF latch is used to hold the (sign extended) offset for the \"data offset indirect\" addressing mode. The JR latch is used to hold the (sign extended) offset for the \"program relative\" addressing mode. The C0 and C1 FIFO (first in first out) holds the opcode. The RD0 to RD3 latches hold the 8, 16 or 32 bit input parameter. The WD0 to WD3 latches hold the 8, 16 or 32 bit output parameter. The AD latch holds the address for a memory read or write operation. Part of the ALUs are the N (negative), Z (zero), C (carry) and V (overflow) flags.\n\nThis CPU wants to be boring. The CPU got a heavy influence from the Motorola 68000. In one point this CPU is special: Every register can only handle two data sizes, called \"half data size\" and \"full data size\". The Motorola 68000 and the Intel 80386 registers can handle three data sizes, 8 bit, 16 bit and 32 bit. The CRISC CPU tries to handle the detail of different data sizes and specially the detail of sign extent and zero extent smarter then the older CPUs.\n\n\n \n\n\n \n \n \n\n===== \n Top level Description =====\n\nCRISC CPU Instruction set\n\n\n\nName\n\nClass\n\nC\n\nPurpose\n\n\n\nRET\n\ncontrol\n\nreturn; \n\nreturn from subroutine\n\n\n\nNOT\n\nlogic\n\nR0 = ~R0\n\ninvert bits, 1-complement\n\n\n\nNEG\n\narithmetric\nR0 = -R0\n\nchange sign, 2-complement\n\n\n\nASR\n\nshift\n\nR0 >>= 1 or R0 >>=\n8\n\narithmetric shift right, keep\nsign\n\n\n\nLSR\n\nshift\n\nR0 >>= 1 or R0 >>=\n8\nlogic shift right, fill with zero\n\n\n\nASL, LSL\n\nshift\n\nR0 \n\nshift left, fill with zero\n\n\n\nTST\n\narithmetric\n\nN,Z = f(R0)\n\nset N and Z flags depending on\nregister contents\n\n\n\nINC\n\narithmetric\n\n++R0\n\nincrement register content\n\n\n\nDEC\n\narithmetric\n\n--R0\n\ndecrement register content \n\n\nAND\n\nlogic\n\nR0 &= R1\n\nlogical AND\n\n\n\nOR\n\nlogic\n\nR0 |= R1\n\nlogical OR\n\n\n\nXOR\n\nlogic\n\nR0 ^= R1\n\nlogical EXCLUSIVE OR\n\n\n\nADD\n\narithmetric\n\nR0 += R1\n\nadd contents of R1 zu contents\nof R0\n\n\n\nSUB\n\narithmetric\nR0 -= R1\n\nsubtract contents of R1 from\ncontents of R0\n\n\n\nCMP\n\narithmetric\n\nN,C,V,Z = f(R0 - R1)\n\nlike SUB but only sets flags\n\n\n\nJMP\n\ncontrol\n\ngoto X;\n\nunconditional jump\n\n\n\nJcc\n\ncontrol\n\nif (), while(), for()\n\nconditional jump\n\n\n\nScc\n\ncontrol\n\nR0 = f(N,C,V,Z)\n\nload R0 with -1 or 0, depending\nof condition code cc\n\n\n\nJSR\n\ncontrol\n\nfunc();\n\njump subroutine\n\n\n\nLD\n\ntransport\n\n\n\ncopy memory to register or\nregister to memory with optional sign extend\n\n\n\n\n\n\nCRISC CPU Addressing mode\n\n\n\n\naddressing mode\n\nC\n\nAssembler\n\nDescription\n\n\n\nImplied\n\nreturn;\n\nRET\n\nreturn from subroutine\n\n\n\nImmediate\nr0 = 0xAFFE;\nLDW R0,#$AFFE\n\nload register with constant\n\n\n\nRegister direct\n\nr0 = r1;\n\nLDW R0,R1\n\nload register with contents of\nanother register\n\n\n\nProgram direct\n\nfunc();\n\nJSR func\n\ncall sub routine\n\n\n\nProgram relative\n\ngoto near;\n\nJMP near\n\njump\n\n\n\nProgram indirect\n\n(*a0)();\n\nJSR (A0)\n\ncall sub routine, address is in\nregister\n\n\n\nData direct\nr0 = variable;\nLDW R0,variable\n\nload register with contents of\nmemory element \n\n\nData indirect\n\nr0 = *a0;\n\nLDW R0,(A0)\n\nload register with the contents\nof the memory element that is addressed by register A0\n\n\n\nData predecrement indirect\nr0 = *--a0;\n\nLDW R0,-(A0)\n\ndecrement register A0 by the\nsize of the memory element. Load register R0 with the contents of the\nmemory element that is addressed by register A0\n\n\n\nData postincrement indirect\nr0 = *a0++;\n\nLDW R0,(A0)+\n\nload register R0 with the\ncontents of the memory cell that is addressed by register A0. Increment\nregister A0 by the size of the memory element.\n\n\nData offset indirect\nr0 = a0->offset;\n\nLDW R0,offset(A0)\n\nload register R0 with the\ncontents of the memory element that is addressed by register A0 plus\noffset. Offset is a constant.\n\n\n\n\n\n\nCRISC CPU Instruction format\n\n1 Byte Instruction Control (ret,\n...)\n\xC2\xA07 6 5 4 3 2 1 0\n+-----+---------+\n|0 0 0| Opcode\xC2\xA0 |\n+-----+---------+\n\n2 Byte Instruction Control\n(scc, ...)\n\xC2\xA07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0\n+-----+-+-------+-----------+---+\n|1 0 0|1|\xC2\xA0 CC\xC2\xA0\xC2\xA0 |0 0 0 0 0 0|rg |\n+-----+-+-------+-----------+---+\n\n2 Byte Instruction\nJump/Call Program relative\n\xC2\xA07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0\n+-----+-+-------+---------------+\n|0 0 1|S|\xC2\xA0 CC\xC2\xA0\xC2\xA0 | 8 Bit constant|\n+-----+-+-------+---------------+\n\n3 Byte Instruction Jump/Call Program direct, Program indirect\n\xC2\xA07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0\n+-----+-+-------+-------------------------------+\n|0 1 0|S|\xC2\xA0 CC\xC2\xA0\xC2\xA0 |\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0 16\nBit constant\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0 |\n+-----+-+-------+-------------------------------+\n\n2 Byte Instruction ALU (and, add, shift, inc, dec, ...)\n\xC2\xA07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0\n+-----+-+-------+---+---+---+---+\n|0 1 1|L|\xC2\xA0 ALU\xC2\xA0 |al2|rg2|al1|rg1|\n+-----+-+-------+---+---+---+---+\n\n2 Byte Instruction Load/Store\n\xC2\xA07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0\n+-----+-+---+---+-+---+-----+---+\n|1 0 0|0|sl1|rg1|d|ext| sl2 |rg2|\n+-----+-+---+---+-+---+-----+---+\n\n3 Byte Instruction Load/Store\n\xC2\xA07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0\n+-----+-+---+---+-+---+-----+---+---------------+\n|1 0 1|0|sl1|rg1|d|ext| sl2 |rg2| 8 Bit constant|\n+-----+-+---+---+-+---+-----+---+---------------+\n\n4 Byte Instruction Load/Store\n\xC2\xA07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0\n+-----+-+---+---+-+---+-----+---+-------------------------------+\n|1 1 0|0|sl1|rg1|d|ext| sl2 |rg2|\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\n16 Bit constant\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0 |\n+-----+-+---+---+-+---+-----+---+-------------------------------+\n\n6 Byte Instruction Load/Store\n\xC2\xA07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7\n6 5 4 3 2 1 0 7 6 5 4 3 2 1 0\n+-----+-+---+---+-+---+-----+---+---------------------------------------------------------------+\n|1 1 1|0|sl1|rg1|0|0 0| sl2\n|rg2|\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\n32\nBit\nconstant\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\n|\n+-----+-+---+---+-+---+-----+---+---------------------------------------------------------------+\n\n\n\nThe CRISC CPU has 16 Bit data bus, 16 Bit address bus. In the CPU there are six buses with 16 Bit each. Three Arithmetric Logic Units are available. The CPU does not have much of a pipeline.\nIn the description I talk about a single clock. In real implementation maybe a two-phase non-overlapping clock (NORA) is used.\nDue to the byte-addressing/word data bus nature of the CPU, a data item (instruction, parameter) can be aligned or not. An data item is aligned if at instruction fetch A0 bit of A latch is zero. If aligned, a 8 Bit data item is on the lower 8 Bit of the databus, a 16 Bit data item uses the full databus. If not aligned a 8 Bit data item is on the higher 8 Bit of the databus, the lower 8 Bit of a 16 Bit data item is on the higher 8 Bit of the databus and the higher 8 Bit of a 16 Bit data item is on the lower 8 Bit of the databus of the next memory fetch. A 8 Bit data item and an aligned 16 bit data item needs 1 memory fetch. An aligned 32bit data item or a non-aligned 16 bit data item needs 2 memory fetches. A non-aligned 32bit data item needs 3 memory fetches.\n\nThe short hand notations for the CPU behaviour are:\non(X, Y) latch X activates tristate output Y.\noff(X, Y) latch X de-activates tristate output Y.\nforward(X) set level triggered latch X to forward data.\nhold(X) set level triggered latch X to hold data.\n\nThe typical fetch/decode/execute/write back cycles are:\nCPU cycle T0 (opcode fetch, 8 bit):\n High-phase:\n Addr ALU: op = *PC++: on(PC latch, right Addr-bus), on(+1 latch, left Addr-bus), forward(ALU latches), ALU = +\n Addressbus: ADDR = PC: forward(A latch)\n Low-phase:\n Addr ALU: op = *PC++: hold(ALU latches), forward(PC latch), off(PC latch, right Addr-bus), off(+1 latch, left Addr-bus)\n Addressbus: out(PC): hold(A latch)\n Databus: op = DATA: forward(Opcode FIFO)\n\nCPU cycle T1 (decode):\n High-phase:\n Databus: op = DATA: hold(Opcode FIFO)\n Sequenzer: set up state machine initial state\n Low-phase:\n\nCPU cycle T2 (execute, 16 bit, data):\n High-phase:\n Data ALU: R0 += R1: on(R0 latch, left Low-bus), on(R1 latch, right Low-bus), forward(ALU latches), ALU = +\n Low-phase:\n Data ALU: R0 += R1: hold(ALU latches), forward(R0 latch), off(R0 latch, left Low-bus), off(R1 latch, right Low-bus)\n\nCPU cycle T3 (write back, 16 bit, aligned):\n High-phase:\n Addr ALU: mem[A0] = R0: on(A0 latch, right Addr-bus)\n Addressbus: ADDR = A0: forward(A latch)\n Data ALU: mem[A0] = R0: on(R0 latch, left Low-bus)\n Databus: DATA = R0: forward(WB LH latch), forward(WB LL latch), on(WB H TS), on(WB L TS)\n Low-phase:\n Addr ALU: mem[A0] = R0: off(A0 latch, right Addr-bus)\n Addressbus: ADDR = A0: hold(A latch)\n Data ALU: mem[A0] = R0: off(R0 latch, left Low-bus)\n Databus: DATA = R0: hold(WB LH latch), hold(WB LL latch), on(WB H TS), on(WB L TS)\n High-Phase:\n Databus: off(WB H TS), off(WB L TS)\n \n... to be continued" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - AndreAdrian name: crisc_cpu status: Empty updated: Mar 3, 2011 wishbone-compliant: 0 - category: Testing / Verification created: Jul 3, 2012 description: '' language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - yursh name: crtg status: Planning svn-updated: Aug 14, 2012 updated: Aug 14, 2012 wishbone-compliant: 0 - category: Crypto core created: Mar 24, 2009 description: "===== \n Description =====\n\nThe Cryptographic Algorithm which is most widely used throughout the world \nfor protecting information. Cryptography is the art of secret writing, \nfollowed by the guarantee to authenticate data and messages and protect \nthe systems from valid attacks .It comprises of encryption and decryption \noperations each associated with a key which is supposed to be kept secret . \n \n We have implement RC6 Algorithm. Which is considered as a secured and \nelegant choice for AES due to its simplicity, security, performance and \nefficiency. RC6 supports 32 bit and 64 bit processing. An eight step \noperation is used to encipher the 64 bit plain text block. The encrypted \ndata is then decrypted by performing the reverse operations on the same. \nThe hardware implementation of RC6 algorithm is done using VHDL \nHardware Description Language. For this implementation Xilinx foundation \nseries 9.2i software and Spartan-3s400pq208-5 kit are being used." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - deepaksamant name: cryptography status: FPGA proven svn-updated: Apr 27, 2009 updated: May 23, 2011 wishbone-compliant: 0 - category: Crypto core created: Feb 16, 2007 description: "===== \n Crypto-PAn =====\n\nA hardware implementation of Crypto-PAn[1]. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the underlying pseudorandom function, supports online key changes, and is capable of line rates exceeding gigabit ethernet.\n\n[1] Blake, A. and Nelson, R. 2008. Scalable Architecture for Prefix Preserving Anonymization of IP Addresses. In Proceedings of the 8th international Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (Samos, Greece, July 21 - 24, 2008). M. Berekovi\xC4\x87, N. Dimopoulos, and S. Wong, Eds. Lecture Notes In Computer Science, vol. 5114. Springer-Verlag, Berlin, Heidelberg, 33-42. DOI= http://dx.doi.org/10.1007/978-3-540-70550-5_5 \n\n \n\n\n \n \n \n\n===== \n Features =====\n\nCrypto-PAn features:\n- One to one mapping from original IP address to anonymized IP address\n- Prefixes are preserved. That is, if two original IP addresses sharea a k-bit prefix, their anonymized mapping also share a k-bit prefix. \n- Consistency is maintained across traces. That is, the same IP address in differant traces is mapped to the same anonymized IP address, if the secret key used is the same. \n\nCore features:\n- Fully pipelined \n- AES(Rijndael) engine capable of 32Gbit/s throughput on Virtex-4.\n- Supports online secret key changes.\n- Compatiable with Jinliang Fan's C+++ reference implementation. That is, using the same secret keys, IP addresses will map to the same anonymous IP addresses.\n- Capable of anonymizing traces at line rates above gigabit ethernet.\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nVerified in hardware on XCV4FX60 FPGA." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - tonyb33 name: cryptopan_core status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 26, 2010 wishbone-compliant: 0 - category: Crypto core created: Jun 28, 2008 description: "===== \n Description =====\n\nThis IP core loads an unsorted, encrypted list of numbers from memory. It then decrypts and sorts the list. \n\nSorting is acheived using a high-throughput, heavily parametric mergesort core. \n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Highly parametric mergsort core\n - folds a single comparator across multiple fifos mapped onto SRAMs\n - compartor scheduler as a parameter\n- High speed PLB master core\n - achieves effective memory throughput of more than 400MB/s\n - uses configurable burst transfers to obtain high throughput\n- Pipelined AES core\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis project is completed and development is closed. It has been successfully implemented on FPGA." language: Other license: MIT licenselink: http://opensource.org/licenses/MIT maintainers: - mcn02 - kfleming - mirv123 name: cryptosorter status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Crypto core created: Aug 31, 2007 description: "===== \n csa =====\n\nthis project implement a dvb common Scrambling Algorithm\n \n\n\n \n \n \n\n===== \n Features =====\n\n-decrypt\n - only decrypt yet\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- status1\n- status2" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - simon111 name: csa status: Design done svn-updated: Apr 20, 2010 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Jun 1, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: unknown maintainers: - zhaofei name: daq_v10 status: Empty updated: Jun 1, 2011 wishbone-compliant: 0 - category: Other created: Jun 15, 2012 description: "===== \n Description =====\n\nThis is a date/time keeping core. It uses an external 100,60 or 50 Hz time-of-day signal to update a group of BCD counters which record the date and time. The date and time is presented as a 16 digit BCD format YYYYMMDDHHMMSSJJ which fits into a 64-bit word.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- optional 50,60, or 100 Hz time-keeping\n- 64 bit bus interface\n- internally decoded to respond in address range $DC0400-$DC0418\n- Mars timekeeping option (millennium style calendar)\n- leap year tracking\n- independent system bus and time-of-day clocks\n- alarm setting" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: datetime status: Planning svn-updated: Jun 17, 2012 updated: Jun 17, 2012 wishbone-compliant: 0 - category: Other created: Sep 25, 2001 description: "===== \n Description =====\n\nDebug Interface is used for development purposes (debugging). It is an interface between the CPU(s), peripheral cores and any commercial debugger/emulator. The external debugger or BS tester connects to the core via JTAG port that is fully IEEE 1149.1 compatible. For that reason jtag TAP needs to be used together with this core.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- New version tested with a test bench and in real HW. (April 8, 2004)\n- Old debug (development) was separated into two different projects. Debug interface is rewritten, documentation updated. Use rel_22 tag for downloading. [January 27, 2004]\n- All files were updated [February 4, 2002] \n- Development Interface was thoroughly tested (functional simulation and in real hardware).\n- GDB debugger was connected to the Development Interface.\n- Boundary Scan is supported. BS chain of the chip where Debug Interface is used, must be defined prior to its use. \n- Specification is finished: DbgSupp.pdf (about 200 KB) (see Downloads).\n- Datasheet is ready: Debug Support Datasheet (prl.).pdf (see Downloads).\n \n\n\n \n \n \n\n===== \n Change log =====\n\n- 08/04/2004 IM New version. Use rel_25 tag for downloading. Documentation updated.\n- 17/01/2004 IM New version. Use rel_22 tag for downloading. Documentation updated.\n- 12/02/2002 IM Datasheet written.\n- 04/02/2002 IM Documentation and code updated (small fixes to make the core smaller, faster and of course more stable). \n- 04/12/2001 IM Documentation and code updated (small fixes, wishbone master interface added) \n- 20/9/2001 IM Documentation and code updated (final release) \n- 13/9/2001 IM Documentation and code updated \n- 23/5/2001 IM Documentation updated \n- 8/5/2001 IM Initial web page + first check-in \n \n\n\n \n \n \n\n===== =====\n\nFeel free to send me comments, suggestions and bug reports." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - igorm name: dbg_interface status: Stable svn-updated: Mar 10, 2009 updated: Aug 5, 2011 wishbone-compliant: 1 - category: DSP core created: Feb 21, 2015 description: "===== \n Description =====\n\nThe goal of this project is to create an IP core for an FFT that runs, in a pipelined fashion, at two samples per clock. A small C++ program will generate the Verilog files, allowing the FFT to be of an arbitrary length--subject only to the capability of the FPGA used to implement the FFT. \n\nOne of my goals is to create an FFT core that can be used with open source and third party Verilog simulation facilities, such as Verilator. This would be difficult with a proprietary IP core." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - dgisselq name: dblclockfft status: Design done svn-updated: Apr 13, 2015 updated: Mar 13, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Sep 25, 2001 description: "===== \n Description =====\n\nRecent advances in communications and networking technologies have made it possible that many applications use digital videos such as teleconferencing and multimedia communications. These applications require a very large bit-rate if being handled without compression. Most video compression standards such as HDTV, H.261, JPEG and MPEG use Discrete Cosine Transform (DCT) as a standard transform-coding scheme.\n\nDiscrete Cosine Transform is decomposing the signal into weighted sums of cosine harmonics; unlike DCT, Discrete Fourier Transform decomposes the signal into weighted sums of orthogonal sines and cosines that when added together reproduce the original signal.\n\nFreeDCT-L is a low power architecture 1-Dimensional 8-point DCT/IDCT core that occupies minimal area for systems that do not require high-speed operation (e.g. Still Image Compression in digital cameras, Audio compression applications). The core\xE2\x80\x99s operating resolution can be easily controlled. The main goal of designing the core was to minimize the size and power consumption. It uses about 3000 gates when implemented on FPGAs. After implementing the design using Alliance Series software for Xilinx XC4000E FPGA family, timing simulation results showed that the core can operate at a speed of 29 MHz. When implementing the design on ASIC 0.8-micron technology, timing simulation showed that the core will operate at a maximum frequency of 51 MHz. The core occupied an area of 1.1 mm2 and contains 11,162 transistors.\n\nFreeDCT-M is a moderate speed 1-Dimensional IDCT core. It processes 12-bit words at a rate of 1 bit per clock cycle. The core will be suitable for MPEG decoding/encoding at the MP@ML ( Main Profile / Main Level). The VHDL core associated with detailed explanation and documentation will be released later.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nBoth cores associated with documentation are packed here in a ZIP file, please feel free to send your opinions or suggestions regarding my work" language: VHDL license: unknown maintainers: - tsherif name: dct status: Beta svn-updated: Mar 10, 2009 updated: Jul 26, 2013 wishbone-compliant: 0 - category: DSP core created: Feb 1, 2010 description: "===== \n Description =====\n\nDCT soft core is the unit to perform the Discrete Cosine Transform (DCT). It performs twodimensional 8 by 8 point DCT for the period of 64 clock cycles in pipelined mode.\n\n\nMain Features:\n\n\nmore than 300 MHz sampling frequency, 64-cycle calculation period,\napproximately 330 CLBs and 4 DSP48E in Virtex-5 device,\n2 DSP48E when the scaled output data mode is used,\n8-bit input data,\n11-bit coefficients,\n12 \xE2\x80\x93 bit results,\npipelined mode,\nlatent delay from input to output is 132 clock cycles,\nstructure optimized for Xilinx Virtex, Spartan FPGA devices.\n\n\nPlease, contact us if you wish to have this IP core modified or adjusted to meet your requirements.\n\n\nThis core is provided by Unicore Systems http://unicore.co.ua. To view our product list of commercial IP cores, please, follow this link" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unicore - aser name: dct_idct status: Stable svn-updated: Feb 2, 2010 updated: Oct 10, 2012 wishbone-compliant: 0 - category: Memory core created: Aug 20, 2011 description: "===== \n Description =====\n\nThis project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board\n \n\n\n \n \n \n\n===== \n Moduls =====\n\n\n \n\n\n \n \n \n\n===== \n Function =====\n\nAfter a Power on :\n==================\n\n1. Init-Sequenz for the RAM\n2. Automaic Write-Sequenz (writes 16 Datawords each 64Bit to the RAM)\n3. Automatic Read-Sequenz (reads the first Dataword from the RAM)\n4. Display the Dataword at the 8Bit LEDs\n\n\nSwitch-0 :\n==========\n\n> SW0 is used as a Reset-Switch\n\n\nSwitch-1 to 3 :\n===============\n\n> SW1 to SW3 selects witch part of the Dataword\n is shown at the LEDs\n\n\nButton north :\n==============\n\n> increments the Adresspointer\n\n\nButton south :\n==============\n\n> decrements the Adresspointer\n\n\nButton east :\n=============\n\n> reads a single Dataword (64Bit) from the actual adress\n\n\nButton west :\n=============\n\n> writes a fixed Dataword (64Bit) to the actual adress\n\n\nStatus LED :\n============\n\n> LED is permanent blinking\n \n\n\n \n \n \n\n===== \n Project Options =====\n\nPlattform : XILINX Spartan-3A\nFPGA : XC3S700A-FGG484\nLanguage : VHDL\nISE :\t\tISE-Design-Suite V:13.1\nIP-Core :\tMIG V:3.6.1\nDDR2-SDRAM :\tMT47H32M16 (64 MByte)\n \n\n\n \n \n \n\n===== \n Limitation =====\n\nBurst Length = 4\nData Width = 16 Bit\n\n> with these settings each Data access reads (and writes)\n a 64Bit Dataword (4 x 16 Bit)\n \n\n\n \n \n \n\n===== \n Read/Write speed =====\n\nRead :\n======\n\n> to Read one Dataword (64Bit)\n 22 Clockzycles are needed\n\nWrite :\n=======\n\n> to Write one Dataword (64Bit)\n 25 Clockcycles are needed\n \n\n\n \n \n \n\n===== \n Status =====\n\n20.08.2011 : Version 7.0 : Project start" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - john_fpga name: ddr2_sdram status: Stable svn-updated: Jun 3, 2012 updated: Jun 3, 2012 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/ddr3_sdram-r3.tar.gz category: Memory core created: Oct 24, 2012 description: "===== \n Downloading =====\n\nThe project files are checked in to SVN, available here:\nSVN files\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis is a controller core for DDR3 SDRAM.\n\nDefault configuration supports one 64 bit UDIMM or SO-DIMM\nSupports DIMM sizes of 1GB, 2GB, 4GB and 8GB\nWorks at the minimum DDR3 transfer rate of 600 MT/s\nHeavily optimised for Xilinx Spartan 6 FPGA family\nImplemented in less than 1300 lines of Verilog\nSupports BC4 (Burst chop 4) read and write commands and the refresh command\nReliable operation verified with XC6SLX25 and XC6SLX75 FPGAs in -2 and -3 speed grades\n\n\nDDR3 controller working in a Spartan XC6SLX25-2i with a 2GB Corsair UDIMM:\n\n\n\n\n \n\n\n \n \n \n\n===== \n Testbench =====\n\nThe testbench consists of a MicroBlaze MCS microcontroller with one module of glue logic to adapt it to the DRAM controller.\nThe glue logic module multiplexes the 256 bit data busses of the DRAM controller down to the 32 bit data busses of the MicroBlaze MCS.\nThe MB MCS only has 1GB of address space available in its IO port interface and the DRAM controller supports DIMMS of up to 8GB. The glue logic accounts for this by using a GPIO port from the MB MCS to provide the high order address bits, allowing SW running on the MB MCS to use a bank switching scheme to fully access DIMMS larger than 1GB." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eschabor name: ddr3_sdram status: FPGA proven updated: Mar 28, 2014 wishbone-compliant: 0 - category: Memory core created: Nov 30, 2011 description: "===== \n Description =====\n\nThis is a fully synthesizable DDR3 Memory BFM. Implemented using Verilog 2001 without any vendor specific IP Block. As such, the BFM is not able to run a very high speed. Test shown that is is able to respond to WRITE and READ instruction at 10MHz. \n \n\n\n \n \n \n\n===== \n Status =====\n\nMemory BFM has been tested and passes all Micron DDR3 testbench. It is also has been tested and able to passes Altera DDR3 Testbench.Has been synthesized using Xilinx ISE 13.2 and Quartus II Version 11.1 Build 173" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - slai name: ddr3_synthesizable_bfm status: Design done svn-updated: Dec 4, 2011 updated: Dec 3, 2011 wishbone-compliant: 0 - category: Memory core created: Dec 20, 2002 description: "===== \n Description =====\n\nThe ddr_sdr controls read and write access of a programmable \nlogic device to a single 256 Mbit memory device. The 32-bit \nwide user interface basically accepts two commands, read or \nwrite. The control logic initializes the memory after reset \nand issues refresh commands from time to time to ensure data \nintegrity. The data width to the memory device is 16 bits \nwide and performs a double data rate operation at 100 MHz \nclock rate.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Version 1.0 available" language: VHDL license: custom licensetext: "\r\n\r\n OpenIPCore Hardware General Public License \"OHGPL\" \r\n Draft Version 0.20-15092000 September 2000\r\n\r\n Copyright (C) 2000 OpenIPCore Organization.\r\n\r\n\r\nEveryone is permitted to copy and distribute and modify this document\r\nunder the terms of the GNU Free Documentation License.\r\n\r\nPreamble\r\n========\r\n\r\nThe preamble is part of the license and the license and its preamble\r\ncan not be split out.\r\n\r\nDefinitions:\r\n\r\nSYSTEM\r\n Is any thing that works or supposed to work to do some \r\n operations depending on some specific inputs and produce \r\n some results. \r\n\r\nHARDWARE DESIGN: \r\n (The terms HARDWARE DESIGN and DESIGN can be used \r\n interchangeably in the license) \r\n \r\n Is any work that defines, describes or simulates a system or \r\n part of a system that could be physically implemented. This \r\n includes but not limited to, system architectures, design \r\n ideas, design description, micro-codes or hardware \r\n instructions. \r\n\r\nHARDWARE DESIGN DESCRIPTION: \r\n (The terms HARDWARE DESIGN DESCRIPTION and DESIGN \r\n DESCRIPTION can be used interchangeably in the license) \r\n \r\n Is any form of documentation or supporting materials that \r\n defines and identifies the Hardware design, how it can be \r\n implemented and/or tested. This includes but not limited to, \r\n HDL codes, schematics, net-lists, PCB layouts, chip and \r\n silicon cell layout, timing diagrams, truth tables, flow \r\n charts, state diagrams, block diagrams or written (digitally \r\n or physically) documentation. \r\n\r\nHardware design files/ CAD files: \r\n Are set of files that are used to describe \r\n the hardware design, its implementation or testing or some \r\n parts of it. \r\n\r\nFabrication files: \r\n Are set of files that are used to physically implement \r\n the design or part of it. \r\n\r\nCOPYING A HARDWARE DESIGN DESCRIPTION: \r\n Is the act of duplicating the design \r\n description or CAD files in anyway. \r\n\r\nDISTRIBUTION OF A HARDWARE DESIGN: \r\n Is the act of publishing and making the design description \r\n available for more activities or people.\r\n\r\nMODIFICATION OF A DESIGN: \r\n Is the act of reproducing the design in order to alter \r\n (not necessarily to succeed to improve) the design itself \r\n or the description of the design. \r\n\r\nIMPLEMENTATION OF A DESIGN: \r\n Is the act of producing/reproducing the hardware design or \r\n part of it to get the physical or part of the physical system. \r\n\r\nThe Derivative work \r\n means any changes, improvements or porting the original work \r\n to other environments or platforms (e.g. different hardware \r\n target, different PLD....). This may vary depending on the \r\n type of the hardware design itself. \r\n\r\nThe based work \r\n is the act of using the design AS IS without any modification \r\n as a building block or module of other design. (e.g. like using \r\n the design as a daughter board for a large system, or using the \r\n HDL code in SoC core). \r\n\r\n\r\n\r\nOpenIPCore/OpenCores License terms.\r\n===================================\r\n\r\nTERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION \r\n\r\n1. This license applies to hardware designs, hardware design \r\n description, CAD or Fabrication files or any other work which \r\n contains a notice placed by the copyright holder saying it may \r\n be distributed under the terms of this License. \r\n\r\n2. You may copy, distribute and/or implement this Hardware Design \r\n or any portion of it as is. Any time you copy or distribute this \r\n design you have to provide all of the source files and \r\n documentations that came with the original work or put them in \r\n a public place that anyone can reach without any kind of \r\n restrictions. \r\n\r\n3. You can not sell the design description, design files or \r\n fabrication files but you may charge fee for the physical act \r\n of transferring a copy \r\n\r\n4. You can implement the design and charge fees for the physical \r\n hardware and you have to provide notice for the public about \r\n the source of the design description. \r\n\r\n5. Any modification of this hardware design or any derivative work \r\n from it should be documented by providing list of changes, reasons \r\n behind the changes and the date of change. \r\n\r\n6. You are allowed to use the design or design files on any work \r\n based on the hardware design. \r\n\r\n7. You may not copy, modify, sublicense, or distribute the design/design \r\n description or files except as expressly provided under this License. \r\n Any attempt otherwise to copy, modify, sublicense or distribute the \r\n design/design description or files is void, and will automatically \r\n terminate your rights under this License. However, parties who have \r\n received copies, or rights, from you under this License will not \r\n have their licenses terminated so long as such parties remain in \r\n full compliance. \r\n\r\n8. Each time you redistribute the design description or files, \r\n the recipient automatically receives a license from the original \r\n licensor to copy, distribute or modify the Program subject to \r\n these terms and conditions. You may not impose any further \r\n restrictions on the recipients' exercise of the rights granted \r\n herein. \r\n\r\n9. You are not required to accept this License, since you have \r\n not signed it. However, nothing else grants you permission \r\n to modify or distribute the hardware design or its derivative \r\n works. These actions are prohibited by law if you do not \r\n accept this License. Therefore, by modifying, distributing\r\n or implementing the hardware design (or any work based on the \r\n hardware design), you indicate your acceptance of this License \r\n to do so, and all its terms and conditions for copying, \r\n distributing or modifying the hardware design or works based \r\n on it. \r\n\r\n10. NO WARRANTY of any kind is provided on the functionality, \r\n performance or risks cased by using this Hardware Design. \r\n\r\n\r\nNO WARRANTY\r\n===========\r\n\r\n11.a. BECAUSE THE HARDWARE DESIGN IS LICENSED FREE OF CHARGE, \r\nTHERE IS NO WARRANTY FOR IT, TO THE EXTENT PERMITTED BY APPLICABLE \r\nLAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS \r\nAND/OR OTHER PARTIES PROVIDE THE HARDWARE DESIGN IMPLEMENTATION \r\n\"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, \r\nINCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE \r\nRISK AS TO THE QUALITY AND PERFORMANCE OF THE HARDWARE DESIGN IS\r\nWITH YOU. SHOULD THE DESIGN PROVE DEFECTIVE, YOU ASSUME THE COST \r\nOF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. \r\n\r\n11.b. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO \r\nIN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY \r\nMODIFY AND/OR REDISTRIBUTE THE HARDWARE DESIGN AS PERMITTED ABOVE, \r\nBE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, \r\nINCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR \r\nINABILITY TO USE THE HARDWARE DESIGN (INCLUDING BUT NOT LIMITED \r\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES \r\nSUSTAINED BY YOU OR THIRD PARTIES OR ANY OTHER KIND OF LOSSES \r\nOR A FAILURE OF THE HARDWARE DESIGN IMPLEMENTATION TO OPERATE \r\nWITH ANY OTHER SYSTEMS), EVEN IF SUCH HOLDER OR OTHER PARTY \r\nHAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. \r\n\r\n11.c IN CASE OF THE PHYSICAL IMPLEMINTATION, THE IMPLIMENTER CAN \r\nPROVIDE WARRANTIES ON THE PHYSICAL HARDWARE AND CHARGE FOR FEES \r\nFOR SUCH WARRANTIES. \r\n\r\n\r\n" maintainers: - markus name: ddr_sdr status: Stable svn-updated: Mar 10, 2009 updated: Apr 30, 2013 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/dds_signal_generator.zip category: Other created: Feb 1, 2012 description: "===== \n Description =====\n\nDirect Digital Synthesis Signal Generator in VHDL tested and implemented in FPGA (Altera Cyclone 2).\n \n\n\n \n \n \n\n===== \n Source code =====\n\nI uploaded the source code files in Downloads section. \nThe source code file is \"DDS Sourcecode.zip(rename)\".\nPlease rename the file form .odt to .zip. (Sorry. I do not know how to use SVN. That's why i uploaded like this).\nIf you want all the source code files accompanying my other work related to this project, download \"Source code(other files) (rename\" and rename to .zip.\nUpdate:\n-------\nI also uploaded the source code in doc format. Download, Open & copy to VHDL file." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lxkarthi name: dds_signal_generator status: Empty updated: Feb 4, 2012 wishbone-compliant: 0 - category: DSP core created: Dec 22, 2008 description: "===== \n Description =====\n\nThe DDS IP core (dds_synthesizer) is a implementation of a direct digital frequency synthesizer (DDS) (also called number controlled oscillator, NCO) which produces a sinewave at the output with a specified frequency and phase (adjustable at runtime).\n\nOnly one quater of the sinewave is stored in the LUT, the rest is computed by simple operations (negating, subtraction), resulting in a reduced memory requirement.\n\nThe resolution of the frequency tuning word (FTW), the phase and the amplitude defined seperately. Several precomputed look-up tables are provided as combinations from 8 to 16 bit phase and amplitude resolution. The frequency resolution can is defined as generic. A matlab script for generating the LUTs for different resolutions is included.\n\nThe design is fully pipelined for maximum throughput. \n\n\n\n\n\n\n\nIf you find something interesting, feel free to contact me: pluto[at]ls68.de" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - plutonium name: dds_synthesizer status: FPGA proven svn-updated: Apr 5, 2013 updated: Apr 3, 2013 wishbone-compliant: 0 - category: Prototype board created: Nov 18, 2009 description: "===== \n Description =====\n\nThis project uses two off the shelf boards and interfaces them. The processor board used is a Olimex LPC-L2294 and the FPGA board is a Terasic DE1. A Olimex ARM-USB-OCD was used to load and debug the code. The boards were cabled together with floppy and hard drive cables. The entire setup cost less than $350. \n\nThe bridge from the wb_async_mem_bridge project is used to interface the External Memory Controller to the Wishbone bus on the FPGA. Currently the SRAM, GPIOs & HEX LED display is connected and there are plans to add the other interfaces on the DE1 as time permits. \n\nEcos has been ported and there are some simple examples of multithreading and interrupts. The shell interface was borrowed from redboot has been striped down and adapted to run in it's own thread. \n\n\nhttp://www.olimex.com/dev/lpc-l2294.html\nhttp://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=83\nhttp://www.olimex.com/dev/arm-usb-ocd.html" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qaztronic name: de1_olpcl2294_system status: Alpha svn-updated: Mar 29, 2011 updated: Apr 6, 2010 wishbone-compliant: 1 - category: Other created: Aug 10, 2011 description: "===== \n Development Status =====\n\nThe core is tested and is being used in FPGA hardware in several projects.\n\n\nThe scope screen below shows 7 switches being debounced with 50us of debounce time. See in the photo at right the 1 clock cycle STRB pulse right after the output register loading. The system clock in the example is 100MHz.\n\n\n\n \n \n \n\n\n \n\n\n \n \n \n\n===== \n Related Links =====\n\nThis core is being used in the SPI_MASTER_SLAVE verification test circuit: http://opencores.org/project,spi_master_slave\nTo get the latest version: http://opencores.org/download,debouncer_vhdl\nIf you have issues you like to be addressed, place a request in the bugtracker: http://opencores.org/project,debouncer_vhdl,bugtracker\nIf you find this core useful, please let me know: jdoin@opencores.org\n\nIf you find the LGPL license to be unfit for your purposes, please let me know and we can study changing the license to another open-source hardware license.\n\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis block is a general-purpose multiple input de-bouncing circuit.\nIt handles multiple inputs, like mechanical switch inputs, and outputs a de-bounced, stable registered version of the inputs.\nA 'new_data' one-cycle strobe is also available, to sync downstream logic.\nCONCEPTUAL CIRCUIT\nThe model has the generics N (input bus width) and CNT_VAL (clock counts for the de-bounce period).\n\n W \n /----------------/----------------\\ \n | | \n | | \n | ______ ______ | _____ \n | W | | W |fdr | W | W |cmp \\ \n \\----/---| +1 |---/----| |--/--+----/----| \\ \n | | | | | \\ \n ------ | | \\ | \n | | | = |-----\\\n |> R | / | |\n ---+-- | / |\n | CNT_VAL---| / |\n | |____/ |\n | |\n \\------------\\ |\n | |\n N ____ | |\n /-------/---)) \\ ____ | |\n | ))XOR |-----) \\ | |\n | /------))___/ )OR |-----/ |\n | | /---)___/ |\n | | | |\n | | \\----------\\ |\n | | N | |\n | \\--------/-----------\\ +----------------------+---------\\\n | | | |\n \\---\\ | | |\n ______ | ______ | | ______ |\n | fd | | | fd | | | |fde | |\n[data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o]\n N | | N N | | N | | | | N | N |\n | | | | | \\---|CE | | |\n | | | | | | | | |\n[clk_i]----> |> | |> | | |> | | | ____ ______\n ------ ------ | ------ | N ____ \\---| \\ | fd |\n | \\---/---)) \\ |AND |-----| |----[strb_o]\n | ))XOR |-----|___/ | |\n \\-------------------------/---))___/ | |\n N | |\n |> |\n ------\n\nPIPELINE LOGIC\nThis de-bouncer circuit detects edges in an input signal, and waits the signal to stabilize for the designated time \nbefore transferring the stable signal to the registered output. \nA one-clock-cycle strobe is pulsed at the output to signalize a new data available.\nThe core clock should be the system high-speed clock, to optimize use of global clock resources, although a compromise \nmay be met by using a lower frequency clock and a smaller counter for the de-bounce period. Care should be taken not to\nuse a combinatorial clock, though, to avoid data setup time conflicts at the pipeline boundary.\nGROUP DE-BOUNCING\nA change in state in any bit in the input word causes reload of the delay counter, and the output word is updated only\nwhen all bits are stable for the specified period. Therefore, the grouping of signals and delay selection should match\nbehavior of the selected signals.\nRESOURCES USED\nGroup de-bouncing saves area by having only one counter that is shared by all grouped signals.\nThe number of registers inferred is: 3*N+(LOG(CNT_VAL)/LOG(2))+1 registers.\nThe number of LUTs inferred is roughly: ((4*N+2)/6)+3.\nSlice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r, \nbut for groups of 8 signals the LUT-FF usage will be optimal.\n\nThis circuit is fully synthesizable and is written in technology-independent VHDL.\nThe design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints, but contains no Xilinx-specific syntax or instantiated components.\n\nVerification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i.\nThe VHDL dialect used is VHDL'93, accepted largely by all synthesis tools." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jdoin name: debouncer_vhdl status: FPGA proven svn-updated: Sep 19, 2011 updated: Apr 20, 2013 wishbone-compliant: 0 - category: System on Chip created: Dec 16, 2003 description: "===== \n Description =====\n\nThis project is to implement an MP3 decoder in VHDL in terms of MPEG-1 layer3 standard. It is composed of all the components of MP3 decoding process. MP3 bitstreams can be fed into the input module of MP3 decoder and a decoded pcm output file will be produced when the MP3 decoding process is completed.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Code is written in VHDL\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Verified in simulation using Modelsim" language: VHDL license: unknown maintainers: - gshi - junzhao - duan - stian name: decoder status: Alpha svn-updated: Mar 10, 2009 updated: Sep 23, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Jan 9, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - arslanmajid name: dedicated_dsp_processor status: Empty updated: Jan 10, 2011 wishbone-compliant: 0 - category: Other created: Jun 14, 2005 description: "===== \n Description =====\n\nA VHDL implementation of the open DEFLATE data compression algorithm. The DEFLATE standard is specified in RFC 1951 and was jointly developed by Jean-loup Gailly and Mark Adler. More information about the DEFLATE algorithm is available on the zlib library home page www.zlib.org\n\nThe full text of the deflate specification and a brief explanation are available on :\nhttp://www.gzip.org/zlib/rfc-deflate.html\n\nAt the core the algorithm uses LZ77 compression, a veriy nice explanation for which is available on the zlib website and I have quoted below\n\nLZ77 compression\n\nLZ77 compression works by finding sequences of data that are repeated. The term ``sliding window'' is used; all it really means is that at any given point in the data, there is a record of what characters went before. A 32K sliding window means that the compressor (and decompressor) have a record of what the last 32768 (32 * 1024) characters were. When the next sequence of characters to be compressed is identical to one that can be found within the sliding window, the sequence of characters is replaced by two numbers: a distance, representing how far back into the window the sequence starts, and a length, representing the number of characters for which the sequence is identical.\n\nI realize this is a lot easier to see than to just be told. Let's look at some highly compressible data:\n\n Blah blah blah blah blah!\n\nOur datastream starts by receiving the following characters: `B,' `l,' `a,' `h,' ` ,' and `b.' However, look at the next five characters:\n\n vvvvv\n Blah blah blah blah blah!\n ^^^^^\n\nThere is an exact match for those five characters in the characters that have already gone into the datastream, and it starts exactly five characters behind the point where we are now. This being the case, we can output special characters to the stream that represent a number for length, and a number for distance.\n\nThe data so far:\n\n Blah blah b\n\nThe compressed form of the data so far:\n\n Blah b[D=5,L=5]\n\nThe compression can still be increased, though to take full advantage of it requires a bit of cleverness on the part of the compressor. Look at the two strings that we decided were identical. Compare the character that follows each of them. In both cases, it's `l' -- so we can make the length 6, and not just five. But if we continue checking, we find the next characters, and the next characters, and the next characters, are still identical -- even if the so-called ``previous'' string is overlapping the string we're trying to represent in the compressed data!\n\nIt turns out that the 18 characters that start at the second character are identical to the 18 characters that start at the seventh character. It's true that when we're decompressing, and read the length, distance pair that describes this relationship, we don't know what all those 18 characters will be yet -- but if we put in place the ones that we know, we will know more, which will allow us to put down more... or, knowing that any length-and-distance pair where length > distance is going to be repeating (distance) characters again and again, we can set up the decompressor to do just that.\n\nIt turns out our highly compressible data can be compressed down to just this:\n\n Blah b[D=5, L=18]!\n\nThen distance and length pairs have to be encoded into huffman codes that follow all the rules of classic huffman trees but with two extra rules\n\n1. In the variation used by the Deflate standard, there are two additional rules: elements that have shorter codes are placed to the left of those with longer codes. \n\n2. Among elements with codes of the same length, those that come first in the element set are placed to the left.\n\nA more detailed explanation is available at the website below:\n\nhttp://www.zlib.net/feldspar.html\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nFully compliant to the deflate compression specifications\n \n\n\n \n \n \n\n===== \n Status =====\n\n07/11/05\nDesign completed. \n\n28/3/06\nUsing the DJB2 hash algorithm, algorithm currently uses 112 slices and outputs a 32 hash key.\n\nNow working on search and match using the hash algorithm\n \n24/05/06\nImproved DJB2 algorithm implemented, some changes made to synchronisie the modules better, algorithm now uses only one slice and is implemented with a 4 byte buffer.\n\n29/05/06\nImplemented the LZ77 algorithm but haventuploaded it as it needs to be integrated with the huffman tree algorithm and that is still being coded." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - smallcode name: deflatecore status: Design done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Crypto core created: Sep 25, 2001 description: "===== \n Description =====\n\nSimple DES/Triple-DES core. \n \n\n\n \n \n \n\n===== \n Motivation =====\n\n- A simple DES core \n- Fast and Small Version \n- Open Source \n \n\n\n \n \n \n\n===== \n Compatibility =====\n\nI believe that the core complies to NIST-800-17. However, there has been no formal third party verification. \n\nThe official NIST specification can be downloaded here: 800-17.pdf.\n\nFor the Triple DES, the NIST reference is located here: FIP46-3.\n \n\n\n \n \n \n\n===== \n Performance =====\n\nTriple DES IP Core\n==============\n\n1) Area Optimized (CBC Mode)\nThis is a sequential implementation and needs 48 cycles to complete a full encryption/decryption cycle. \n- 0.18u UMC ASIC process: 5.5K gates, > 160 Mhz\n- Spartan IIe 100-6 : 1450 LUTs (about 60%), 88MHz\n\n2) Performance Optimized (EBC Mode)\nThis is a pipelined implementation that has a 48 cycle pipeline (plus 1 input and 1 output register). It can perform a complete encryption/decryption every cycle. \n- 0.18u UMC ASIC process: 55K Gates, 300MHz (19.2 Gbits/sec)\n- Virtex-II-1500-6: 79% utilization, 166Mhz (10.6 Gbits/sec)\n\n\n(Single) DES IP Core\n==================\n\n1) Area Optimized (CBC Mode) \nThis is a sequential implementation and needs 16 cycles to complete a full encryption/decryption cycle. \n- 0.18u UMC ASIC process: >155Mhz 3K Gates \n- Xilinx Spartan IIe-50: >100 MHz 1339 LUTs (87% device utilization)\n- Altera APEX 20KE-1: 1106 lcells >27MHz \n- Altera FLEX 10K50E-1: 1283 lcells >43MHz \n\n2) Performance Optimized (EBC Mode)\nThis is a pipelined implementation that has a 16 cycle pipeline (plus 1 input and 1 output register). It can perform a complete encryption/decryption every cycle. \n- 0.18u UMC ASIC process: >290Mhz 28K Gates \n- Xilinx Spartan IIe-200: 140 MHz 4448 LUTs (94% device utilization)\n- Altera APEX 20KE-1: 6688 lcells >53MHz \n- Altera FLEX 10K130E-1: 6485 lcells >76 Mhz \n \n\n\n \n \n \n\n===== \n Implementing the core =====\n\nNothing special about implementing the core.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Thanks to Sakamoto Yasuhiro for providing a key select unit that is 50% smaller than the original ! It has been updated in the area optimized version, but might also be applicable for other versions.\n- Added a triple DES version\n- Added many more test vectors to the single DES version\n- Added Encrypt/Decrypt input (Thanks to Mark Cynar for providing the code)\n- Changed Directory Structure\n- Improved test benches\n \n\n\n \n \n \n\n===== \n Change log =====\n\n- 10/7/2004 RU - Updated key select unit in the are optimized version\n- 31/10/2002 RU - Added Triple DES versions\n- 28/9/2002 RU - Added Xilinx Spartan 2e synthesis results\n- 10/6/2001 RU - Updated Directory Structure, added encrypt/decrypt, improved test bench \n- 9/14/2000 RU - Initial release\n\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: des status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nVHDL implementation of the classic DES block cipher (iterative architecture)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: descore status: Stable svn-updated: Aug 10, 2013 updated: Aug 10, 2013 wishbone-compliant: 0 - category: ECC core created: Jul 30, 2014 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: design_of_soft_error_resilient_fpga status: Empty updated: Aug 3, 2014 wishbone-compliant: 0 - category: Crypto core created: Mar 6, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: desl status: Empty updated: Apr 16, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nVHDL implementation of the DESL block cipher (iterative architecture)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: deslcore status: Stable svn-updated: Aug 10, 2013 updated: Aug 10, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nVHDL implementation of the DESLX block cipher (iterative architecture)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: deslxcore status: Stable svn-updated: Aug 10, 2013 updated: Aug 10, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nVHDL implementation of the DESX block cipher (iterative architecture)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: desxcore status: Stable svn-updated: Aug 10, 2013 updated: Aug 10, 2013 wishbone-compliant: 0 - category: Processor created: Dec 15, 2003 description: "===== \n Description =====\n\nThe data flow processor (DFP) is a flexible microprocessor written in VHDL which you can program down to the gate level to optimize your entire design. It is composed of 7 components with a specific data flow architecture. In most cases you just provide a VHDL file containing the program you want the processor to run, compile the whole design and then download it to an FPGA. For more specific designs, the code for the components can be altered to suit your needs. The components are:\n\nTR - top register - top-most register for manipulating data or data flow\nFU - function unit - provides functions to operate on data with TR and DS\nDS - data stack - for holding intermediate data values \nME - memory - holds data, program and memory mapped I/O\nPC - program counter - current address of program in memory\nRS - return stack - holds values from PC for program nesting and return\nIR - instruction register - runs instruction sequences from memory\n\nBy design, there is no bank of registers as in a conventional microprocessor design. This simplifies the instructions as they don't need a source or destination field. Instead, data items are pushed and popped to/from a stack. There is also no cache.\n\nThe idea is that since the FPGA ultimately will be manipulating data flows through it when it is running an application program, prebuilt soft processors ready for deployment and able to execute programs, can be used. While this is not new in of itself, the extension we add is flexibility, in that while the structure is there, it is also fully resizable and programmable. The depth of the stacks, the width of the data bus and the length of memory are all changeable parameters from 0,1,2... to chip limits.\n\nThe parameters are gleaned from compiling the code down to a hardware description language, VHDL in this case, for compiling or simulating with hardware tools.\n\nIn addition to changeable parameters, the instruction set is also programmable. When a DFP program is constructed, part of it will either define primitives, one or more instructions in a sequence, or include required ones from a library. The other part of a DFP program utilizes these primitives to form the basis language for the program. The program looks similar to assembler.\n\nFor more information, see the DFP and GCA websites:\nhttp://members.shaw.ca/dataflowprocessor/\nhttp://www.ece.ualberta.ca/strawbot/GCA/\n\n \n\n\n \n \n \n\n===== \n IMAGE: dfp.gif =====\n\nFILE: dfp.gif\nDESCRIPTION: Structure of the DFP\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- VHDL coded Data Flow Processor\n- VHDL coded RS232 interface, can be connected as a peripheral\n- DFP Program compiler with full documentation and example programs\n- DFP Program libraries including:\n\t- basic assembler primitives\n\t- stack manipulation primitives\n\t- multi-step math implentations of addition, subtraction, multiplication, and division (see the DFP website for more info) \n\t- Granular computing operations, including functionality for applications requiring fast fuzzy control\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Fully synthesizable with Xilinx ISE 6.1 (make sure to turn off ROM extraction in the properties for Synthesize - XST, under HDL Options tab)\n- Should be able to simulate with any VHDL simulator (tested with DirectVHDL, ModelSim, and Symphony EDA)\n- 4/30/05 For the Windows platform, there is a newer compile of the Timbre tool used for creating VHDL code at:\n http://members.shaw.ca/dataflowprocessor/Resources/DFP/DFPcompiler/\nor\n- major new release with many updates at:\n http://members.shaw.ca/strawbot/GCA\n- New website for natural artificial life forms using GCA technology:\n http://members.shaw.ca/calf/" homepage: http://members.shaw.ca/dataflowprocessor/ language: VHDL license: unknown maintainers: - strawbot name: dfp status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: DSP core created: Feb 6, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - orenr name: dft_fft status: Empty updated: Feb 6, 2012 wishbone-compliant: 0 - category: Testing / Verification created: Sep 5, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - yashajyothi name: dft_technique_for_asynchronous_dominant_soc status: Empty updated: Sep 5, 2013 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/dgsim.doc category: Arithmetic core created: Jan 26, 2015 description: '' language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - buaaww name: dgsim status: Empty updated: Jan 28, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Jan 28, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dk2npz name: digfilter status: Empty updated: Jan 29, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Jun 10, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - perthpiti name: digital_pet status: Empty updated: Jun 11, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Oct 5, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: digitales_2 status: Empty updated: Oct 5, 2011 wishbone-compliant: 0 - category: Processor created: Feb 1, 2008 description: "===== \n Description =====\n\nThis Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture. Please note that it was developed on a Sparten-3E Starter Kit and memory in VHDL code is embedded via XILINX specific routines.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Assembler\n- Simulator\n- Simple I/O (Leds, Buttons, UART, Hitachi LCD)\n- VGA Controller\n \n\n\n \n \n \n\n===== \n Status =====\n\n- presented in class as working" language: VHDL license: unknown maintainers: - fellnhofer name: diogenes status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Sep 29, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: direct_sequence_spread_spectrum_dsss-cdma_implementation status: Empty updated: Sep 29, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Jul 19, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hosier name: displayport_sink status: Empty updated: Jul 21, 2014 wishbone-compliant: 0 - category: Processor created: Nov 8, 2009 description: "===== \n Description =====\n\nsimple alu" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - leoel name: distributed_intelligence status: Planning svn-updated: Nov 8, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Oct 28, 2002 description: "===== \n Description =====\n\nThis is a collection of synthesizeable hardware dividers. Different types of dividers are available. All dividers are fully pipelined and provide a 2N by N division every clock cycle. All designs are fully parameteriseable and synthesizeable.\nThe dividers take two inputs Z(2N-bit divident) and D(N-bit divisor), and return Q(N-bit quotient), S(N-bit remainder), div0(division by zero), and ovf(overflow).\nA sample implementation of a 32/16 bit divider with a remainder output runs at about 82MHz in a Spartan2e100 -6 device and occupies 1132 LUTs (about 47%) and 1736 registers (about 72%) of the device.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Fully synthesiseable\n- Fully parameteriseable\n- Pipelined design (one pipeline stage per bit) provides a result every clock cycle.\n- Includes testbench\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe following division units are ready and available for download:\n- Non-restoring unsigned by unsiged divider\n- Non-restoring signed by unsiged divider" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rherveille name: divider status: Stable svn-updated: May 5, 2009 updated: Sep 28, 2011 wishbone-compliant: 0 - category: System on Chip created: Mar 25, 2011 description: "===== \n Description =====\n\nSingle channel 32 or 64 bit AHB master DMA core. Supports simultaneous read and write, command lists, peripheral control, timeouts and endianess swapping. Based on Provartec PR201 http://www.provartec.com/ipproducts \n \n\n\n \n \n \n\n===== \n Related projects =====\n\nGeneric AHB matrix\nhttp://opencores.org/project,robust_ahb_matrix" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: dma_ahb status: Mature svn-updated: Apr 3, 2011 updated: Jun 25, 2013 wishbone-compliant: 0 - category: System on Chip created: Mar 25, 2011 description: "===== \n Description =====\n\nSingle channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control, timeouts and endianess swapping. Based on Provartec PR200 http://www.provartec.com/ipproducts\n\n \n\n\n \n \n \n\n===== \n Related projects =====\n\nGeneric AXI interconnect fabric\nhttp://opencores.org/project,robust_axi_fabric" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: dma_axi status: Mature svn-updated: Apr 3, 2011 updated: Apr 29, 2011 wishbone-compliant: 0 - category: System on Chip created: Mar 25, 2011 description: "===== \n Description =====\n\nThese is an obsolete project that should be removed.\nPlease refer to the AHB DMA 32 / 64 bits project" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: dma_axi32 status: Empty updated: Apr 12, 2011 wishbone-compliant: 0 - category: Communication controller created: May 15, 2004 description: "===== \n Description =====\n\nDiscrete Multi Tone (DMT) is the modulation scheme used for Asymmetric Digital Subscriber Line (ADSL) systems and one of the modulation schemes used for Very high-speed Digital Subscriber Line (VDSL) systems.\n\nGoal of the project is to implement the individual building blocks of a DMT transceiver, following ITU-T recommendation G.992.1 for ADSL systems.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Following ITU-T recommendation G.992.1 ADSL\n- No trellis support\n- No echo cancellation\n\n\nPhase 1, DMT Modem:\n\n- Constellation encoder\n- Gain\n- IDFT\n- Cyclic prefix\n\n- TDQ\n- Cyclic prefix\n- DFT\n- Constellation decoder\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Working on DMT Modem\n \n\n\n \n \n \n\n===== \n Statistic =====" language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - dannori name: dmt_tx status: Planning svn-updated: Jul 14, 2010 updated: Nov 7, 2011 wishbone-compliant: 0 - category: Communication controller created: Aug 7, 2010 description: "===== \n Description =====\n\nThis core is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\n\nDMX protocol fully implemented in hardware\nDMX channels simply mapped in CSR address space\nThru mode enables operation as a traditional DMX receiving device\n\n \n\n\n \n \n \n\n===== \n More information =====\n\n\nCSR bus specifications\nCore documentation\nDMX512 at Wikipedia" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: dmx512 status: FPGA proven svn-updated: Aug 24, 2010 updated: Aug 13, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Jan 7, 2009 description: "===== \n Features =====\n\n- The unit is designed to be synchronous to one global clock. All registers are updated on the rising edge of the clock.\n- All registers can be reset with one global reset.\n- The multiply operation is broken up to take advantage of the 25 x 18 multiply blocks in the Virtex5 DSP48E slices. The 25 x 18 multiply twos complement block will perform a 24 x 17 unsigned multiply, so it takes 9 DSP48E slices to perform the 53 x 53 bit multiply required to multiply two double-precision floating point numbers.\n- fpu_double.v is the top-level module. The input signals are:\n- 1) clk\n- 2) rst\n- 3) enable\n- 4) rmode (rounding mode)\n- 5) fpu_op (operation code)\n- 6) opa (64-bit floating point number)\n- 7) opb (64-bit floating point number)\n\n- The output signals are:\n- 1) out (64-bit floating point output)\n- 2) ready (goes high when the output is ready)\n- 3) underflow\n- 4) overflow\n- 5) inexact\n- 6) exception\n- 7) invalid\n\n- Each operation takes the following amount of clock cycles to complete:\n- 1.\taddition : \t\t 20 clock cycles\n- 2.\tsubtraction: \t\t21 clock cycles\n- 3.\tmultiplication: \t 24 clock cycles\n- 4.\tdivision:\t\t 71 clock cycles\n\n- This is longer than some floating point units, but the support for denormalized numbers requires several more logic levels and a longer latency.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- version 1\n- pipelined versions of add/sub and multiply are included in the \"pipeline\" folder\n \n\n\n \n \n \n\n===== \n Double Precision Floating Point Unit =====\n\nIEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4 rounding modes (nearest, 0, +inf, -inf). This unit also supports denormalized numbers, which is rare because most floating point units treat denormalized numbers as zero. The unit can run at clock frequencies up to 230 MHz for a Virtex5 target device.\nAlso, a pipelined version of add/sub and multiply is available in the pipeline folder. Add/sub has a latency of 24 clock cycles, then an answer is available on each clock cycle. Multiply has a latency of 21 clock cycles. Denormalized numbers are treated as 0 by the pipelined versions." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - davidklun name: double_fpu status: Design done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/dpll-isdn.doc category: Arithmetic core created: Mar 30, 2011 description: "===== \n References =====\n\n1.\tYamamoto H., Mori S. Performance of a binary quantized all digital phase-locked loop with a new class of sequential filter//IEEE Trans. \xE2\x80\x93 1978. \xE2\x80\x93 V. Com-26, \xE2\x84\x961. \xE2\x80\x93 P. 35-45.\n\n2.\tCessna J.R., Levy D.M. Phase noise and transient times for a binary quantized digital phase-locked loop in which Gaussian noise//IEEE Trans. \xE2\x80\x93 1972. \xE2\x80\x93 V. Com-20, \xE2\x84\x962. \xE2\x80\x93 P. 94-104.\n\n3.\tYukawa J., Mori S. A binary quantized digital phase-locked loop//IECE. \xE2\x80\x93 1973. \xE2\x80\x93 Vol. 56-A, \xE2\x84\x9612. \xE2\x80\x93 P. 79-85." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dmsu name: dpll-isdn status: Stable updated: Feb 18, 2013 wishbone-compliant: 0 - category: Memory core created: Nov 1, 2013 description: "===== \n Description =====\n\nThis project provides a parameterizable synchronous FIFO which uses LUTs instead of Block RAMs for its memory. The FIFO can be parameterized in depth and width. It has been used in a number of commercial products. It is primarily used for implementing small buffers for the transmit and receive functions of UARTs. (A companion project, BRSFmnCE, provides the same basic functionality using block RAMs.)\n \n\n\n \n \n \n\n===== \n Synthesis/PAR Summary =====\n\nThe DPSFmnCE has been used in several projects/products. It is generally used as a small FIFO for UARTs. The following synthesis and Map/PAR results effectively summarize the resource utilization of the DPSFmnCE in a XC3S50A-4VQG100I FPGA. This FPGA is not the only one in which DPSFmnCE has been used, but it allows the characterization of the resource requirements of the DPSFmnCE.\n\nResults for 16 x 8 Distributed RAM Synchronous FIFO\n\nNumber of Occupied Slices: 32\nNumber of Slice FFs: 14\nNumber of 4-input LUTs: 52\n Number used a Logic: 20\n Number used as RAMs: 32\n\nReported Speed (Synthesizer): 276 MHz\nReported Speed (MAP/PAR): 252 MHz" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelA name: dpsfmnce status: FPGA proven svn-updated: Nov 2, 2013 updated: Nov 2, 2013 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/dqpsk-r2.tar.gz category: Communication controller created: Mar 6, 2013 description: "===== \n Description =====" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: dqpsk status: Planning svn-updated: Apr 16, 2013 updated: Apr 19, 2013 wishbone-compliant: 0 - category: Communication controller created: Sep 28, 2013 description: "===== \n Description =====\n\nDQPSK symbol mapper suitable for TETRA/APCO-25 physical layer." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: dqpskmap status: Stable svn-updated: Sep 29, 2013 updated: Sep 29, 2013 wishbone-compliant: 0 - category: Memory core created: Sep 25, 2001 description: "===== \n Description =====\n\nParameterisable DRAM model, i.e. scalable data and address widths. Simulation assertions can be toggled on/off. Uses !RAS/!CAS control sequence for modelling DRAM activity. Refresh is monitored with data corrupted to \"UU ... \" \n \n\n\n \n \n \n\n===== \n Status =====\n\n- VHDL code is available (see Downloads)\n \n\n\n \n \n \n\n===== \n Author =====\n\n- Damon P Thompson" language: VHDL license: custom licensetext: "This VHDL design file is an open design; you can redistribute it and/or\nmodify it and/or implement it under the terms of the Openip General Public\nLicense as it is going to be published by the OpenIP Organization and any\ncoming versions of this license.\nYou can check the draft license at\nhttp://www.opencores.org/OIPC/license.shtml\n" maintainers: [] name: dram status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Testing / Verification created: Dec 17, 2009 description: "===== \n Description =====\n\nDS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and include the macro tasks based on that write/read tasks. A test with macros is included. Only the Slope and the Counter registers are not supported." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - akhachat name: ds1621 status: Beta svn-updated: Apr 7, 2010 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Nov 18, 2011 description: "===== \n Description =====\n\nA controller manages the communication with the DS2348 chip. It writes the CONV and CONT commands, and it reads the current, voltage and temperature value. \nFPGA proven." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qwert name: ds2348_ctrl status: Empty updated: May 12, 2014 wishbone-compliant: 0 - category: System controller created: Jul 28, 2005 description: "===== \n Description =====\n\nA project aimed at providing a DSP/FPGA based development board. \n\nTesting has begun, so far Power supplies, DSP, FPGAs have been proven to be 100% functional. Testing of the SDRAM and FLASH memories has be started and will require time for pattern read/write to be completed. \n\nIf you are interested in this dev kit please contact me by my email address. I will be happy to call/email you back with more details. We have 3 more kits available, but will require assembling (typ. 2 weeks) before they can be shipped. We have not determined a price for kits yet, but reasonable offers will be accepted. \n\nWe are also working a seconday IDE to the TI CCS to allow lower cost development. This is not a primary task as we have CCS2, but realise that for students/personal use CCS2 is too expensive. We are considering opening a compile farm to allow users to upload a project and receive a compiled a.out file that would be loaded into the Flash via HPI from a PC with download utilities. If you would like to help on this aspect, please contact me by email.\n\nA datashort is provided at http://www.qortek.com/products.aspx additionally you can contact QorTek for Pricing of Kits. Kit prices are determined to cover parts, pcb and assembly, or partial assembly. Sorry we can't give these away :(\n\n\nNov 15, 2005\nSDRAM was tested at full EMIF speed (100Mhz) Initial testing showed no problems.\n\nEMIF to WB_Master interface implemented. Tested working at 50Mhz, optimitize to work at 100Mhz.\n\nNov 19 2005\nDSP cards tested in cPCI chassis, and PCI bus testing began!! Working out a few issues between WB master and WB Slave on PCI core.\n\nNov 23 2005\nDSP and PCI core are talking via WB interface! WB bus speed has been droped to 50MHz due to PCI core timing constraints. A second cPCI communication card developed by QorTek is being programmed with the PCI core and an internal RAM Block for DSP to PCI access testing. \n\nA few schematic entry errors have been identified and fixed for a REV 1 release. None of the errors are show stoppers! A new release of the schematic will appear soon noting schemitcal errors.\n\nDec 13th 2005\nLots of HDL coding and simulation and in system testing has been done. We are working to release a core for the board to connect the DSP to the PCI Core. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Standalone Operation w/ cPCI Interface\n - PICMG 2.0 REV 3.0 ( pending testing ) \n - 3U cPCI Card or Standalone operation.\n - Daughter Card interface for user defined hardware.\n - 1 TI TMS320C6713GDP Processor 300MHz\n - ALL GPIOs routed out to Daughter Card and FT256 BGA\n - 1 Xilinx XC3S1000FG320 BGA ( Main bus interface/arbitrator )\n - 1 Xilinx XC3SxxxxFT256 (User defined applications )\n - All DSP GPIO available, user definable routing to External Interface\n - DSP HPI Interface for programming / data exchange\n - 4 40pin Header Daughter Card interface\n - Fully qualified 32bit data/20bit Address bus\n - 24 GPIO (SE) or 20 GPIO w/4DP (user definable) 8 Shared with Xinterface\n - ALL DSP GPIO Pins available\n - 1 68Pin (scsi like connector) External Interface/GPIO\n - All Signal Routed to FT256\n - 48 GPIO SE or 24 GPIO DP\n - 1 External Reset thru FPGA\n - 1 External Interrupt thru FPGA\n - IO Vref, 3.3v, and Ground included.\n - Multiple Power Supplies for FPGA VCCOs and DSP Core Voltage\n - User adjustable. 4A Max (execpt FPGA Vaux)\n - DSP Core voltages 1.2, 1.25, 1.4 (support all TI 6713 devices)\n - External Interface/GPIO Voltage range 1.2-3.3v in 0.1v increments.\n - FPGA Aux 2.5v (1.5A max)\n - FPGA Internal 1.8v\n - Includes Nexus (Altium Designer) JTAG Interface for interface to Nanoboard.\n - Open to sugestions\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Schematic Entry 100% done\n- PCB Layout/Simulations 95% done\n- PCB Testing/Assembly 50% done\n - PCB Power up testing complete. All Power Supplies working.\n - Power routing verified.\n - PCB Assembly Started. (Third party assembly)\n- Software / FPGA code 0% done\n - WISHBONE compliant IP Core to Link DSP to PCI Core. 0% Done.\n - WISHBONE compliant IP Core to Link Daughter Card IF to DSP/PCI Core.\n\n \n\n\n \n \n \n\n===== \n Images =====\n\nThis board is 95% fully assembled.\nhttp://opencores.com/project,dualspartainc6713cpci,DSP_near_done_tiny.jpg\n\nWe have begun writing FPGA and DSP code to link the PCI Bridge to the DSP and also allow users to program the DSP from the HPI. \n\nMore Imganes can be found here (not up to date, yet):\nhttp://opencores.org/project,dualspartainc6713cpci,images\n \n\n\n \n \n \n\n===== \n System Diagram =====\n\nhttp://opencores.org/project,dualspartainc6713cpci,SystemDiagram.jpg" language: Other license: unknown maintainers: - brianshea name: dualspartainc6713cpci status: Stable svn-updated: Mar 10, 2009 updated: Apr 16, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Nov 7, 2009 description: "===== \n Description =====\n\nIntroduction:\nFrom my thesis: Low-Density Parity Check (LDPC) coding is a form of error coding introduced by Gallager that can achieve performance close to the Shannon limit, exceeding the performance of Turbo codes. The coding scheme was introduced in the early 1960\xE2\x80\x99s, but has gained favor recently due to excellent performance and lack of patent rights. Several recent standards include optional or mandatory LDPC coding methods; among these is the second generation Digital Video Broadcasting standard for satellite applications (DVB-S2). This application is unencumbered by low latency requirements, so the standard employs strong coding over codewords 64,800 bits long. Although the standard was designed for low complexity in hardware, the length of the codewords makes this the most computationally intensive of LDPC codes described in current standards.\n\nProject:\nThis project should be interesting because the design goals are different from decoders used in other standards. Rather than trying to achieve fairly good error correction over small blocks in a short amount of time, this decoder uses very long codewords and a large number of configurations to achieve very good performance over a wide range of channels.\n\nThis project is based on a project I submitted toward fulfillment of my Master's degree in 2008. It originally targeted a 180nm ASIC library provided by the university, but I want to re-implement it for FPGA. There are areas in which I could use some help:\n\n- Verify functional correctness. It does work, in terms of correcting flipped bits, but I wrote the encoder, so it's possible I misunderstood something. An extra set of eyes checking my interpretation of the standard could be useful.\n- Testbench improvements. My noise model is just a bunch of files from which I randomly pull samples. I think it would be nicer to call a C function to add noise to the signal. There are a number of other minor improvements I'd like to make to the testbench as well.\n- Synthesis to FPGA. The RAM and ROM models I'm using now are suitable to implementation in FPGA, but they're still just behavioral models. I need to switch to real RAM's and ROM's, and build the project in a large FPGA.\n- General coding and testing. Checking over the code to find bugs or suggest improvements could be helpful.\n- Wishbone I/O? Right now, I load groups of bits into the decoder in parallel (360, 180 or 90 bits at a time, depending on certain parameters of the implementation). It might be better to add a standardized interface, perhaps Wishbone.\n- Looking forward. The design permits layered decoding, which is a method to reduce the number of iterations in the decoder while achieving the same performance. Unfortunately, something is going wrong when I change the ROM to layered decoding. It would be useful if someone could investigate this.\n\nStatus:\nI've lost some fairly important files due to entropy and a re-installation of the OS. In particular, I had C code for creating the ROM file and some C models to verify the Verilog's correctness that have been lost. Unfortunately, I'm not sure what bugs may exist in the current RTL that had actually already been fixed. A quick change to the ROM table allowed me to run a simulation (with ModelSim), and it successfully corrected the errors, but it will take me some time to get the project back into proper shape. To avoid any further loss, I'll check in all the RTL code and an overview document now." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jcorley name: dvb_s2_ldpc_decoder status: Planning svn-updated: Mar 30, 2010 updated: Dec 3, 2010 wishbone-compliant: 0 - category: Other created: Dec 23, 2004 description: "===== \n Features =====\n\nLeGall 5/3\nMax image size: 512x512 grey scale\nMax levels: 7\nTools: ISE Foundation 6.3i; ModelSim 5.7g\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis core implements Forward and Inverse Discrete Wavelet Transform (FDWT and IDWT) on still image. Wavelet LeGall 5/3 is selected in design. The project is simulated on ModelSim 5.7g and going to implement on Spartan-3 Starter Kit.\n \n\n\n \n \n \n\n===== \n Status =====\n\n11/10/2004: started\n20/12/2004: Core is correctly simulated on Lena image (512x512)." language: VHDL license: unknown maintainers: - vkchau name: dwt2d status: Beta svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Apr 29, 2002 description: "===== \n Description =====\n\n\n \n\n===== \n Features =====\n\n- feature1\n- feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\nReady for downloading via CVS. Path: e1framer" language: VHDL license: unknown maintainers: - victor name: e1framer status: Beta svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Apr 7, 2004 description: "===== \n E1 Framer & Deframer =====\n\nE1 framer Deframer core implements CCITT (ITU) recommedations G.704,G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate.\nNote:This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department / Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi. Please see http://www.iitd.ac.in/ee and http://www.iitd.ac.in/bsttm for details\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Frame Types supported:\n - E1 Basic frame\n - CRC Multiframe\n - CAS Multiframe\n\n- CAS R2 (Channel Associated Signalling Q.421) Implementation\n- 8 bit Microprocessor Interface\n- 512 bit slip buffer\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nCompleted" language: VHDL license: unknown maintainers: - hnpatel name: e1framerdeframer status: Beta svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Feb 12, 2012 description: "===== \n Description =====\n\nThe Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of $c$ identical elements in the elliptic curve group. \n\nThe elliptic curve is super-singular $E:y^2=x^3-x+1$ in affine coordinates defined over a Galois field $GF(3^m)$, $m=97$, whose irreducible polynomial is $x^97+x^12+2$.\n \nThe elliptic curve group is the set of solutions $(x,y)$ over $GF(3^m)$ to the equation of $E$, together with an additional point at infinity, denoted $O$. An element in the elliptic curve group is also called \xE2\x80\x9Ca point\xE2\x80\x9D. The elliptic curve group is abelian. The group law is described in the document/specification. \n\nThe Elliptic Curve Group core consists of two modules, one computing the addition of two elliptic curve group elements ($P_1+P_2$) and the other computing the addition of many identical elliptic curve group elements ($c\xE2\x8B\x85P_1$). The first module is called $point_add$. The second module is called $point_scalar_mult$.\n\nThe core is written in Verilog 2001, and it is carefully optimized for FPGA. For example, input signals are synchronous and sampled at the rising edge of the clock. Output signals are driven by flip-flops, and not directly connected to input signals by combinational logic. There is no latch, and only one clock domain in entire core. \n\nThe $point_add$ module runs at 192 MHz on the Xilinx Virtex-4 XC4VLX200-11FF1513 FPGA board. It computes one addition within 2.7 microseconds if with a 100MHz clock. The $point_add$ module uses 12,099 (6%) LUTs, 6,694 (7%) slices, 6,141 (3%) flip-flops of the XC4VLX200-11FF1513 FPGA board. \n\nThe $point_scalar_mult$ module runs at 148 MHz on the Xilinx Virtex-4 XC4VLX200-11FF1513 FPGA board. It computes one addition within 0.552 milliseconds if with a 100MHz clock. The $point_scalar_mult$ module uses 13,780 (7%) LUTs, 7,272 (8%) slices, 7,451 (4%) flip-flops of the XC4VLX200-11FF1513 FPGA board. \n\nThe core is open source, under the license of LGPL version 3.\n \n\n\n \n \n \n\n===== \n Technical specification =====\n\nSpecification Rev 0.1\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Elliptic Curve Group for hyper-elliptic curve $y^2=x^3-x+1$ \n- The irreducible polynomial is $x^97+x^12+2$ \n- Fully synchronous design \n- Fully synthesize-able \n- ONLY ONE clock domain in entire core \n- NO latch \n- All output signals are buffered \n- Vendor independent code\n \n\n\n \n \n \n\n===== \n Status =====\n\n- The core is ready and available in Verilog from OpenCores svn \n \n\n\n \n \n \n\n===== \n TODO =====\n\n- using projective coordinates may improve speed\n- adopting base-3 scalar multiplication value may improve speed, requiring base-2 to base-3 transforming function, and point tripling function\n \n\n\n \n \n \n\n===== \n Donation =====\n\nIf this project has helped you, please consider donating an FPGA to Homer Hsing (Xilinx FPGA is preferred). To donate him will help him develop more valuable project, and is to help you." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: ecg status: FPGA proven svn-updated: Mar 4, 2012 updated: Apr 18, 2012 wishbone-compliant: 0 - category: System on Chip created: Feb 3, 2014 description: "===== \n Current stable version =====\n\n/eco32/tags/eco32-0.26\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe ECO32 system is a microprocessor system-on-chip, consisting of\na 32-bit CPU and several controllers for peripheral devices (keyboard,\ncharacter display, timer, serial line, SDRAM, Flash-ROM, IDE disk).\n\nThe ECO32 CPU is a simple 32-bit RISC processor with an instruction\nset loosely modelled after MIPS, currently without floating point\ninstructions. We want to execute some flavour of UNIX on it, so it\nhas got two operating modes (kernel/user) and a memory management\nunit (paging with TLB support). The processor was first simulated\nat the instruction set level (the simulator is included), then at\nthe HDL level, and has finally been implemented in an FPGA.\n\nIncluded in the project is an ANSI C compiler (LCC from Fraser and\nHanson) with a back-end for ECO32, a simple tool chain (assembler\nand linker), as well as a monitor program, which can be flashed into\nnon-volatile memory on an FPGA board. Also included are tools to\ncreate a disk image which can be used as the system disk with the\nsimulator. A disk server makes this \"disk\" available for the real\nECO32 on an FPGA over a serial line. An IDE (parallel ATA) disk or\nan SSD can be accessed from the real ECO32 as well." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - hellwig name: eco32 status: FPGA proven svn-updated: Apr 25, 2015 updated: Mar 19, 2015 wishbone-compliant: 0 - category: Processor created: Mar 24, 2009 description: '' language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - leonous name: ecpu status: Planning svn-updated: Apr 1, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Mar 24, 2009 description: "===== \n Comments =====\n\n# ECPU 0.1.alpha \n# ==============\n#\n# Background\n# ========\n# Resurrected university project originally written in VHDL. \n# Converted to Verilog by hand and fixed bugs.\n# \n# Modifications made in verilog post-conversion:\n# - New barrel shifter\n# - Reviewed opcode list\n# - Enhanced testbench to allow for random stimulus (verilog only tb)\n# - Tested using Icarus \n# \n# Currently checking for synthesis:\n# - Passes synthesis checks using \"veriwell ... +synopsys\"\n# \n# Features\n# ========\n# * 15 working opcodes/functions :\n# cADD_AB \n# cINC_A \n# cINC_B \n# cSUB_AB \n# cCMP_AB - Same as Xor\n# cASL_AbyB - Uses last three bits of B (barrel shift)\n# cASR_AbyB - Uses last three bits of B (barrel shift)\n# cCLR - Clear outputs\n# cDEC_A \n# cDEC_B \n# cMUL_AB - not implemented [yet]\n# cCPL_A \n# cAND_AB \n# cOR_AB \n# cXOR_AB \n# cCPL_B \n# \n# * Flags C, V, Z - not implemented [yet]" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - leonous name: ecpu_alu status: Design done svn-updated: Apr 30, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Mar 1, 2014 description: "===== \n Description =====\n\n\n \n\nEdge is a microarchitecture implementation for mips1 ISA. \nIt has a 32 bit datapath divided into five pipeline stages operating at 50 MHz frequency. \nSupporting timer and other interrupt types and exceptions is implemented through co-processor0. \nEdge has been tested and verified on Atlys that has a Spartan-6 XC6SLX45 FPGA. \nFor the Atlys board, UART driver is provided to communicate with PC at 115200 baud rate. \n\n\n\n\n\n\nYoutube link for simple C programs running [1] \n\nhttps://www.youtube.com/watch?v=Hxwq2KWzycU" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - heshamelmatary name: edge status: Alpha svn-updated: Mar 2, 2014 updated: Jun 29, 2014 wishbone-compliant: 0 - category: Processor created: Apr 26, 2012 description: "===== \n Description =====\n\nA simple Educational 3 bus Architecture processor used as a tutorial mini-Project for Processor Controller and Instruction Set Architecture using VHDL without addressing modes for simplicity.\n \n\n\n \n \n \n\n===== \n Features =====\n\n32 Register 32bit each\n16 ALU Operation\n33 simple RISC ISA\ndo Files for each component\nTestbench file Describe the Processor behavior" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eng_ayman_mohamed name: edu_3bus_arch_processor status: Empty updated: May 18, 2013 wishbone-compliant: 0 - category: System on Chip created: Oct 25, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - moricy name: ela status: Empty updated: Oct 27, 2014 wishbone-compliant: 1 - alternate-download: http://liberatedcontent.de/openhardware/elm-r8.tar.gz category: Processor created: Feb 23, 2010 description: '' language: Verilog license: unknown maintainers: - dsheffie - rcharting name: elm status: Empty svn-updated: Feb 26, 2010 updated: Feb 26, 2010 wishbone-compliant: 0 - category: System on Chip created: Apr 8, 2002 description: "===== \n Description =====\n\nEmbedded 32-bit mini RISC uProcessor project with SDRAM controller will develope a basic block IP (Intellectual Properties) for designing a complete SOC (System On a Chip) system. Today almost in every Advanced Digital products you will find a few uController or uProcessor. Both of these cathegories needs a processing power to recieve some sord of input or data and needs to process it for the end application or perhaps to store the input/data. In order for the system to process or perhaps store the incoming data it needs to distinguish between the incoming command and data itself. This can be done by either a simple FSM (Finite State Machine) or a more complex circuitry such as a uProcessor.\n\nuProcessor need a space to store it's code and a seperate space to store it's temorary data informations. For this project since the entire system would be in a single chip I will create a SDRAM (Synchronous Dynamic Random Access Memory) controller which will recieve the uProcessor read and write command and translated into the approprite device cycles for SDRAM devices, SDRAM will be used to store the temporary Data. Also there would be an interface for the Flash memory to store our codes.\n\nThe embedded uProcessor for our SOC project would be a 32-bit RISC (Reduced Instruction Set Computer) which allows all the Instructions to be executed in a single clock cycle. \n\nEmbedded 32-bit mini RISC uProcessor for this project would have a five stage pipeline as follow:\n\n1) Fetch the Instruction \n2) Decode the Fetched Instruction \n3) Execute the Decoded Instruction \n4) Check the Flag and Interrupts \n5) Write to Register File \n\nFurthermore the SOC would have the following peripherals:\n\n. Bus Arbiter \n. Serial-to-Parallel Converter \n. Set Associative, two-way LRU Cache \n. DMA \n. PIO Interface \n. Timer \n. Watch-Dog Timer\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n*\t32-bit mini RISC uProcessor with SDRAM Controller\n*\tPC100 CL2 100 Mhz SDRAM Controller\n*\tSupports up to 8MB SDRAM for Data Storage\n*\tSupports up to 512KB Flash for Code Storage\n\nRepository:\nCVS:embedded_risc\n \n\n\n \n \n \n\n===== \n Status =====\n\n\xE2\x80\xA2\tPreliminary Architectural Block Diagram defining of the SOC Project is being prepared. 09/04/2002\n\xE2\x80\xA2\tPreliminary Architectural Block Diagram defining of the SOC project has been finished. 05/06/2002" language: Verilog license: unknown maintainers: - hosseinamidi name: embedded_risc status: Alpha svn-updated: Mar 10, 2009 updated: Mar 13, 2011 wishbone-compliant: 0 - category: Processor created: Apr 2, 2010 description: "===== \n Description =====\n\nEncore intends to explain basic microprocessor principles. Starting at a the simplest micro sequencer based level, all the way up to pipelines, caches, mmu, multi-datapaths etc." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: encore status: Alpha svn-updated: Feb 27, 2011 updated: Feb 19, 2011 wishbone-compliant: 0 - category: Prototype board created: Dec 17, 2009 description: "===== \n Description =====\n\nA FPGA development board based on EP2C35F672, with SDRAM and flash ." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - yless name: ep2c35_board status: Beta svn-updated: Sep 7, 2010 updated: Dec 20, 2009 wishbone-compliant: 0 - category: System on Chip created: Jul 9, 2009 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - erwing name: epc_rfid_transponder status: Alpha svn-updated: Jul 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Feb 2, 2003 description: "===== \n Description =====\n\nThis Module is EPP v1.9 and can communicate with a computer parallel port. It is memory less module and has got two bits to tell the module user about the arrival of data either address or data from Pc and when module user wants to transmitt the data he has to place the required bits i.e send_data bits to appropriate value and place the data in address or data register. The module has a special mode in which it forst transmitt the address to PC and than Data. The three spare bits are used to tell the PC about the data whether it is address or data and also it sets spare3 bit when it has get data from PC and when that data is removed by the module user than it will reset that spare3 bit.\n \n \n\n\n \n \n \n\n===== \n Features =====\n\n- data and address read and write capability\n- can tell the PC to wait as the processing is going on.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Completed\n- ..." language: '' license: unknown maintainers: - ahmadyar name: epp status: Empty svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/erp.v category: Processor created: Sep 17, 2004 description: "===== \n Description =====\n\nAn implementable and enhancable RISC Core developed in Verilog HDL, tested on Xilinx IIE Spartan FPGA.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\n-Currently present Verilog Module is implementable, and also enhancements could be made as desired\n- status2" language: Verilog license: unknown maintainers: - shahzadjk name: erp status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 26, 2014 wishbone-compliant: 0 - category: Communication controller created: Apr 9, 2014 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lmaarsen name: esoc status: Design done svn-updated: Aug 23, 2014 updated: Jul 5, 2014 wishbone-compliant: 0 - category: Communication controller created: Oct 9, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jrwagz name: ether_arp_1g status: Planning svn-updated: Oct 11, 2011 updated: Oct 9, 2011 wishbone-compliant: 0 - category: Other created: Jul 16, 2012 description: "===== \n EtherLab =====\n\nEtherLab sends data via Ethernet packets from the Spartan-3E StarterKit to\n a host PC or vice versa.\n \n Protocol\n The transport protocol is the name giving EtherLab protocol, that comes \n directly after the Ethernet layer. An EtherLab layer provides 8 seperate\n channels each transporting 16 bit of data.\n \n Hardware\n The hardware reads and sends EtherLab packets only and communicates with \n the 4 D/A Converters, LEDs, swithes, buttons, digital inputs and outputs.\n \n EtherSocket \n EtherSocket is a C# implementation based on Pcap.Net and provides the bare\n minimum functions to read and send EtherLab datagrams. Incomming data is \n read constantly in a seperate thread. To send data, the user first updates\n at least one channel and sends the entire updated packet afterwards.\n \n LabVIEW\n The C# EtherSocket implementation has been ported to LabVIEW. Polymorphic\n VIs provide custom read and update operations for Booleans and Floats.\n \n\n\n \n \n \n\n===== \n Legal Notice =====\n\nCopyright (C)2012 Mathias H\xC3\xB6rtnagl \n\nThis program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. \n\nThis program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - idiolatrie name: etherlab status: Beta svn-updated: Jul 20, 2012 updated: Nov 25, 2012 wishbone-compliant: 0 - category: Communication controller created: Nov 25, 2005 description: "===== \n Description =====\n\nmail group is added to track all the Q&A from the author. \nIf you have any question about the design, please send your question to mail group. The answer will be recorded as reference for other people. \nHomepage: http://groups.google.com/group/opencores-tri-mode-eth-mac \nGroup email: opencores-tri-mode-eth-mac@googlegroups.com \n\n\n10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The whole project will be finished in TEN weeks inluding verilog coding,RTL level verification.\nA GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.\n\n \n\n\n \n \n \n\n===== \n main Features =====\n\n\xC3\x98\tImplements the full 802.3 specifiction.\n\xC3\x98\thalf-duplex support for 10 100 Mbps mode\n\xC3\x98\tFIFO insterface to user application\n\xC3\x98\tsupport pause frame generation and termination\n\xC3\x98\ttransmitting frames souce MAC address insertion\n\xC3\x98\treceiving frames destination MAC address filter\n\xC3\x98\treceiving broadcast frames throughout constraint\n\xC3\x98\tsupport Jumbo frame 9.6K\n\xC3\x98\tRMON MIB statistic counter\n\n \n\n\n \n \n \n\n===== \n Project Status =====\n\n- collect some documents about tri-mode ethernet MAC controller(done)\n- coding in verilog(done)\n- coding verification scripts(done)\n- starting verification(done)\n- writing specification(done)\n- FPGA proven(done) 2006-06-20\n- Supporting modelsim simulator. I also changed the default simulator from NC-sim to modelsim which is much populor than NC-sim :->. As well, the new version \"dll\" files for modelsim are ready. (done) 2008-7-26\n- My next task is to connect this IP core to xilinx Microblaze processor.(done)2008-8-17\nA new directory EDK was created in project root. All needed driver and EDF for EDK are available there. \n\n \n\n\n \n \n \n\n===== \n Synthesis area report =====\n\n##### START OF AREA REPORT #####\nI/O ATOMs: 321\n\nTotal LUTs: 1839 of 10570 (17%)\nLogic resources: 1839 ATOMs of 10570 (17%)\nATOM count by mode:\n normal: 1555\n arithmetic: 284\n\nDSP Blocks: 0 (0 nine-bit DSP elements).\nDSP Utilization: 0.00% of available 6 blocks (48 nine-bit).\nShiftTap: 0 (0 registers)\nMRAM: 0 (0% of 1)\nM4Ks: 0 (0% of 60)\nM512s: 0 (0% of 94)\nTotal ESB: 0 bits \n##### END OF AREA REPORT #####]\n\n \n\n\n \n \n \n\n===== \n verification report =====\n\n1. 1G mode ,46-1500 length packet sending and receiving was tested\n2. 100M mode, 46-1500 length packet sending and receiving was tested\n3. 10M mode , 46-1500 length packet sending and receiving was tested\n \n\n\n \n \n \n\n===== \n place and route report =====\n\nLogic Utilization:\n Number of Slice Flip Flops: 1,198 out of 21,504 5%\n Number of 4 input LUTs: 1,526 out of 21,504 7%\nLogic Distribution:\n Number of occupied Slices: 1,206 out of 10,752 11%\n Number of Slices containing only related logic: 1,206 out of 1,206 100%\n Number of Slices containing unrelated logic: 0 out of 1,206 0%\n *See NOTES below for an explanation of the effects of unrelated logic\nTotal Number 4 input LUTs: 1,555 out of 21,504 7%\n Number used as logic: 1,526\n Number used as a route-thru: 29\n Number of bonded IOBs: 78 out of 448 17%\n Number of BUFG/BUFGCTRLs: 5 out of 32 15%\n Number used as BUFGs: 2\n Number used as BUFGCTRLs: 3\n Number of FIFO16/RAMB16s: 4 out of 72 5%\n Number used as FIFO16s: 0\n Number used as RAMB16s: 4\n\nTotal equivalent gate count for design: 20,650\nAdditional JTAG gate count for IOBs: 3,744\nPeak Memory Usage: 220 MB" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - maverickist name: ethernet_tri_mode status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 19, 2015 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Description =====\n\nThe Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. \n\nThe MAC is the portion of ethernet core that handles the CSMA/CD protocol for transmission and reception of frames. It peforms Frame Data Encapsulation and Decapsulation, Frame Transmission, and Frame Reception.\n\nSize is approximately 28k gates (2400 flip-flops).\n \n\n\n \n \n \n\n===== \n Specification =====\n\n\nEthernet Design Document is being written (still under construction) Sep 5th). For downloading the working version see the Download section.\nEthernet Core Specification is updated (Sep 4th). For downloading see the Download section.\nEthernet Data Sheet (Product Brief) is finished. For downloading see the Download section.\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n\nAll modules are joined together in a complete Ethernet solution. (July 30, 2001).\nWISHBONE DMA Host interface is finished. (July 20, 2001). \nControl module is finished. (July 10, 2001).\nRxEthMAC module is updated (June 27, 2001).\nTxEthMAC module is updated (June 19, 2001).\nA MII Management Module is updated (June 02, 2001). \nWISHBONE master interface is finished. Additional DMA core is not needed any more (February 12, 2002)\nAddress recognition system is finished (February 18, 2002).\nEthernet Core tested in HW (March 3, 2002).\nEthernet Core running under uCLinux (April 17, 2002)\nEthernet Core improved (many bugs fixed). Running on Xess XCV800 board (under uCLinux), ORP board and and on Flextronics Semiconductor board with VirtexE 1600 on it. Tested with ping, tftp and ftp protocols (September 4, 2002).\nControl frame transmission and reception fixed. (November 22, 2002)\nEthernet MAC core was tested on Altera's NIOS board. (January 7, 2003)\nEthernet MAC core was updated. Some bugs were fixed. (January 30, 2003)\nTestbench finished. (January 30, 2003)\nEthernet MAC core was updated. Some bugs were fixed. (April 30, 2004)\nAdded support for simulation with Icarus Verilog (July 2011)\n\n\n\n\nThe IP core has been chosen by Flextronics Semiconductor, proven in FPGA technology and integrated into a Flextronics' design. Flextronics can offer commercial design services to companies that want to use this IP in their products - for more information fill out this questionnaire." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - igorm - knguyen - tadejm - olof - unneback name: ethmac status: ASIC and FPGA proven svn-updated: Feb 14, 2012 updated: Sep 2, 2013 wishbone-compliant: 1 - category: Communication controller created: Mar 24, 2005 description: "===== \n Description =====\n\nThe 10G ethernet mac core. It is compliant with ieee 802.3ae. Our plan is:\n\n1. reading specification\n2. observation of different companies 10g ethernet mac core specifcation /data sheets\n3. identify the difference between 10/100/1000/1g ethernet mac cores.\n4. make the specification\n5. make the architecure document\n6. make the design document\n7. RTL coding and verication\n8. validating it on fpga\n\nMain datapath logic is being tested on fpga now. Latest codes will be check in soon.\n \n \n\n\n \n \n \n\n===== \n Features =====\n\n- It is compliant with ieee 802.3ae\n \n- 10GBASE-R\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Planning\n- Reading specification\n- System design\n- Coding\n- Receive Engine passed simulation\n- Transmit Engine passed simulation\n- Main Datapath is being tested on fpga" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - eniac - sherry151 name: ethmac10g status: Alpha svn-updated: Mar 10, 2009 updated: Sep 23, 2010 wishbone-compliant: 0 - category: Prototype board created: Jan 23, 2006 description: "===== \n Description =====\n\nEUS 100LX is an \"open\" system board conforming to the PC104 format (90,2mm x 95,9mm) designed for industrial control and data acquisition applications. It is equipped with CPU, gate array and support electronics and comes with Linux operating system version 2.4 or 2.6, driver for communication with FPGA and peripheral devices, Allegro graphics library. Example FPGA cores are available in source form, as well as full board documentation - schematics, layout (available at http://www.dspfpga.com/?page=eus_100lx).\n \n\n\n \n \n \n\n===== \n Features =====\n\n- ETRAX 100LX / MCM4+16 CPU\n - 32 MB SDRAM, 8 - 64 MB Flash\n - FPGA Spartan 3-XC3S400 - 1500, connected directly on CPU bus\n - support for partial reconfiguration without readback\n - dedicated independent SDRAM for FPGA - 16MB\n - power management, watchdog, temperature and voltage sensors implemented in MSP430 microcontroller\n - 10/100Mb Ethernet port\n - 2 x USB 1.1 port\n - 1 x RS232 port for ETRAX and MSP (may be extended upto 4 ports)\n - JTAG interface for FPGA (Parallel Cable IV connector) and MSP\n - character LCD display supported including programmable backlight and contrast control\n - TFT LCD supported via linear framebuffer core, VGA support planned\n - 14 LVDS pairs or 28 LVTTL IOs\n - 90 separate input/output signals from FPGA, 5V tolerant\n - 94 general IO from ETRAX, MSP and FPGA\n - single power suplly voltage: 5V @ 600mA (depends on configuration and USB device consumption)\n - port of Allegro graphics library\n - boot over ethernet\n - FPGA initialization and communication tools\n - OS Linux, ftp, web, telnet\n - all source code licensed under GPL or OHGPL\n - royalty free application development software\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Schematic: done\n- PCB Layout: done\n- PCB Assembly & Testing: done\n- Linux 2.4: done\n- MCU Software: done\n- FPGA Boot & Communication utility: done\n- FPGA Codes adn Examples: starting - available soon\n \n\n\n \n \n \n\n===== \n Block Diagram =====\n\nhttp://opencores.org/project,eus100lx,EUS100LX_BD.gif\n \n\n\n \n \n \n\n===== \n Pictures =====\n\nhttp://opencores.org/project,eus100lx,180px-EUS_T_N.jpg (Top Side)\nhttp://opencores.org/project,eus100lx,180px-EUS_B_N.jpg (Bottom Side)" language: VHDL and Verilog license: OHGPL licenselink: http://liberatedcontent.de/openhardware/OHGPL-0.20.html maintainers: - slavek - freza name: eus100lx status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Prototype board created: Apr 28, 2008 description: "===== \n Description =====\n\nEUS FS is an \"open\" system board designed for industrial control and data acquisition applications. It is equipped with a 32-bit CPU working @ 200MHz (Etrax FS), Xilinx's gate array (Spartan 3E) and support electronics. A BSP package contains Linux operating system version 2.6, driver for communication with FPGA and peripheral devices. Example FPGA cores are available in source form, along with full board documentation and schematics.\n \n\n\n\n\n \n\n\n \n \n \n\n===== \n Features List =====\n\n- Board dimensions 85 x 55 mm (3.35 x 2.175\" )\n- 200MHz, 32bit Etrax FS processor\n- Up to 256MB SDRAM\n- 8 - 64 MB Flash\n- FPGA Spartan 3E - XC3S500-1600E connected directly on the CPU bus\n- Up to 64MB dedicated independent DDR SDRAM\n- Temperature, voltage and current consumption sensors implemented in MSP430 microcontroller\n- Unique board serial number\n- 10/100Mb Ethernet port\n- 1 x USB port\n- 1 x RS232 port (could be extended up to 4 ports)\n- JTAG interface for FPGA (Parallel Cable IV connector)\n- 91 separate input/output signals from FPGA\n- IO processor, peripheral or 72 general IOs from ETRAX processor\n- Single power supply voltage: 5V @ 700mA (depends on configuration and USB device consumption)\n- Boot over Ethernet\n- Opensource bootloader\n- FPGA initialization and communication tools\n- OS Linux 2.6, ftp, web server, telnet\n- All source code licensed under GPL or OHGPL\n- Three basic configurations:\n- Full system: Etrax FS + FPGA\n- Only Etrax processor\n- Only FPGA with Microblaze support\n- Evaluation Board is available\n- Board dimensions 160 x 100 mm (6.3 x 3.94\") - Eurocard compatible\n- 2 x IO connector 96 pin, DIN41612 Class 3 compatible, IO signals +5V compatible and protected\n- 1 x 10/100Mb Ethernet connector\n- 2 x RS232 Serial connectors\n- 2 x JTAG interface for FPGA and ETRAX FS (Paralel Cable IV connector)\n- 1 x JTAG interface for MCU MSP430\n- 1 x VGA analog video connector\n- 1 x USB host connector and 1 x USB peripheral connector\n- 1F high capacitance for RTC back-up\n- 8kB FRAM I2C memory\n- Keyboard with 5 buttons inclusive with LEDs + Reset button\n- Single power supply voltage 5V, socket for EIAJ standard power plug\n- SW Tool chain available\n\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Schematic: done\n- PCB Layout: done\n- PCB Assembly & Testing: done\n- U boot loader: done\n- Linux 2.6 kernel: done\n- PTXDist tool chain: done \n- FPGA Boot & Communication utility: done\n- FPGA Codes adn Examples: available\n \n\n\n \n \n \n\n===== \n Docs =====\n\nEUS FS Schematics, rev. 1.0 \nEUS FS Schematics, rev. 1.1\nStarter Board Schematic\n \n\n\n \n \n \n\n===== \n Reference designs =====\n\nFPGA Registers \nDDR Memory test based on Microblaze \nShows how to make LED blinking \nShows using of buttons to control LEDs \nShows how to use VGA interface \nShows how to connect registers into BUS interface" language: '' license: unknown maintainers: - slavek name: eusfs status: Empty svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Library created: Jan 6, 2006 description: "===== \n Description =====\n\nThis project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code.\n \n\n\n \n \n \n\n===== \n Features =====\n\nautomatic count stop/start value generation functions. You enter a time duration and clock frequency and the value is automatically computed. Your choice of binary or LFSR number spaces.\n\nLFSR counters created by function call.\n\nclock generation procedures\n\ntype and number conversion functions:\n\nsynthesizable binary_to_BCD and BCD_to_binary functions\nsynthesizable BCD_to_seven_segment display functions\nstring value to std_logic_vector: \"32\" -> \"0100000\"\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nProduction Ready. Please let me know of ANY problems you find.\n \n\n\n \n \n \n\n===== \n Project Type =====\n\nVHDL Library" language: VHDL license: custom licensetext: "Permission to use, copy, modify, distribute, and sell this source code\nfor any purpose is hereby granted without fee, provided that \nthe above copyright notices and this permission notice appear\nin all copies of this source code. \n\nTHIS SOURCE CODE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND, \nEXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, \nANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. \n\nTHE USER OF THIS SOURCE CODE ASSUMES ALL LIABILITY FOR THEIR USE\nOF THIS SOURCE CODE. \n\nIN NO EVENT SHALL MICHAEL BILLS BE LIABLE FOR ANY SPECIAL, INCIDENTAL, \nINDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\nRESULTING FROM LOSS OF USE, DATA, OR PROFITS, WHETHER OR NOT ADVISED OF\nTHE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING \nOUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. \n" maintainers: - mbills name: extension_pack status: Stable svn-updated: Mar 10, 2009 updated: Oct 25, 2010 wishbone-compliant: 0 - category: Testing / Verification created: Jul 26, 2013 description: "===== \n Description =====\n\nEziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in projects. Furthermore\xEF\xBC\x8Cmore functions and characteristics will be opened. This manual is intended for users with no previous experience with EziDebug . It introduces you with the basic flow how to set up EziDebug. The example used in this tutorial is a small design written in Verilog and only the most basic commands will be covered in this manual. This manual was made by using Version 1.0 of EziDebug on Windows." language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - EziDebug name: ezidebug status: Stable svn-updated: Aug 15, 2013 updated: Jul 29, 2013 wishbone-compliant: 0 - category: Communication controller created: Jul 23, 2014 description: "===== \n Description =====\n\nIt's a general purpose Cypress EZUSB communication core which was developed for ZTEX FPGA Boards and supports the following features:\n\n\n EZ-USB slave FIFO input\n EZ-USB slave FIFO output\n buffering and filtering of the interface clock from the EZ-USB\n Scheduler if both directions are active\n Automatic committing 'PKTEND' after timeout\n\n \n\n\n \n \n \n\n===== \n Interface =====\n\nThe usage of this core is best described by a commented port definition:\n\nmodule ezusb_io #(\n\tparameter CLKBUF_TYPE = \"\",\t// selects the clock preparation method (buffering, filtering, ...)\n\t // \"SPARTAN6\" for Xilinx Spartan 6, \n\t \t// \"SERIES7\" for Xilinx Series 7, \n\t \t// all other values: no clock preparation\n\tparameter OUTEP = 2, // EP for FPGA -> EZ-USB transfers\n\tparameter INEP = 6 // EP for EZ-USB -> FPGA transfers \n ) (\n output ifclk, // buffered output of the interface clock\n // this is the clock for the user logic\n input reset, // asynchronous reset input\n output reset_out, \t\t// synchronous reset output\n \n // FPGA pins that are connected directly to EZ-USB.\n input ifclk_in, // interface clock IFCLK\n inout [15:0] fd, // 16 bit data bus\n\toutput reg SLWR, PKTEND, // SLWR (slave write) and PKTEND (packet end) flags\n\toutput SLRD, SLOE, // SLRD (slave read) and SLOE (slave output enable) flags\n\toutput [1:0] FIFOADDR, // FIFOADDR pins select the endpoint\n\tinput EMPTY_FLAG, FULL_FLAG, // EMPTY and FULL flag of the slave FIFO interface\n \n\t// Signals for FPGA -> EZ-USB transfer. The are controlled by user logic.\n input [15:0] DI, // data written to EZ-USB\n input DI_valid,\t\t\t// 1 indicates valid data; DI and DI_valid must be hold if DI_ready is 0\n output DI_ready, \t\t// 1 if new data are accepted\n input DI_enable,\t\t// setting to 0 disables FPGA -> EZ-USB transfers\n input [15:0] pktend_timeout,\t// timeout in multiples of 65536 clocks before a short packet committed\n \t\t\t\t\t// setting to 0 disables this feature\n \n\t// Signals for EZ-USB -> FPGA transfer. They are controlled by user logic.\n output reg [15:0] DO, // data read from EZ-USB\n output reg DO_valid,\t\t// 1 indicates valid data\n input DO_ready,\t\t\t// setting to 1 enables writing new data to DO in next clock\n // DO and DO_valid are hold if DO_ready is 0\n \t\t\t\t\t// set to 0 to disable data reads \n // debug output\n output [3:0] status\n );\n\n \n\n\n \n \n \n\n===== \n Verilog instantiation example =====\n\nThis is an example instantiation in Verilog:\n\n\nezusb_io #(\n\t.OUTEP(2),\t\t // EP2 for FPGA -> EZ-USB transfers\n\t.INEP(6), \t\t // EP6 for EZ-USB -> FPGA transfers \n\t.CLKBUF_TYPE(\"SERIES7\")\t\t// selects the clock preparation method (buffering, filtering, ...)\n\t // \"SPARTAN6\" for Xilinx Spartan 6, \n\t \t// \"SERIES7\" for Xilinx Series 7, \n\t \t// all other values: no clock preparation\n ) ezusb_io_inst (\n .ifclk(ifclk),\n .reset(reset), \t\t\n .reset_out(reset_usb),\t\t\n\n // pins\n .ifclk_in(ifclk_in),\n .fd(fd),\n\t.SLWR(SLWR),\n\t.SLRD(SLRD),\n\t.SLOE(SLOE), \n\t.PKTEND(PKTEND),\n\t.FIFOADDR({FIFOADDR1, FIFOADDR0}), \n\t.EMPTY_FLAG(FLAGA),\n\t.FULL_FLAG(FLAGB),\n\n\t// signals for FPGA -> EZ-USB transfer\n\t.DI(rd_buf[15:0]),\t\t\n\t.DI_valid(USB_DI_valid),\t\n\t.DI_ready(USB_DI_ready),\t\n\t.DI_enable(1'b1),\t\t\n .pktend_timeout(16'd73),\t// timeout in multiples of 65536 clocks (approx. 0.1s @ 48 MHz) before a short packet committed\n \t\t\t\t\t\n\t// signals for EZ-USB -> FPGA transfer\n\t.DO(USB_DO),\t\t\t\n\t.DO_valid(USB_DO_valid),\t\n\t.DO_ready((mode_buf==2'd0) && !reset_ifclk && !FULL),\t\n // debug output\n\t.status(if_status)\t\n );\n\n \n\n\n \n \n \n\n===== \n VHDL instantiation example =====\n\nA component declaration of the module can be found in file ezusb_io_component.vhdl\nThis is the VHDL variant of the instantiation from above.\n\n\n-- ...\nsignal reset2 : std_logic;\nsignal DO_ready : std_logic;\n\nbegin\n\n ezusb_io_inst : ezusb_io \n generic map (\n\tOUTEP => 2,\t\t -- EP for FPGA -> EZ-USB transfers\n\tINEP => 6 \t\t -- EP for EZ-USB -> FPGA transfers \n ) \n port map (\n\tifclk => ifclk,\n reset => reset, \t\t-- asynchronous reset input\n reset_out => reset_usb,\t\t-- synchronous reset output\n -- pins\n ifclk_in => ifclk_in,\n fd\t => fd,\n\tSLWR\t => SLWR,\n\tSLRD => SLRD,\n\tSLOE => SLOE, \n\tPKTEND => PKTEND,\n\tFIFOADDR(0)=> FIFOADDR0, \n\tFIFOADDR(1)=> FIFOADDR1, \n\tEMPTY_FLAG => FLAGA,\n\tFULL_FLAG => FLAGB,\n\t-- signals for FPGA -> EZ-USB transfer\n\tDI\t => rd_buf(15 downto 0),\t-- data written to EZ-USB\n\tDI_valid => USB_DI_valid,\t\t-- 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0\n\tDI_ready => USB_DI_ready,\t\t-- 1 if new data are accepted\n\tDI_enable => '1',\t\t\t-- setting to 0 disables FPGA -> EZ-USB transfers\n pktend_timeout => conv_std_logic_vector(90,16),\t\t-- timeout in multiples of 65536 clocks (approx. 0.1s @ 48 MHz) before a short packet committed\n \t\t\t\t\t\t-- setting to 0 disables this feature\n\t-- signals for EZ-USB -> FPGA transfer\n\tDO => USB_DO,\t\t\t-- data read from EZ-USB\n\tDO_valid => USB_DO_valid,\t\t-- 1 indicated valid data\n\tDO_ready => DO_ready,\t\t\t-- setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0\n -- debug output\n\tstatus\t => if_status\n );\n\n reset2" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ZTEX name: ezusb_io status: Stable svn-updated: Jul 29, 2014 updated: Jul 29, 2014 wishbone-compliant: 0 - category: Prototype board created: Apr 19, 2004 description: "===== \n Description =====\n\nTarget of this project is development FPGA and/or FPGA powered real time audio DSP applications. This is Free (like freedom) Hardware project, a PCI card with stand-alone possibility, with high-end digital and analog audio interfaces and MIDI.\n\nPossible target development areas will be:\n- Audio effects and delays \n- Equalizers (or digital audio filters of any type)\n- Acoustics correction\n- Digital crossovers (for loudspeaker systems)\n- Voice recognition\n- Synthesizers/samplers\n- Sample rate converters\n- Jitter attenuation\n- Mixing\n- Studio mastering\n- Audio measurements\n- Audio streaming (Ethernet, ATM,...)\n- Geophone and Hydrophone applications\n- Medical applications\n- Etc.\n\n\n\nNOTES\n\n- abbreviation FAC2222M is Free Audio Card with 2 analog inputs, 2 analog outputs, 2 digital input channels, 2 digital output channels and MIDI in/out interface.\n\n\n\nWhy FPGA based audio DSP?\n\n- Classic DSP processors have no (or too few, IMHO) available free software developer tools.\n- All nonFPGA digital audio implementations (classic DSP and/or PC) have problems with latencies (3ms or more will be hard to tolerate), especially for a number of cascaded processing procedures. FAC2222M card will be PC and/or MIDI controller guided, and PC will not be processing engine. In that case FPGA will give \"brute force\" to solve problem with latencies.\n- We know that FPGA will have single or small number of possible DSP functions implemented in same time. That is not real problem if card will be used for testing single VHDL/Verilog DSP implementations. If we provide USB (re)configuration on-the-fly, FPGA small possible DSP capacity drawback will not be that big as we expected. FAC2222M will be reconfigurable piece of hardware, with free (like freedom) firmware and with free source for it, loadable through USB (also).\n- Why not?\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nHardware project Audio DSP PCI Card is still in planning phase. All possible and reasonable suggestions and questions will be greatly appreciated.\nPlease send them to http://www.opencores.org/forums.cgi/cores/post (cores mailing list)." language: '' license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - boggy - zorica name: fac2222m status: Empty svn-updated: Mar 10, 2009 updated: May 8, 2006 wishbone-compliant: 0 - category: Arithmetic core created: May 28, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - neeraj93 name: face_detection_verilog1995 status: Empty updated: May 28, 2013 wishbone-compliant: 0 - category: Communication controller created: Dec 14, 2012 description: "===== \n Description =====\n\nThis project implements the simple and light protocol for transmission\nof data from low resources FPGA connected to the Ethernet PHY\nand an embedded system running Linux OS.\nThe main goal was to assure the reliable transmission over unreliable\nEthernet link without need to buffer significant amount of data\nin the FPGA. This created a need to obtain possibly early \nacknowledgment of received packets from the embedded system,\nand therefore the protocol had to be implemented in layer 3.\n\nThe Ethernet type 0xfade was used (unregistered, but as this\nprotocol should be used only in a small private networks,\nwithout routers, with switches only, it should not be a problem).\n\nWe assume, that the FPGA is capable to store one \"set\" of packets\n(in the example design length of this set is equal to 32).\nTo start the transmission, receiver sends the \"start transmission\"\npacket:\n\n\nTGT,SRC,0xfade,0x0001,pad to 64 bytes\n\n\n\nAfter reception of the \"start transmission\" packet, the transmitter\n(FPGA) starts to send the data packets:\n\n\nTGT,SRC,0xfade,0xa5a5,set & packet number, delay, 1024 bytes of data\n\n\n\nAfter reception of the correct data packet, the receiver sends the\n\"acknowledge\" packet:\n\n\nTGT,SRC,0xfade,0x0003,set & packet number, pad to 64 bytes\n\n\n\nAnother packet may be used to request immediate stop of transmission:\n\n\nTGT,SRC,0xfade,0x0005, pad to 64 bytes\n\n\n\nWhen first packets from the current set buffered in FPGA are \ntransmitted and acknowledged, they may be replaced with the packets\nfrom the next set - the current state of transmission is stored\nin desc_memory in the desc_manager entity.\n\nWhen particular packet is not acknowledged, it is transmitted once\nagain. In current example design each packet has simple attributes:\n\nset number\nvalid (ready to be sent)\nsent (has been sent at least once - used for delay adaptation)\nconfirmed (reception has been confirmed, packet may be replaced\n with the same packet from the next set)\n\nList of packets is cyclically browsed to move the \"head\" and \"tail\"\npointers.\nIf the data packets are sent too quickly, the acknowledge\npackets from the embedded system are received too late,\nand the packet is retransmitted before acknowledge arrives.\nThe same may occur if the embedded system is overloaded \nwith packets from different slaves and drops some packets.\nTherefore paradoxically resending of packets as soon as possible\ndoes not provide the maximal throughput, and a delay between\npackets must be introduced.\nOf course if this delay is too big, the transmission also slows down.\nTo find the optimal delay, I have implemented a simple adaptive\nalgorithm based on analysis of the ratio between number of all sent\npackets and of retransmitted packets: Nretr/Nall\nIf the data packets are sent too quickly, the ratio of Nretr/Nall\nincreases indicating, that the delay should be higher.\nIf the ratio Nretr/Nall is near to 0, we may reduce the delay.\nSuch a simple algorithm works quite satisfactory.\n\nIn the embedded system, the fpga_l3_fade.ko driver allows you\nto service multiple FPGA slaves connected to different network\ninterfaces.\nThe \"max_slaves\" parameter lets you to set the maximum number of \nslaves, when module is loaded.\n\nAfter that, you can open /dev/l3_fpga0, /dev/l3_fpga1 ...\ndevices, to connect different slaves.\nTo connect one of those devices to particular FPGA slave,\nyou need to use the ioctl command L3_V1_IOC_STARTMAC \n(please see the attached receiver2.c application for\nan example).\nThe data received from the FPGA are placed in a kernel\nbuffer (each subdevice has its own buffer) which may be mmapped\nto the user space application, providing very quick access\nto the data. Another ioctl commands: L3_V1_IOC_READPTRS\nand L3_V1_IOC_WRITEPTRS allow you to read the head and tail\npointers in this buffer and to confirm reception of data.\nThe attached receiver2.c application uses the described\nmechanisms and simply tests, if the connected FPGA slave\nsends consecutive 32-bit integers.\n\nThe project is also hosted at my website:\nhttp://www.ise.pw.edu.pl/~wzab/fpga_l3_fade\n\nDescription of the project is also available at http://arxiv.org/abs/1208.4490\nThe updated description is published in the article: http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=1763152 \n\n===== DISCLAIMER: =====\n\nThe published sources are \"the first iteration\". They work for me,\nbut I do not provide any warranty. You can use it only on your \nown risk!\n\n===== LICENSING: =====\n\n\nMy kernel driver is released under the GPL license\nMy user space application is public domain\nMy FPGA code is published with BSD license\nThe core kept in FPGA_with_MAC directory includes also very\n slightly modified Ethernet MAC \n http://opencores.org/project,ethernet_tri_mode\n which is published under LGPL. (The core located in the FPGA_no_MAC \n directory does not use MAC core, the Ethernet PHY is controlled directly\n by simple state machines.)\nDue to licensing issues I can include only xco files for blocks\n generated by Xilinx tools\n\n\n===== REBUILDING of FPGA CORES =====\n\nMy sources have been tested with three boards: SP601, Atlys and\nSpartan-3E Starter Kit. In the FPGA_with_MAC and FPGA_no_MAC\nsubdirectories there are\nthree subdirectories: sp601, atlys and sk3e. In each of those\nsubdirectories there is the \"build.sh\" script, which\nshould recreate the .bit file needed to configure particular\nboard.\n\n===== EXPERIMENTAL \"JUMBO FRAMES\" BASED IMPLEMENTATION FOR 1Gb/s and 10GB/s LINKS =====\n\nIn the directory experimental_jumbo_frames_version you can find\nthe experimental version of my protocol, working with the 10Gb/s link on the \nKC705 board and with 1Gb/s link on the Atlys board.\nIt uses longer \"jumbo frames\" with 8192 bytes of user data to transmit\ndata from the FPGA.\nThe high speed operation has exposed serious disadvantages of the previous\nimplementation. E.g. the concept of \"sets\" of packets has been dropped,\nand instead packets are sequentially (modulo 2^32) numbered in the data\nstream.\nAdditionally a possibility to send user defined commands (16-bit command\ncode, 32-bit command argument, 12-bytes return value (with 8 bytes defined\nby the user)) to the FPGA.\nThe design has been initially tested, and is working, but it still\nneeds some improvements.\nAfter the cleanup, this approach will be ported also to the version\nworking with standard frames." language: VHDL license: multiple maintainers: - wzab name: fade_ether_protocol status: FPGA proven svn-updated: Feb 1, 2015 updated: Oct 5, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jul 22, 2002 description: "===== \n Description =====\n\nA 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.) \n\nThe generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35Micron standard CMOS process using the properties of Galois Fields and has been conceived as a \"free\" IP. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- 5 independent channels @ 4Gbps each\n- Works (simulations) with a standard AMS 0.35Micron process\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Ready to use." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - trueno name: fast-crc status: ASIC proven svn-updated: Mar 10, 2009 updated: Aug 8, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Aug 8, 2010 description: "===== \n Description =====\n\nA fast (single-cycle) base-2 antilog function.\n\nNeed an electronic design solution? Visit http://www.cantares.on.ca/\n\nDoesn't run quite as fast as my Log code: 166MHz, vs. 250MHz for the log. Registering the input would bring that up. Takes about the same resources as the log.\n\nTo do a single-cycle square-root, first take the log. Then, divide that result by 2 (shift), and take the antilog. Tada... \n\nIf you use this, please write and tell me about it!" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelDunnCantares name: fast_antilog status: Stable svn-updated: Aug 8, 2010 updated: Jan 28, 2011 wishbone-compliant: 0 - category: DSP core created: Feb 26, 2015 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Vampailleur name: fast_generic_iir_filter status: Empty updated: Feb 26, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Oct 10, 2009 description: "===== \n Description =====\n\nA fast (single-cycle) base-2 log function, based on the description at http://www.cantares.on.ca/extras.html\n\nNeed an electronic design solution? Visit http://www.cantares.on.ca/\n\nFirst uploaded version is in Verilog, with pipelining to maximize the clock frequency. An example implementation: It takes less than 2% of the smallest CycloneIII, and runs at 250MHz on the IOs. Probably even higher if internal-only. It even fits in a mid-sized CPLD!\n\nSecond version strips outs the pipelining registers. Simpler if you don't need the throughput. This one clocks in at 14ns propagation delay pin-pin on the same CycloneIII. Not a bad speed for a logarithm, right? :-) (BTW, the syntax here requires System Verilog)\n\nThe third version is similar to the first, except the fractional LUT has been expanded for higher accuracy and resolution.\n\nIf you use any of these, please write and tell me about it!\n\np.s., check out my antilog project too - combine them for square-root" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelDunnCantares name: fast_log status: Stable svn-updated: Aug 3, 2010 updated: Jan 28, 2011 wishbone-compliant: 0 - category: Video controller created: Feb 16, 2007 description: "===== \n Connecting to the world outside =====\n\nThis part was completely redesigned due to variant output inpedances of different CPLD/FPGA and to reduce the moving pattern from older versions.\nThe two transistors are used for impedance transformation so the output inpedance has not more much effect\nto the result. In the upper part the luminance signal is generated and in the lower part the chrominance\nsignal. The two 1,2KOhm resistors on fbh and fbl pin sets the chrominance output to\na defined level. The chrominance signal is mixed with the luminace signal by an simple capacitor, this is\nalso used in cheap s-video to FBAS adapters. So this works, it should be easy to create s-video by\nsplitting this connection, but this feature is untested.\n \n\n\n \n \n \n\n===== \n Summary =====\n\nThe design written in VHDL fits in a cheap XC9536 CPLD if only PAL or NTSC signals are generated. \nWalking pattern visible on some TV at older versions of the design are minimized. The design is more easy\nexpandable but by the cost of an increased amount of external hardware. For some cases ther are ready-to-use\njedec files in the jedec folder.\n\nFor a german version have a look at my homepage http://www.jcwolfram.de/projekte/vhdl/main.php\n \n \n\n\n \n \n \n\n===== \n Changelog =====\n\n7.2.2007 the first public version (0.21)\n \n * PAL and version NTSC for 16, 20, 32 and 40 MHz clock frequency\n\n9.3.2007 version (0.31) \n\n * give up the way with a long ROM table in favor of an mixed signal generation\n * a more clearly design and improved image quality\n\n\n \n\n\n \n \n \n\n===== \n Luminance signal generation =====\n\nThe luminance signal generation is the same as generate B/W only signals. It uses a little table to calculate\nthe different levels. This component is located in file luma_gen.vhd. In some cases it is also possible to generate the luminance signal directly by the rgb source without using this component. For example, if your MCU is already generating an BAS signal you can add the chrominance signal in the simple way of a capacitor. \n \n\n\n \n \n \n\n===== \n A simple example =====\n\nTo get a chip, who's working a little bit of additional logic (glue) is necessary. \nThe rgb signals are stored in regsters to get a more synchronous design and to avoid glitches by different\ninput delays. Also 2 threestate outputs for the chrominance-signals (burst and colour) and if needed, a\nclock divider for the CPU/MCU clock. The luminance signal generation is clocked only by the CPU clock because faster clocking has no advantage and provides undesirable noise. \nThe cgsel signal can used as an fourth bit to select one of 8 grey levels or with an external switch. '0' selects\ncolour mode and '1' selects greylevel mode. With the cg\\_pnsel signal it is possible to switch between PAL ('0')\nand NTSC ('1') without any hardware changes. If only PAL or NTSC is needed, feeding this signal with statically '0' or '1' results in decreasing the amount of logic cells. \n\n \n\n\n \n \n \n\n===== \n A little bit of theory =====\n\nThere are many usefull addresses on the Internet and so I only want to tell briefly the most important to know \nabout the PAL system. Horizontal timing and vertical timing are identical to the black and white BAS signal \nas much as possible. The main difference is the colour carrier signal which is used to encode the additional\ninformation.\nTo avoid moires on black'n white pattern the colour carrier has a crooked frequency. \nNamely the horizontal frequency of 15,625 hertz * 283.75 plus the half vertical frequency (25 hertz). \nWith it one comes on 4,433,618.75 hertz. To generate this we can use a quartz oscillator or find a way to use \nthe system clock from teh rgb source (e.g. microcontroller). This can be done by using DDS (Direct Digitally Synthesis) \nand a error of just abovementioned 25 hertz must be accepted, otherwise we need very wide counters to the signal production.\nWith a clock frequency of 16 MHz we need such a counter (accumulator register) with 12-bit width. \nEvery clock the counter adds 1135 (283.75 * 4) and so we get the (approximate) value of the colour carrier.\nWith 20 MHz clock speed this would be theoretical 908, a 10-bit-wide counter should be also enough with addition of 227.\n\nTo identify a colour signal and to synchronise the quartz oscillator in the TV, the normally quadrature-modulated \ncolour carrier will be sent unmodulated shortly after the synchronous impulse for approx. 10 periods. This is named\nas the burst. If burst is sent the phase changes from line to line between -135 and +135 degrees.\nHowever, after my experiences 8 periods are also sufficient. The amplitude of the Bursts amounts to 0,15V exactly 50% \nof the maximum amplitude with maximum colour saturation. For the basic colours a saturation of about 50% is \ncompletely sufficient but its also possible to create a table with another saturation. The FBAS (CVBS) signal consists\nof three signals:\n\n * the luminance signal Y = 0,299*R + 0,587*G + 0,114*B\n * the U colour signal U = 0,493 * (B-Y)\n * the V colour signal U = 0,877 * (R-Y)\n \nThe Y signal will transfer directly, the U and V signals modulates the colour carrier by quadrature-modulation.\nIn brief the U signal is multiplied by the cosinus wave of the colour carrier and the V signal with about\n0 or 180 degrees of the sinus wave of the colour carrier. Besides, the tone is encoded in the phase and the colour\nsaturation in the amplitude of the modulated colour carrier. In the last stage the three signals will be added and \nduring the synchronous impulses it must be set to 0 V. \n \n\n\n \n \n \n\n===== \n History and features =====\n\nAfter some projects of rgb colour video output with AVR microcontrollers there was the question\nabout FBAS (cvbs) signal generation on a simple and easy way. For example, to be able to feed a \nmodulated HF signal into an aerial arrangement.\nBecause a microcontroller is rather inexpedient for it on account of the necessary processing speed,\nthe decision fell in favour of a CPLD. Of course there is for such things also special-IC's,\nbut I did not want to choose this way. As result there is a simple design which also fits in a XC9536 from Xilinx.\nThe encoder components can be also integrated into other designs, provided, the regulations of the LGPL are kept.\n\n * the colour carrier frequency is generated from the system clock of 16 or 20 MHz\n * inputs: hsync, vsync and rgb\n * 8 basic colours / 8 grey steps eligible\n * the same hardware can be used for PAL and NTSC\n\nthe following image shows a \"screenshot\" of a test program. Because of the spectral sensitivity of my digicam the colours which contains blue are brighter as viewed by eyes.\n \n\n\n \n \n \n\n===== \n Timing =====\n\nDue to the complex logic, the timing in chroma-path is a little bit critical and limits clock speed.\nFor correct results for 32MHz a 7ns CPLD is needed, for 40MHz a 5ns one. So fast spikes are filtered\nby lowpassing at the output, a 15ns Device works well in all cases. For better timing more macrocells\n(38-40) are necessary to flatten the design. Another way is to store stages of the chrominance signal\ngeneration in stages (pipelining). This causes in delay between chrominance and luminance signals which\nshould not be visible on TV. Or, the luminance signal must also beeing delayed. For PAL and a little bit\nless of image quality the 16- and 20MHz versions are an good alternative. \n\n \n\n\n \n \n \n\n===== \n Realisation =====\n\nAnd now te big question, how can we fit these functions in a small CPLD. \nThe colour carrier and the Burst signal do the least problems, the modulation and mixture with the Y signal \nis less trivial. After some experiences with long ROM tables including the first official version 0.21 I\ndecided this was not a good way. Poor image quality and the need for an external script were the reasons\nfor searching another way. With the first attempts appeared that it is possible theoretically to generate\na FBAS (CVBS) signal, while rebuild the signal path digitally. But, the logic expenditure is rather high. \nThe new way I've found is to generate chrominance and luminance signals digitally and add them on an\nanalog way after lowpassing. So it's possible to limit the bandwidth of the chrominance and the luminance\nsignals separately.\n \n\n\n \n \n \n\n===== \n IMAGE: chroma_gen.png =====\n\nFILE: chroma_gen.png\nDESCRIPTION: chroma generation component\n\n \n\n\n \n \n \n\n===== \n IMAGE: luma_gen.png =====\n\nFILE: luma_gen.png\nDESCRIPTION: luma generation component\n\n \n\n\n \n \n \n\n===== \n IMAGE: main.png =====\n\nFILE: main.png\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n IMAGE: connect.png =====\n\nFILE: connect.png\nDESCRIPTION: wiring diagram\n\n \n\n\n \n \n \n\n===== \n chrominance signal generation =====\n\nThe DDS synthesis and burst generation are like the older versions, but the signal generation is completely\nredesigned. The component which does this is located in the file chroma\\_gen.vhd.\nThe necessary phase shift is calculated of the 4 MSB of the carrier signal, rgb and burst. The resolution\nis limited to 4 bits resulting in phase steps of 22,5 degrees.\n\n-burst ha a phase of +135 and -135 degrees, equivalent shift vallues are 6 and 10 (16-6)\n-because of V=0 on blue colour the phase shift in this case is 0 deg n odd and even lines.\n-the phase shifts of the other colours can be determined by the colour circle, the value is changing between n and 16-n between the lines.\n-in the case of NTSC generation the phase shift of burst and colour does not alter between the lines \n\nThe necessarey phase shift is been calculated by a little table and was added to the colour carrier\nvalue to get the phase of the modulated carrier. For simplification only the MSB of the addition was\nused to generate a rectangular signal. For black, white and grey levels the chrominance signal is switched\noff, for the burst signal a output to generate a reduced amplitude is activated.\nThis concept is easy expandable to generate more colours in higher phase resolution and/or multiple\ncarrier levels.\nIn the result of problems with XST and configurations (ignored by 7.1) in file main.vhd the component \ndeclaration is followed by the selected architecture. For different clock speeds there are exists 4 architectures, clock16, clock20, clock32 and clock40. \n\nThe testing of the image quality is mostly subjective by using a 5\\\" LCD-TV (the only i can use to thest NTSC). At PAL modes the quality is better than at NTSC modes, but this is more problem of the TV standards. The 16- and 20MHz verions are highly unuseable for NTSC generation because of \\\"blowing\\\" from coloured to non coloured areas in the image. Better lowpassing of the chrominace signal should help but is not tested.\n\n \n\n\n \n \n \n\n===== \n IMAGE: fbas-enc_scrs1.jpg =====\n\nFILE: fbas-enc_scrs1.jpg\nDESCRIPTION:" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - joergwolfram name: fbas_encoder status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Oct 9, 2014 description: "===== \n Moved =====\n\nThis project has moved to: \nvirtex7_pcie_dma" language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: felix_virtex7_pcie_dma status: Empty updated: Jan 9, 2015 wishbone-compliant: 0 - category: Other created: Aug 5, 2003 description: "===== \n Description =====\n\nThe aim of this Core is to track the first file saved \ninto a FAT16 volume and to read the information from it offering those data to a Wishbone bus trough a Wishbone slave interface. The Core has an IDE interface that permits the attachment of devices as Compact Flash (no DMA support). It uses about 300 Xilinx Spartan II slices (if Area optimization is chossen about 285). \n\nInternally it has two Modules that can be used indepently. Both of them are implemented using a Picoblaze Programmable State Machine, using Xilinx BlockRams for instructions. Those modules are: \n\n1 - HOST ATAPI UNIT (HAU): Controls IDE signals and manages the ATAPI protocol for sector reading. For a sector read, it only needs the LBA (Logic Block Address) as input, answering with the words of that sector. This module can be used in embedded systems that do not require any specific FAT format. As the control state machine is implented in \"software\", modifications (write support, for example) are easy to implement. \n\n2 - FAT PROCESSOR UNIT (FAU): It requests to HAU the necessary sectors to track and read the first valid file which has been stored into the IDE device that uses a FAT16 volume. \n \n\n\n \n \n \n\n===== \n IMAGE: FFR16.jpg =====\n\nFILE: FFR16.jpg\nDESCRIPTION: FFR16 internal module division and interfaces\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Small area requeriments.\n- Written in VHDL and in KCPSM assembler.\n- Co-simulation facilities (KCPSM assembler generates VHDL simulable file).\n- Mix & Run in SoPC due to the use of a Wishbone interface is used. Spartan II and 50 Mhz clock\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Design is finished and available in VHDL from OpenCores CVS. \n- Documentation is no still available." language: VHDL license: OHGPL and GPL maintainers: - armando name: ffr16 status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Library created: Feb 16, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Vj84529 name: fft8_processor status: Empty updated: Feb 16, 2013 wishbone-compliant: 0 - category: DSP core created: Feb 1, 2010 description: "===== \n Description =====\n\nFFT-based FIR Filter is a unit to perform the finite impulse responce filter based on the Fast Fourier Transform (FFT). It performs the convolution of the unlimited signal sequence with the synthesized impulse responce of the length of Ni=N/2 samples, where N = 64, 128, 256, 512, 1024. The data and coefficient widths are tunable in the range 8 to 18.\n\n\nMain Features:\n\n\nThe filtering algorithm is the sectioned convolution with accumulating based on N-point radix-2 FFT, where N = 64, 128, 256, 512, 1024\nOne complex signal channel or two parallel real signal channels. \nFilter types are LPF; LPF and HPF; LPF and HPF, and differentiator; LPF and HPF,and double differentiator.\nInput data, output data, and coefficient widths are generics\nBandpass frequencies of the LPF and HPF filters, filter type are dynamically tunable parameters. The frequencies for both real channels are tuned independently\nStop band ripple for 16-bit dates is higher than 60 db. The transitional frequency band is less than 6 bins (1 bin = Fs/N, where Fs is the sampling frequency\nDynamic range for 16-bit dates is higher than 70 db\nStructure optimized for Xilinx Virtex2, Virtex4, Spartan3 FPGA devices, and can be implemented in Altera, Actel, Lattice devices as well.\nThe maximum clock frequency for Virtex4 devices is equal to Fclk = 190 MHz, and for Spartan3E devices is equal to Fclk = 80 MHz. \nThe maximum sampling frequency Fs by N=1024 is less than Fclk/29.\nThe latent delay of the filter by N=1024 is equal to 1790 cycles of Fs.\n\n\nPlease, contact us if you wish to have this IP core modified or adjusted to meet your requirements.\n\n\nThis core is provided by Unicore Systems http://unicore.co.ua. To view our product list of commercial IP cores, please, follow this link" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unicore - aser name: fft_fir_filter status: Stable svn-updated: Feb 2, 2010 updated: Apr 27, 2011 wishbone-compliant: 0 - category: DSP core created: Apr 11, 2007 description: "===== \n Description =====\n\nThe RTL computes Fast Hadamhard Transform of 8-bit input data. The code has been developed using standard FHT algorithm using matrix addition. The code has been functionally verified and also synthesized for Xilinx FPGA.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\n- status1\n- status2" language: Verilog license: unknown maintainers: - kaushal_buch name: fht status: Design done svn-updated: Mar 10, 2009 updated: Dec 18, 2010 wishbone-compliant: 0 - category: Memory core created: Jun 2, 2011 description: "===== \n Description =====\n\nName: First In First Out (FIFO)\n\nSpecification:\n1.\tA FIFO is a list that data is written at the rear of the list but then read from the beginning of the list, with a read is also removing the read data from the list.\n2.\tThis FIFO design is an 8x16 register file where the total address line is 8 and each address line is 16 bits wide.\n3.\tFor writing operation, the first data will be written into register file is at address \xE2\x80\x98waddr\xE2\x80\x99 (R[waddr]\xE2\x86\x90wdata)and then the address will be incremented by one so that the next data coming will be written at waddr+1 (R[waddr+1]\xE2\x86\x90wdata) . Since the total address line is 8, so the address will be incremented only up to 8 and then it will wrap around to 0.\n4.\tFor reading operation, the first data that will be read is at address \xE2\x80\x98raddr\xE2\x80\x99 (rdata\xE2\x86\x90 R[raddr]), and then the address will be incremented by one so that the next data that will be read is coming from address \xE2\x80\x98raddr+1\xE2\x80\x99 (rdata\xE2\x86\x90 R[raddr+]). Same thing happened to address for reading, it will only incremented up to 8 and then it will wrap around to 0.\n5.\tAfter writing or reading operation is performed, the counter value for both writing address (waddr) and reading address (raddr) is compared either the counter value is equal or not. If writing operation is performed and then if waddr == raddr means the FIFO is FULL. If reading operation is performed and then waddr == raddr means the FIFO is empty. These two conditions are always updated after each operation is performed for both writing and reading.\n6.\tNoticed that for this FIFO design, write and read operation cannot be handled at the same time even the reading and writing operations are at different addresses.\n7.\tAs a result, the conditions detecting the queue being full and the queue being empty are depends on what operation is performed first before checking which is either writing first or reading first." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - muzabyte name: fifo status: Empty updated: Jun 3, 2011 wishbone-compliant: 0 - category: Memory core created: Mar 20, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - aTomek132888 name: fifo_srl_uni status: Stable svn-updated: Mar 21, 2010 updated: Apr 19, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Nov 30, 2007 description: "===== \n Description =====\n\nDescription of project.." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: filter status: Empty updated: Nov 4, 2010 wishbone-compliant: 0 - category: DSP core created: Apr 12, 2012 description: "===== \n Specifications =====\n\n- as much as 256 TAPs in Xilinx Virtex/Spartan2 (per cascade unit) \n- low gate count (on expense of lower input sample frequency range) with a single MAC unit per core and sequential calculation of output samples (TAPs don't operate in parallel) \n- 2 to 256 TAPs range set by a user \n- 16 bit or less input sample width set by a user \n- 16 bit or less coefficient width set by a user \n- simple design that allows cascading several FIR filter cores (external adder required) \n \n\n\n \n \n \n\n===== \n Description =====\n\nFIR, or Finite Impulse Response, filters have the distinctive trait that their impulse response lasts for a finite duration of time as opposed to IIR, or Infinite Impulse Response, filters whose impulse response is infinite in duration. \n \n\n\n \n \n \n\n===== \n IMAGE: typical_tap.gif =====\n\nFILE: typical_tap.gif\nDESCRIPTION: Typical block diagram of a TAP unit in typical FIR filters\n\n \n\n\n \n \n \n\n===== =====\n\nCurrently FIR filter core uses two dual-port memories for accessing input samples (first circular FIFO) and coefficients (second circular FIFO). It takes NUM_TAPS+1 to compute new output sample. Supported DP memory is of Xilinx Virtex/Spartan2 FPGAs. Also a generic DP memory is provided (it synthesizes into flip-flops). \n\n \n\n\n \n \n \n\n===== \n IMAGE: fir_block.gif =====\n\nFILE: fir_block.gif\nDESCRIPTION: Block diagram of our \"sequential\" FIR filter core\n\n \n\n\n \n \n \n\n===== \n Synthesis =====\n\n- Synthesized with Xilinx Foundation 2.1i (Synopsys Express FPGA compiler, Xilinx P&R tools) for Xilinx Virtex -6 FPGA design takes 229 Virtex slices and 2 BlockRAMs and operates at 55MHz (12 TAPs, 16 bit coefficients and input samples, +-2.29 input sample frequency). \n \n\n\n \n \n \n\n===== \n Status =====\n\n- design is available in VHDL from OpenCores CVS (see Downloads)\n- documentation will be written if enough interest (or if there will be a volunteer to do this) \n- also see TO DO list in design's VHDL sources \n \n\n\n \n \n \n\n===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lampret name: fir status: Empty updated: Sep 2, 2014 wishbone-compliant: 0 - category: DSP core created: Mar 22, 2013 description: "===== \n Description =====\n\nVHDL Parametrizable FIR Filter\n\nImplementation:\n\n-Direct Form II\n-Real format entry for normalized coeficients\n-Internal fixed-point implementation (configurable resolution)\n\nSimulation:\n\n-Matlab file (.m) \n-VHDL testbench and macro (.do) for simulation\n\n===========================================================\n EXAMPLE\n===========================================================\n\nduv_FIR_low_area : ENTITY WORK.FIR_low_area\n\nGENERIC MAP( \n..data_length...=>..12,....-- input/output length \n..data_signed...=>..true,..-- input/output type (signed or unsigned)\n..improv_t........=>..false,.-- minimal timing improvement (+1 cycle delay) \n..bits_resol.......=>..16,....-- bits for decimal representation of coeffients\n..taps..............=>..5,.....-- order+1, 2 taps (coefficients) as minimum \n..coefficients....=>..(.......-- normalized coefficients (bo,b1, ..., bN)\n............................-0.11735685282030676,\n.............................0.23471370564061372,\n.............................0.7066280917835991,\n.............................0.23471370564061372,\n............................-0.11735685282030676,\n.............................OTHERS=>0.0)....-- (always end with \"others=>0.0\")\n\nPORT MAP(\n..areset.....=>..areset,..-- active high \n..sreset.....=>..'0',.......-- active high \n..clock_fs..=>..CLK, \n..enable....=>..'1', \n..xn..........=>..input,....-- FILTER INPUT (fixed-point or whole number)\n..yn..........=>..output...-- FILTER OUTPUT (keeps same format as input)\n );\n\n\nENJOY!!!" language: VHDL license: unknown maintainers: - arroxo2 name: fir_filter status: FPGA proven svn-updated: Apr 12, 2015 updated: Apr 13, 2015 wishbone-compliant: 0 - category: DSP core created: Dec 29, 2005 description: "===== \n Description =====\n\nVHDL core generator\n\nFIRGEN Project generates optimized VHDL codes for FIR Filters and Multiplier arrays\nusing \"Nonrecursive Signed Common Subexpression Algorithm\".\n\nprogram writen on C++\n--------------------------\nfirgen [OPTION..]\nAvailable options are :\n-w Input Data Width\n-m Generate Only Multipliers Array\n-a Generate Asynchronus Multipliers array (no CLK signal)\n-e Use CLK_EN input\n-c filter coefficients, coma separated\n-o Output File Name\n-? Help\n\nExample For Use:\n----------------\nFirGen -w 16 -c 1,2,3,4,5 -o my_fir\n\nthis command generates 2 output files\nmy_fir.vhd - Main Fir module\nmy_fir_mult.vhd - Multipliers Array (DIn*C1, DIn*C2,..., DIn*Cn)\n\nInput data width is 16 bit\nFilter Coefitions : 1,2,3,4,5\n \n\n\n \n \n \n\n===== \n Features =====\n\nFIR Filter Generator\nMultiplyer Array Generator with common input\n \n\n\n \n \n \n\n===== \n Status =====\n\nStable and ready for use Ver1.1\nAsynchronus operation\nand CLK_En features added\n\n------------------------------------------------------------------\nDownload URL:\nhttp://www.opencores.org/pdownloads.cgi/list/fir_filter_generator\n\n------------------------------------------------------------------\nnote : May be you will need to install cygwin from www.cygwin.com to be able\n run this program." language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - borisk name: fir_filter_generator status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: DSP core created: Sep 10, 2013 description: "===== \n Description =====\n\nThis FIR filter is very generic and flexible. It has been tested working on an FPGA, though the existing version does not yet have a Wishbone control interface. I will be adding one to it soon. Stay tuned!" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: fir_wishbone status: FPGA proven svn-updated: Mar 30, 2015 updated: Mar 4, 2014 wishbone-compliant: 1 - category: Communication controller created: Sep 25, 2001 description: "===== \n Description =====\n\n*NOTE* This project is currently unmaintained and uncompleted. If you would like to take over this project please contact the current maintainer Kris Bahnsen.\n\n\n\nFireWire, Apple's implementation of IEEE 1394 protocol, is a high performance serial bus protocol to provide easy-to-use, low-cost, high-speed communications. Click here for a good collection of links to IEEE 1394 documents. \n\nThe goals of the FireWire project is to provide IEEE 1394 and IEEE 1394a-2000 compliant Link Layer cores: Link core and Host Controller core. The project will also include firmware for Transaction Layer and Serial Bus Management Layer.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Developing test bench/test plan for the link controller\n- RTL coding in Verilog\n- Revising \"Link Core Specification\"\n- 03/03/2002: Checked in the link request block verilog file link_req.v 1.1\n- 11/11/2001: Checked in \"Link Core Specification Rev 0.1\"\n- 25/10/2001: Finished reading FireWire related specs and datasheets.\n- 30/06/2001: Released initial FireWire homepage. \n \n\n\n \n \n \n\n===== \n Project plan =====\n\n- FireWire homepage setup \n- FireWire protocol research\n- FireWire specification documentation \n- RTL coding in Verilog \n- Test bench development and verification \n- Synthesis and P&R targeting Altera and Xilinx FPGA's \n- Timing verification \n- FireWire cores validation on hardware if possible \n- FireWire cores release" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - johnsonw10 - l33tbunni name: firewire status: Planning svn-updated: Mar 10, 2009 updated: May 3, 2015 wishbone-compliant: 1 - category: Arithmetic core created: Nov 21, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: unknown maintainers: - rajenderbaddam name: firfilter status: Empty updated: Nov 21, 2013 wishbone-compliant: 0 - category: Memory core created: Mar 30, 2013 description: "===== \n Description =====\n\nFifo Design to use Gray pointer\n\nIntroduction Fist Revision Design \n1)\tFifo verilog design code to use read gray pointer and write gray pointer\n2)\tAdder verilog code to use 1\xE2\x80\x99s complement and 2\xE2\x80\x99s complement,it is used to increment or decrement read pointer or write pointer.\n3)\tFull Adder verilog code to add fully two 32 bits operands.\n4)\tBin2Gray verilog code to convert Binary Code to Gray Code.\n5)\tGenerate Full and Empty Signals.\n\nSecond Revision Design as follows (6~10)\n6) Circular Queue Fifo design code to use read gray register, write gray register, data gray register.\n7) Gray Counter Up/Down(or Adder/Subtractor) doesn't use complement.\n8) Gray2Bin convertion module uses to calcualte data count to remain in Fifo now.\n9) Full and Empty Signals use to display Fifo status.\n10) Gray Counter Resouce Sharing is to reduce Gray Counter logic just one.\n\nreference> Altera Web Site Gray Counter Verilog Source,\n Verilog Designer's Library,\n Advanced Digital Design with Verilog HDL,\n Digital Design (mano)\n\nQuestions of my Fifo to my emails : hotak321@naver.com \nThanks to all of you !!!" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hotak321 name: fito_to_use_gray_pointers status: Empty updated: Dec 8, 2013 wishbone-compliant: 0 - category: Library created: Sep 9, 2011 description: "===== \n Description =====\n\nfixed_extensions_pkg is a fixed-point arithmetic package written in VHDL \naccording to the VHDL-2008 update of the standard. It uses VHDL-2008 back-\ncompatible libraries (by David Bishop) that are included in this distribution \nfor the sake of completeness.\n\nCurrently, the \"fixed_extensions_pkg\" package implements the following:\n\n-ceil:\n round towards plus infinity.\n-fix: \n round towards zero.\n-floor:\n round towards minus infinity.\n-round: \n round to nearest; ties to greatest absolute value.\n-nearest:\n round to nearest; ties to plus infinity.\n-convergent: \n round to nearest; ties to closest even.\n-bitinsert: \n bit-field insertion to word\n-bitextract: \n bit-field extraction from word\n\nfixed_extensions is distributed along with a tool (gentestround) to generate \ncustomized VHDL test designs." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - kavi name: fixed_extensions status: Beta svn-updated: Feb 20, 2014 updated: Feb 20, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Aug 25, 2011 description: "===== \n Description =====\n\nThis project was started in order to create fixed point (Q format) arithmetic modules in verilog.\n\nWhat was created was a parameterized (specify size (N) and number of fractional bits (Q)) implementation to make configuring for different projects simple.\n\nThis implementation uses the following data structure:\n\n| sign (0+/1-) | whole number | fractional bits |\n| ____1 bit___ | _N-Q-1 bits_ | _____Q bits____ |\n\nThe following modules were created:\n-Twos Complement\n-Addition (Combinational)\n-Multiplication (Combinational using standard * operator)\n-Division (Clocked, standard binary division)\n\nEach of these modules is accompanied by a testfixture, and each has been tested for minimal functionality\n\nNOTE: Division's testfixture (qdiv_tf.v) contains 2 tasks that convert between verilog real and fixed point representations (including checking for numbers too big to represent and loss of precision).\n \n\n\n \n \n \n\n===== \n SVN Files =====\n\nThe source files in the SVN have been separated into three groups:\n\n- src: containing the verilog sources files {qadd.v,qmult.v,qdiv.v,qtwosComp.v}. These are the parameterized verilog modules implementing the fixed point arithmetic\n\n- testfixtures: containing the three testfixtures for each of the arithmetic operations (add,mult,div). These testfixtures show how data is being entered into the data structure from real life (giving understanding to the user in how to implement in their own projects).\n\n- implementation: containing a sample 'top' module that implements the arithmetic operations in a Q23/32bit scenario" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - samis13 name: fixed_point_arithmetic_parameterized status: FPGA proven svn-updated: Apr 10, 2013 updated: Oct 31, 2013 wishbone-compliant: 0 - category: Other created: Mar 29, 2004 description: "===== \n Description =====\n\nThis project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix and inference for it. The input and output data will be 64-bit. Each input and output data will have 8 elements in each universal space, and each degree of membership is a discreet set of 256 members from 0 to 1. For the rule matrix, it can either generate it based on the input data or directly input it to its matrix. When the rule memory has already builded, a master can read the whole matrix from this FLHA. For inference, the output will be based on the input and the rule matrix. This FLHA should be smart enough to tell the master (requester) about its status: done, rule building busy, inference busy, error, etc.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Capable of building and storing fuzzy rules using standard composition rule.\n- Using interpolation method to obtain the inference result.\n- Input and output data will have 8 elements in each universal space, and each degree of membership is a discreet set of 256 members from 0 to 1. Current plan is that fuzzification and defuzzification of data are done by the host (master). I might add defuzzification to the model in the future.\n- Device has to be smart enough to indicate its status, such as done, rule building busy, inference busy, etc, when requested by the host (master).\n- WishBone compliant.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- FLHA's core is done. Simulated on ModelSim XE II 5.7c. Looks fine. Help me to improve, or find any bugs. Thanks.\n- Start to work on the WishBone interconnect." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - songching name: flha status: Beta svn-updated: Mar 10, 2009 updated: Dec 25, 2013 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/fli.zip category: Testing / Verification created: Oct 4, 2013 description: "===== \n Description =====\n\nUsing ModelSim Foreign Language Interface for c - VHDL Co-Simulation and for Simulator Control on Linux x86 Platform\n\nWriting testbenches in VHDL can be very cumbersome. This can be solved by using a programming language with more features that does not need to bother about hardware implementation restrictions. This project demonstrates how plain c can be used for testing. Besides generating Stimuli and Analyze results, optional features, like a control interface and simulation accelerators, have been added to this testbench environment.\n\ncode can be found on\nhttps://github.com/andrepool/fli" homepage: http://github.com/andrepool/fli language: VHDL license: Apache License version 2.0 licenselink: http://opensource.org/licenses/Apache-2.0 maintainers: - andrepool name: fli status: Stable updated: Oct 7, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Feb 16, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Zhangyusdu name: floating_point_multiplier status: Empty updated: Feb 16, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jan 5, 2010 description: "===== \n Description =====\n\nVHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs.\nThe unit is an implementation of the ICSILog algorithm." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - NikosAl name: fp_log status: Stable svn-updated: Dec 21, 2010 updated: Dec 21, 2010 wishbone-compliant: 0 - category: Communication controller created: Jan 14, 2011 description: "===== \n Description =====\n\nFPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a host-software library/API (Java and C++). It enables a host PC to transmit data at 120 Mb/s to XIlinx-based FPGA boards via Ethernet using standard internet protocols (UDP/IP). A custom lightweight connection-oriented protocol guarantees reliability. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports all ICAP functionality. The core also provides an extensible user-channel interface and provides up to 15, 8-bit user-data channels that can be connected to user circuitry (configurable by the user). The host software API supports both Java and C++ and provides high-level functionality for making connections and transmitting data." language: Verilog & VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - peteralieber - jsmonson name: fpga-cf status: Alpha svn-updated: Sep 21, 2011 updated: Aug 18, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Mar 18, 2014 description: "===== \n Description =====\n\nThis implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices. The architecture is based on the research presented in the following paper: http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG6530_RCS_html_dr/outline_W2014/docs/PAPER_REVIEW_dr/2013_dr/GRAD_dr/FPGAbasedMedianFilter.pdf\n\nSorry, but we do not have time to develop a proper architecture document. However the paper presents a brief and at the same time complete description for this implementation design." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - joaocarlos name: fpga-median status: Stable svn-updated: Mar 21, 2014 updated: Mar 21, 2014 wishbone-compliant: 0 - category: System on Chip created: Sep 25, 2001 description: "===== \n Architecture Description =====\n\nField-Programmable Gate Arrays (FPGAs) are flexible and reusable high-density circuits that can be (re)configured by the designer, enabling the VLSI design/validation/ simulation cycle to be performed more quickly and cheaply.\n\nThe flexibility provided by FPGAs cause a substantial performance penalty due to non-specialized circuit design and signal delay through the programmable routing resources, compared do ASIC designs but FPGAs are still 1000 times faster than circuit simulators.\n\nThis core provides plural of high-speed reprogrammable logic. This FPGA has regular structure and consists of three configurable elements: Look-Up-Tables (LUTs), each with 8 inputs and 2 outputs, full 4b adders and Input-Output Cells (IOCs). It logic size is aproximately equal to 1500 Virtex LUTs. The development system offers fully automated logic placement and routing (more about P&R software can be found in FPGA P&R Software document). Every non-adder function is stored in static memory array, called LUT, during programing phase. Also connections are established to match desired schematics. Programing data should be supplied by any external data source, e.g. main memory, disk, processor built.\n\nNOTE: This version does not support multiple FPGA connection, but FPGA design can be easily adopted, connecting status registers in Input Output Logic module. There is also no tristate support.\n\nFull specification Fpga.pdf (84k).\n\nMore information about the WISHBONE SoC and a full specification can be found here. \n \n\n\n \n \n \n\n===== \n Software Description =====\n\nPlacement and routing software is a tool, which automaticaly (or with some user help) distributes given elements, so that they match certain criteria. For FPGA (Field Programmable Gate Array) this criteria usully is limited number of FPGA resources (connections, number of programmable elements, speed of (or part of) circuit, etc). More about resources and their functionality can be found in FPGA Architecture document.\n\nCommand line utility is in development, which performs mapping, placement and routing for specified architecture. Currently it supports two input file types:\n\n- Verilog, GTECH library, technology independent\n- EDIF, technology independent\n\nSince P&R is NP-complete problem, no optimal practical solution for large placement can be found, so we are forced to search for sub-optimal solution.\n\n \n\nKRPAN P&R Software Beta v0.1 is now available for download, but it still needs a lot of work\n\nKRPAN.jar (118k) (Requires Java Runtime Environment v1.2).\n\n.jar files can be run using JRE on command line:\njava -jar KRPAN.jar\n\nJar (code correctness) can be verified using Sun's jarsigner command line utility. OpenCores (self published) certificate is available here\n\nKRPAN P&R software is published under GNU GPL license, available here.\n\nDownload KRPAN P&R API Documentation (javadoc) docs.jar (398k).\n\nComplete KRPAN P&R Java sources sources.jar (133k).\n\nSample Verilog file pwm12_8s.v (30k).\n\nJava programming language was choosed, to allow full portabillity on several platforms and faster development. \nAlso we conjecture that Java will become more supported and used and have more computing potential. Java console applications require 70% to 250% the speed of maximally optimized C programs to calculate same results (only Windows platform was tested, but compilers provided by Sun share same code). It is estimated, for this application, that Java would run 100% slower than matching C program.\n\nKRPAN screenshot after routing phase:\n\n\nPreliminary SW documentation is available here (PDF, 81k)\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nHELP NEEDED - HW developers to develop RTL model. \nP&R software coding started 15th february full source code available when first stable version will be reached - aproximately at end of March HELP NEEDED - more Verilog/Edif examples are needed to test, if you wish to help please contact us first before sending actual files. SUGGESTIONS NEEDED. You can help with architecture design - many things are still open. message will be posted to cores@opencores.org when any significant progress is made. cores@opencores.org is at the same time official mailing list for FPGA project.\n\n \n\n\n \n \n \n\n===== \n Change log =====\n\n- 13/3/2001 MM Initial web page \n- 30/3/2001 MM Added KRPAN v0.1 \n- 5 /4/2001 MM Modifications to architecture, spec updated \n- 20/4/2001 MM first SW spec available, added screen shot" language: Verilog license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - lampret - markom name: fpga status: Planning svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: DSP core created: Aug 12, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - krishnaraj916 name: fpga_based_concurrent_multi-function_generator status: Empty updated: Aug 12, 2014 wishbone-compliant: 0 - category: Other created: Jan 7, 2007 description: "===== \n Description =====\n\nConfigure Altera and Xilinx FPGAs using a small low cost micro-controller and commodity SD/MMC/SPI flash memory.\n\nThere are already solutions available that use a CPLD and SD/MMC/SPI flash memory, but this scheme uses a very small C8051 micro-controller in place of the CPLD, and this has several advantages.\n1. Smaller. C8051 is available in a 4mm x 4mm package.\n2. Very few additional components. eg C8051 has internal oscillator.\n3. Less programming headers. Only one small header required.\n4. A local microprocessor can be connected to the C8051 UART port, and program the flash memory using a few simple commands.\n\nDownloads configuration files at 2Mbps. For example a Cyclone EP1C20 can be configured in under 2 seconds. \n\nThe total solution is very compact requiring only 2 ICs, 1 programming header, 1 resistor, and 2 capacitors.\n\nTo program the SD/MMC/SPI flash memory on your target hardware, you can purchase the Base2Designs USB2Flash programming adapter (http://www.base2designs-store.com).\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Low cost.\n - Customer can upgrade hardware by replacing SD card.\n - Wide choice of flash memory manufacturers.\n - Large flash memory capacity.\n - Flash memory can be used to store large software images.\n - Fail safe in field re-programming.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nRelease 1.0 available. Tested with Altera and Xilinx FPGAs. Download from http://www.opencores.org/pdownloads.cgi/list/fpgaconfig\nIf there is enough interest I will port the C8051 firmware to a USB capable microcontroller. This would allow end customers to upgrade their hardware directly from a PC.\n\n \n\n\n \n \n \n\n===== \n IMAGE: fpgaConfig_system_block_diag.gif =====\n\nFILE: fpgaConfig_system_block_diag.gif\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n IMAGE: altera_config.png =====\n\nFILE: altera_config.png\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n News =====\n\nSee fpgaConfig used in a complete project at:\nhttp://opencores.org/project,openriscdevboard" language: Other license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - sfielding name: fpgaconfig status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Nov 5, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - ulped name: fpgo status: Empty updated: Nov 5, 2014 wishbone-compliant: 0 - category: Coprocessor created: Sep 25, 2001 description: "===== \n Description =====\n\nThis is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions. It supports four rounding modes: Round to Nearest Even, Round to Zero, Round to +INF and Round to -INF. \n\nThere is now also a separate FP compare unit. It is located in the fpu/fcmp directory. \n \n\n\n \n \n \n\n===== \n Motivation =====\n\n- A 100% IEEE 754 compliant Floating Point Unit \n- Usable by the OR1K CPU \n- Options to extend the core \n- Free !\n \n\n\n \n \n \n\n===== \n Compatibility =====\n\nTo the best of my knowledge the FPU is 100% IEEE 754 compliant. I have run over 14Mil. test vectors on it, that where generated using the SoftFloat library by John R. Hauser, which can be found at: http://www.jhauser.us/arithmetic/SoftFloat.html. \nThe test pattern generator is included with the distribution. \n\n \n\n\n \n \n \n\n===== \n Performance =====\n\n- Single cycle execution \n- 4 stage pipeline\n \n\n\n \n \n \n\n===== \n Implementing the core =====\n\nIt is very difficult to partition such a complex piece of hardware for optimal pipe lining. Therefore you will need a synthesis tool that has a \"retiring\" feature to obtain best results. \n\nActual Add/Sub, Multiply and Divide cores must be replaced in the primitives.v file, or your synthesis tool must be able to synthesize them for you. I might fix this in the future. \n \n\n\n \n \n \n\n===== \n Status =====\n\n- Second version of the core is released. Included with the release is also a test bench and a test pattern generator. \n- I won't be doing any more work on the core in the near future, except for bug fixes. \n- The core can be downloaded from OpenCores CVS via cvsweb or via cvsget (use fpu for module name) \n \n \n\n\n \n \n \n\n===== \n Things that need to be done =====\n\n- Add a remainder function \n- Predict leading zeros to improve performance of post normalize unit \n \n\n\n \n \n \n\n===== \n Change log =====\n\n- 9/16/00 RU Added FP compare unit \n- 9/15/00 RU Added int to float and float to int conversion \n- 9/15/00 RU Fixed documentation \n- 9/13/200 RU Initial release \n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: fpu status: Stable svn-updated: Mar 10, 2009 updated: Sep 2, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jan 28, 2006 description: "===== \n Description =====\n\nThis is a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- FPU supports the following arithmetic operations:\n -\tAdd\n -\tSubtract\n -\tMultiply\n -\tDivide\n -\tSquare Root\n\n- For each operation the following rounding modes are supported:\n -\tRound to nearest even\n -\tRound to zero\n -\tRound up\n -\tRound down\n\n- Pipelined to achieve high operating frequency (100MHz with Cyclone EP1C6)\n\n- Tested with 2 million test cases\n\n- Hardware proven: FPU was implemented in a Cyclone I\xE2\x80\x93EP1C6 FPGA chip and was then connected to the Java processor JOP(http://www.jopdesign.com (jopdesign.com)) to do some floating-point calculations.\n\n\nFor more details please read the documentation. If that doesn't help, then post your question here: http://groups.yahoo.com/group/32bit_fpu/\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 30-Jan-2006: Uploaded project (files will be imported into CVS very soon)\n- 02-Mar-2006: Added CVS files\n- 28-Mar-2006: Tested the FPU with 2 million test cases and corrected two bugs. [fpu_v14]\n- 28-Mai-2006: 1)Intializing bug fixed in testbench; 2)Extended 1 clock cycle more for multiplication, becasue of an Intializing issue.[fpu_v15]\n- 14-Jun-2006: 1)Corrected a syntax error in \"tb_fpu.vhd\": start_i - 16-Jul-2006: 1)Corrected bug related to adding two denormalized operands.[fpu_v17]\n- 22-Jul-2006: 1)post_norm_addsub.vhd: Restructured and fixed a bug; 2)fpu.vhd: Altered add/sub COUNT; 3)tb_fpu.vhd: Added some boundary values. [fpu_v18]\n- 26-Apr-2007: 1)A minor bug was found and corrected when the serial multiplier is used (thanks to Chris Basson!). [fpu_v19]\n \n\n\n \n \n \n\n===== \n License =====\n\nYou can use this code academically, commercially, etc. for free; just acknowledge the author." language: VHDL license: custom licensetext: "This source file may be used and distributed without \nrestriction provided that this copyright statement is not \nremoved from the file and that any derivative work contains \nthe original copyright notice and the associated disclaimer.\n \n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY \nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED \nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS \nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR \nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, \nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE \nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR \nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF \nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT \nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE \nPOSSIBILITY OF SUCH DAMAGE. \n" maintainers: - jidan name: fpu100 status: FPGA proven svn-updated: Mar 10, 2009 updated: Sep 9, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jan 16, 2009 description: "===== \n Description =====\n\nIEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4 rounding modes (nearest, 0, +inf, -inf). This unit also supports denormalized numbers, which is rare because most floating point units treat denormalized numbers as zero. The unit can run at clock frequencies up to 185 MHz for a Virtex5 target device.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- The unit is designed to be synchronous to one global clock. All registers are updated on the rising edge of the clock.\n- All registers can be reset with one global reset.\n- The multiply operation is broken up to take advantage of the 25 x 18 multiply blocks in the Virtex5 DSP48E slices. The 25 x 18 multiply twos complement block will perform a 24 x 17 unsigned multiply, so it takes 9 DSP48E slices to perform the 53 x 53 bit multiply required to multiply two double-precision floating point numbers.\n- fpu_double.v is the top-level module. The input signals are:\n- 1) clk\n- 2) rst\n- 3) enable\n- 4) rmode (rounding mode)\n- 5) fpu_op (operation code)\n- 6) opa (64-bit floating point number)\n- 7) opb (64-bit floating point number)\n\n- The output signals are:\n- 1) out (64-bit floating point output)\n- 2) ready (goes high when the output is ready)\n- 3) underflow\n- 4) overflow\n- 5) inexact\n- 6) exception\n- 7) invalid\n\n- Each operation takes the following amount of clock cycles to complete:\n- 1.\taddition : \t\t 20 clock cycles\n- 2.\tsubtraction: \t\t21 clock cycles\n- 3.\tmultiplication: \t 24 clock cycles\n- 4.\tdivision:\t\t 71 clock cycles\n\n- This is longer than some floating point units, but the support for denormalized numbers requires several more logic levels and a longer latency.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- version 1" language: VHDL license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - davidklun name: fpu_double status: Design done svn-updated: Feb 13, 2010 updated: Oct 11, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jun 18, 2004 description: "===== \n Description =====\n\nThis Floating Point units were developed as part of the HAVOC project. The Design schematics and related files can be browsed at the FPU repository, or downloaded as a separate file from the FP units home page.\n\nThe FP Adder is a single-precision, IEEE-754 compilant, signed adder/substractor. It includes both single-cycle and 6-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 385 CLBs and with a theoretical maximum operating frecuency of 6MHz for the single-cycle design and 87MHz for the pipelined design. The design was tested at 33MHz.\n\nThe FP Multiplier is a single-precision, IEEE-754 compilant, signed multiplier. It includes both single-cycle and 4-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 119 CLBs and with a theoretical maximum operating frecuency of 8MHz for the single-cycle design and 90MHz for the pipelined design. The design was tested at 33MHz.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- IEEE-754 compilant\n- 32 bits, single precision\n- Works with normalized and unnormalized numbers\n- Simple block design, good for FP arithmetic learning\n- Adder\n - 385 CLBs\n - 87 MHz, 6-stage pipelined\n- Multiplier\n - 119 CLBs\n - 90 MHz, 4-stage pipelined\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Initial Release made available in June, 2004. Uploaded in November 2004.\n- Updated in July 2006. Removed references to the HAVOC library, now using the default work. Corrected bug handling the underflow in the multiplier (thanks to H. Sakman for reporting the bug).\n- Updated in June 2010. Fixed a bug in the normalization when the add of two normal numbers produced a denormal, they where not properly represented. Many thanks to Math Verstraelen for reporting this bug.\n \n\n\n \n \n \n\n===== \n Home Page =====\n\nhttp://speech.mty.itesm.mx/~gmarcus/FPU/FPU.html" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - gmarcus name: fpuvhdl status: FPGA proven svn-updated: Jun 21, 2010 updated: Feb 23, 2012 wishbone-compliant: 0 - category: Other created: May 9, 2010 description: "===== \n Usage and Operation =====\n\nIn order to operate the circuit correctly it must first be reset (asynchronously). \nBelow is a timing diagram that illustrates the reset pulse timing requirements.\n\nNote: the circuit only needs to be reset once to operate properly. Every time the divide factor N changes, the circuit automatically resets itself.\n\n \n\n\n \n \n \n\n===== \n Specifications =====\n\nThe adjustable frequency divider is designed in two parts:\n\n\nEven Divider\nWhen the input signal 'N' is set to an even number the even divider is used because the output will be synchronized with the rising edges of the input clock. The even divider has a much simpler architecture consisting of basically cascaded flip-flops.\nOdd Divider\nWhen 'N' is odd the output needs to be synchronized with both the rising and falling edges of the input clock in order to achieve a 50% duty cycle output. The odd divider is much more complex than the even divider and requires two internal counters that are offset from each other." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - joecrop name: freq_div status: ASIC proven svn-updated: Jul 23, 2010 updated: Mar 3, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Sep 13, 2014 description: "===== \n Description =====\n\nclk=input clock 1Mhz\nfi=input Frequency\nfo=output Frequency In Unit Hertz" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - majidma3000 name: frequencymeter status: Empty updated: Oct 5, 2014 wishbone-compliant: 1 - category: DSP core created: Dec 19, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: fsk_transceiver_with_iir_filter status: Empty updated: Dec 24, 2010 wishbone-compliant: 0 - category: Communication controller created: Jul 7, 2010 description: "===== \n Description =====\n\nThe FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC.\nThis core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode.\nData rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput.\n\nFor more information see FTDI's appnote \"AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf\"\n\nIncluded: VHDL core, NIOS test application, PC test application" language: VHDL license: unknown maintainers: - wes314 name: ft2232hcore status: Stable svn-updated: Jul 8, 2010 updated: Mar 8, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Dec 9, 2014 description: "===== \n Description =====\n\nFT816 floating point accelerator consists of two ninety-six bit floating point accumulators between which floating point or fixed point operations occur. Basic operations include ADD, SUB, MUL, DIV, FIX2FLT, FLT2FIX, SWAP, NEG and ABS. The floating point accumulators operate as a memory mapped device placed by default between $FEA200 and $FEA2FF. The floating point accelerator communicates through a byte wide data port and twenty-four bit address port. It was intended for use primarily with smaller byte oriented cpu\xE2\x80\x99s like the 65xx, 68xx series in order to provide them with some floating point capability." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: ft816float status: Alpha svn-updated: Dec 9, 2014 updated: Dec 9, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jul 31, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gookyi name: fulladder status: Empty updated: Aug 1, 2014 wishbone-compliant: 0 - category: Library created: Sep 27, 2011 description: "===== \n Description =====\n\nFunbase project focuses on FPGA-based embedded product development. Immediate drivers are customer driven, networked development and design effort saving methods. Special goal is to make FPGA technology accessible to SW engineers without special HW experience. The project has a web page http://funbase.cs.tut.fi but the IP components will be hosted by OpenCores." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - funbase - lanttu - ttybot - siwastaja - ase - kamppia name: funbase_ip_library status: Planning svn-updated: Jun 17, 2013 updated: May 8, 2012 wishbone-compliant: 0 - category: Other created: Oct 29, 2013 description: "===== \n Description =====\n\nG.729A codec core performs encoding and decoding of 16-bit LPCM audio samples according to ITU-T G.729A standard. The codec core supports multiple channel operations in half-duplex and full-duplex modes." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - madsilicon name: g729a_codec status: FPGA proven svn-updated: Feb 15, 2014 updated: Nov 17, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Aug 9, 2013 description: "===== \n Description =====\n\nThis project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation & synchronisation, CRC computations, scrambling & descrambling, cryptography, etc. This design is very generic / parameterisable, in the sense that it is intelligent enough to be able to \"create\" (or generate) the LFSR structure based on user input (a VHDL generic). In the lfsr entity (galois-lfsr.vhdl), there is a generic named taps, which allows you to input a vector of tap locations for the LFSR.\n\n\n\n\n\n\nFor example, to create an LFSR with a polynomial of x^8 + x^2 + x + 1, all you have to do is specify a tap vector of (0,1,2,8), i.e. register outputs 0, 1, 2, and 8 are tapped. After specifying the tap vector with the correct tap locations, simply map the vector to the LFSR instance, as follows:\n\n\t/* user.vhdl example file. */\n\ti_lfsr: entity work.lfsr(rtl) generic map(\n\t\ttaps => (\n\t\t\t/* Specify the tap vector here. */\n\t\t\t0|1|2|8=>true,\n\t\t\t7 downto 3=>false\n\t\t)\n\t)\n\tport map(...);\n\n\n\n\n\n\n\nNote that the design assumes the largest tap location is fed back to all the previous taps, by means of connecting to the inputs of each XOR gate of previous taps.\n\n\n\n\n\n\nTo simulate the design with Mentor Graphics Questa/ModelSim, simply cd into the testbench/questa folder, and execute simulate.sh from the Unix prompt:\n\n$ ./simulate.sh\n\n\n\n\n\n\n\nIf you have ModelSim/QuestaSim installed, the GUI will appear immediately after you run the script.\n\n\n\n\n\n\nCurrently, we provide only the simulation script for Linux/Unix. Contact us if you need help with simulating this project on Windows, and we will send you separate instructions.\n\n\n\n\n\n\nIf you are using any other simulator, do let us know how this core works with your tool. One of the goals of this project is to make this core as vendor independent as possible.\n\n\n\n\n\n\nThis design synthesises in Quartus. In the coming weeks, we will be verifying this core on hardware. We also have plans to verify on Xilinx FPGAs. Stay tuned for updates.\n\n\n\n\n\n\n\nNote that although you set the VHDL-2008 option in Quartus, it doesn't yet support boolean_vector and integer_vector. So we need to add these definitions for synthesis. You can find them in a separate file (packages/pkg-types.vhdl):\n\n\ttype boolean_vector is array(natural range <>) of boolean;\n\ttype integer_vector is array(natural range <>) of integer;\n\n\n\n\n\n\nThese VHDL-2008 additions are very useful, so request your tool vendor for this support, if they haven't already.\n\n\n\n\n\nFor comments or feedback relating to this core, or if you wish to contribute to this project in any way, feel free to drop us an email (given below).\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n[29-Jul-2013]: Design completed.\n[8-Aug-2013]: Basic functional simulations completed; synthesis done (Quartus).\n \n\n\n \n \n \n\n===== \n To Do =====\n\n- More comprehensive testbench.\n- Make the design Wishbone-compliant.\n- Documentation.\n \n\n\n \n \n \n\n===== \n Contact Us =====\n\nWe offer training, design services, and consultancy in VHDL-based FPGA / ASIC designs.\n\nTauhop Solutions - Penang, Malaysia\nsite: http://www.tauhop.com\nemail: info@tauhop.com\ntel.: +60-16-333-0498 (daniel)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: galois_lfsr status: FPGA proven svn-updated: Mar 4, 2014 updated: Mar 4, 2014 wishbone-compliant: 0 - category: Communication controller created: Oct 5, 2004 description: "===== \n Download =====\n\nThe latest release of the Gamepads project is version 0.3 BETA.\n\n\n\n\nGet this and all previous versions of the design files from SVN: Download repository.\n\n\n\n\nPlease keep in mind that trunk/ is work in progress and might contain smaller or bigger problems.\n\n\n\n\nYou should also check the Tracker for known bugs and see if they affect your work.\n\n\n\n \n\n\n \n \n \n\n===== \n Tools =====\n\nThe following tools are integrated and are required for this project:\n\n\n\nThe GHDL simulator\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis project contains a collection of cores that interface with various gamepads.\n\n\n\n\n\nEach gamepad type has a dedicated controller core which handles the communication with one or more pads of the same type. The status of the buttons together with information about the pad axes is provided by a simple interface.\nSystems integrating such a core can monitor this interface via general purpose IO lines.\n\n\n\n \n\n\n \n \n \n\n===== \n Available Gamepad Controllers =====\n\nCurrently available gamepad controlles are\n\n\n\nGCpad - connects to a Nintendo Gamecube controller\nSNESpad - connects to one or more gamepads of the Super Nintendo Entertainment System\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe project has beta status. This means that not all cores and features have been used under all possible conditions.\nThe SNESpad and the basic flavor of the GCpad are heavily used in several FPGA implementations. The full flavor of GCpad is only verified inside the core's testbench. It has not seen in-depth use in real hardware so far." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - arniml name: gamepads status: FPGA proven svn-updated: Aug 15, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Aug 21, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - axuan252689 name: gbiteth status: FPGA proven svn-updated: Aug 22, 2013 updated: Aug 22, 2013 wishbone-compliant: 1 - category: Arithmetic core created: Jun 3, 2011 description: "===== \n Description =====\n\nName: Signed GCD Calculator\nSpecification:\n1.\tThis is a parameterized module of a GCD calculator and for this project the input of the GCD calculator is a signed 8-bit input.\n2.\tFrom the original design GCD calculator, the feature of this GCD calculator is upgraded which it is supporting the operation of signed numbers.\n3.\tSince this is a 8-bit GCD calculator the range number for positive input is from 0 to 127 and the range number for negative input is from -128 to 0. In short, the range of the input is -128 to +127.\n4.\tThe bit number 7 is used to check whether the input is positive or negative number. If the bit number 7 is HIGH, so the input is a negative number and if LOW the input is a positive number.\n5.\tWhen the input is a negative number, the number will be converted to the corresponding positive number by 2\xE2\x80\x99s complement operation in the Verilog code design entry by assigning the positive input equals to negative, the synthesizer will convert the negative number to positive number. \n6.\tFrom the original design of this GCD calculator, some consideration should be taken care of in order to get the output of the GCD calculator, which is refer to register G. In the first design entry, the register G will never give an output of the GCD calculator unless doing some changes on the original datapath by removing the register G or by enabling the load enable of register G during the negative edge clock triggered in the datapath design entry because in order to get the output from the register G, the GCD must be in the same state(S1) after the result of alu is loaded into either register P or register Q. Another option to modify the original datapath module is by adding a register with tri-state output for register , meaning that, when the value for P and Q are equal, a control signal will be enabling the output of the tri-state buffer so that we can get the result of the GCD.\n7.\tAll of these three methods are modifying the original datapath unit. Besides that, the control unit module also can be modified by adding 1 more state to the ASM Flowchart which is S2. Noticed that, at S0 that input p0 and q0 are loaded in register P and register Q respectively, and at S1 the result of alu(substraction) will be loaded into either register P or register Q which is depends on the result of the comparator. After some iteration, once the P and Q are equal, we can load the current P value into register G as the result of the GCD, so that we have to add another 1 more state (S2) to load the P value into register G resulting a stable GCD output that can be supplied the another modules in a system.\n8.\tAs a result, the original datapath design entry is modified by assigning a control signal enG the bufferG (active HIGH) such that the output can be yeild at this state which is S1. Otherwise the GCD output is high-Z." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - muzabyte name: gcd status: Empty updated: May 18, 2012 wishbone-compliant: 0 - category: Crypto core created: Oct 14, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: unknown maintainers: - tariq786 name: gcm-aes status: FPGA proven svn-updated: Oct 16, 2010 updated: Oct 16, 2010 wishbone-compliant: 0 - category: System on Chip created: Feb 22, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - andreas name: gdp64hs_fpga status: Empty updated: Feb 22, 2013 wishbone-compliant: 0 - category: System on Chip created: Sep 23, 2008 description: "===== \n Description =====\n\nThe GECKO system is a general purpose hardware/software co-design environment for real-time information processing and/or system-on-chip (SoC) solutions. The GECKO system supports a new design methodology for system-on-chips, which necessitates co-design of software, fast hardware and dedicated real-time signal processing hardware.\n\n\n\n\n\nThis is now the third generation of these boards, so the current project is called GECKO3.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAll GECKO3 system components can be stacked together, as they all have a common backbone bus connector and all have the size of a credit card.\n\n\n\n\n\nInformation about the whole Project, all related modules, software support, tutorials and much more can be found on the project wiki:\nlabs.ti.bfh.ch/gecko\n\n\n\n\n\nGet the nice GECKO3 project leaflet in pdf format with all important information about our project.\n\n\n\n \n\n\n \n \n \n\n===== \n GECKO3 Modules =====\n\nThe GECKO system comprises hardware modules that can be readily interfaced. The GECKO3main module is the main experimental platform, offering the necessary computing power for processing intensive real-time algorithms as well as the necessary flexibility for control intensive software tasks.\n\n\n\n\n\nDifferent GECKO3 modules are available to adapt the GECKO3main to the needs of different applications. An optional board, the GECKO3interface, houses a 160 x 128 pixel graphical color OLED display and a keyboard.\n\n\n\n\n\nThe autonomous GECKO3EDU robot is a composition of different modules with sensors, motors and mechanical housing. It is used for educational purposes. One of its modules, the GECKO3power board, provides the necessary power supply and, in addition, houses H-bridges to control the robot\xE2\x80\x98s motors, on-board ultrasonic sensor for measuring distances to obstacles and line sensors for line-follower applications. The GECKO3 robot is the mechanical vehicle for the robot with 2 or 4 small motors and a 3900 mAh Li-Ion battery pack.\n\n\n\n\n\n\nFor autonomous robots, various sensor capabilities are crucial. The GECKO3sensors board therefore houses a variety of sensors like two-dimensional magnetic field sensor for compass application, a two-dimensional acceleration sensor, digital video camera for image processing as well as a bluetooth wireless communication device.\n\n\n\n\n\nTo support autonomous navigation in outdoor environments, the robots can use the GECKO3gps module to quickly add a high sensitivity GPS receiver with an on-board antenna. The module is GALILEO aware.\n\n\n \n\n\n \n \n \n\n===== \n GECKO3main =====\n\nThe features of the Gecko3main board include:\n\nFPGA with 1.5Mio. to 4Mio. gates (Xilinx Spartan3)\n128 Mbyte DDR SDRAM and 32Mbyte NOR Flash (Enough to support Linux)\nUSB 2.0 interface for configuration and data transfer\n 100 Mbit/s Ethernet interface\nSmall, as size range of a credit card (85 x 54,5 mm)\nFully Compatible with IP-Cores from: Opencores.org, LEON3 (GRLIB) and Xilinx EDK\n\n\n\n\n\n\n\n\n\n\n\n\nExtensibility, Scalability\nThe GECKO3main includes fully populated GECKO3 system bus connectors. The module can be stacked with any other GECKO3 module and also with other GECKO3main modules. We provide a fast and collision free development environment because none of the I/O Pins on the System Bus are shared with on-board peripherals.\n\n\n\n\n\nUSB 2.0 Communication and FPGA Configuration\nMatlab and Labview can access the GECKO3main through the VISA API (Virtual Instrument Software Architecture) using the Instrument Control Toolbox in Matlab. The VISA API can also be used from other environments calling Windows DLLs. On Linux you can use normal file I/O with the USB-TMC driver instead of the proprietary VISA driver. The USBTMC Driver is included in every Linux Kernel >2.6.28, and you can also compile it yourself for older kernels. We use this system not only to configure the FPGA during development and for data communication, but also to configure the FPGA in stand-alone mode.\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Project license =====\n\n\nAll parts of this project (including text, photograph and any other original works), unless otherwise noted is licensed under a Creative Commons License (by-nc-sa)\n\n\n\n\nFor more information check out the License page in our wiki." homepage: http://labs.ti.bfh.ch/gecko language: VHDL license: CC-BY-SA and LGPL maintainers: - hga3 - nussgipfel - ktt1 name: gecko3 status: FPGA proven svn-updated: Apr 20, 2010 updated: Mar 16, 2012 wishbone-compliant: 1 - category: System on Chip created: Feb 1, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - ktt1 - hga3 name: gecko4 status: Planning svn-updated: Feb 13, 2011 updated: Apr 7, 2011 wishbone-compliant: 0 - category: Other created: Jan 9, 2011 description: '' language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - syslinux name: gedif status: Empty updated: Jan 9, 2011 wishbone-compliant: 0 - category: Memory core created: Sep 24, 2002 description: "===== \n Description =====\n\nGeneric, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Written in Verilog\n- Fully Synthesizable (FPGA & ASIC libraries)\n- Parameterized\n- Single and Dual Clock \n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- All FIFOs that are release are done. They have been simulated and most of them have been used in one way or another in one of my projects. Some have been verified in real hardware.\n- October 2003, Added a dual clock FIFO that is gray code encoded (fully parameterizable)\n \n\n\n \n \n \n\n===== \n Dependencies =====\n\nTo use this IP core, you must also download the generic_memories models. Download here\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: generic_fifos status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 29, 2011 wishbone-compliant: 0 - category: Memory core created: May 3, 2013 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: genesys_ddr2 status: FPGA proven svn-updated: May 8, 2013 updated: May 6, 2013 wishbone-compliant: 1 - category: DSP core created: Apr 12, 2012 description: "===== \n Description =====\n\nThis is an elementary generic structural VHDL code for FIR digital filters in transposed-form and direct-form implementations. \n\nThis project covers a wide spectrum of design aspects, in particular design and both functional and formal verification. \n\nThe project is developed in VHDL and modeled in SystemC. The SystemC model is used for functional and formal verification.\n\nTCL scripts for GHDL and SystemC is included within the project files.\n\nThis code could be considered for VHDL classes or DSP classes for amateurs or beginners. \nThe developed code was synthesized for FPGA and ASIC (0.13um CMOS) using: \nXilinx \t\tISE \nSynopsys \tDesign Compiler \nCadende \tRTL Encounter \n\nFurther, it was implemented using Xilinx Spartan-3E FPGA utilizing the Spartan-3E Starter Kit. It was tested using Xilinx ChipScope and a complete lab setup, as well. The filter output was converted to analog output using the on-board DAC to trace it on a Spectrum analyser." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: gfir status: Stable svn-updated: Apr 13, 2012 updated: Apr 13, 2012 wishbone-compliant: 0 - category: Library created: Sep 4, 2005 description: "===== \n Description =====\n\nPerhaps more of a collection of part than a true library, this is a set of VHDL parts that may be used as a set of building blocks for larger designs.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\ncounters, shift registers, pulse stretchers (high, low, and programmable) and other MSI parts\nsix fixed length LFSR's (24, 36, 48, 64 bits and two that are set with Generics)\ntwo Programmable length LFSR's\nclocked delay lines (fixed and programmable)\ncontrol registers (individual bits may be set, cleared, or inverted)\nGPIO\nPulse Generator\nBurst Generator\nParity generator\nSweep Generator\nCIC filter\nNCO's (some using a CORDIC, others using a Look up tables)\nCORDIC (with 20 bit or 28 bit atan function)\n(-)Sin/Cos look-up tables (12 bit, 14 bit, and 16 bit) \nbaud rate generator\nFIR Filters (Serial and parallel - most with generics, some that do not use multipliers)\nthree MAC's (Multiply Accumlator - one with generics)\nTVFD filter\nFIFO's (sync and async)\nDual port RAM (1 write port, 2 read ports) \nFour byte dual port RAM (2nd port of 32, 16, or 8 bits)\nFASM RAM (Synchronous write port, Asynchronous read port(s))\n\nRandom Number Generator \nRandom number scaler (2)\n\nSix \xE2\x80\x9CIn place\xE2\x80\x9D Multipliers\n (two with two signed inputs, two with two unsigned inputs, \n and two with both- a signed input and an unsigned input\n two of those have all bits on output)\n\nComplex adder, multipliers\ndigital attenuator\n\nVMEbus Slave interface Modules (A32D32,A24D16,A16D16)\n\nPulse Width Modulator\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nWaiting for suggestions" language: VHDL license: custom licensetext: "Permission is hereby granted, free of charge, to any person obtaining a copy of this\nOpenCores Project and associated documentation (the \"lesser IP\"), to use it in the in\nlarger designs (the \"greater IP\") without restriction, subject to the following conditions:\n1. The copyright notice is retained in the source files, and if they are modified, the\n Revision block must updated to identify the changes.\n2. The lesser IP itself may not be sold, but this restriction is limited to the lesser IP\n itself, not to any greater IP that it may be used in. (Inclusion on a distribution CD\n of, for example, OpenSource Projects is not considered a \"sale\")\n3. Any greater IP which uses the lesser IP, when distributed as source code or\n synthesized net list, must include in the documentation an acknowledgement of\n using the GH VHDL Library (This acknowledgement is not required for the\n distribution of a fuse map or other hardware implementation in CPLD, FPGA,\n ASIC or other form of custom IC).\n4. THE LESSER IP IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY\n KIND, EXPRESS OR IMPLIED.\n5. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ARISING\n FROM, OR IN CONNECTION WITH THE USE OF THE LESSER IP.\n" maintainers: - ghuber - hlefevre name: gh_vhdl_library status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Jul 20, 2012 description: "===== \n Description =====\n\nThis project is developed at Reconfigurable Computer Laboratory - FRM - UTN, \nand allows simulate and synthesize the Gregory-Newton extrapolation algorithm, \nusing integer numbers." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ivanmillan36 - Ruy name: gnextrapolator status: FPGA proven svn-updated: Aug 21, 2012 updated: Aug 14, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Aug 7, 2014 description: "===== \n Description =====\n\nThe Gaussian Noise Generator core generates white Gaussian noise of standard normal distribution, which can be used to measure BER to extremely low BER levels (~10-15). The core uses a 64-bit combined Tausworthe generator and an approximation of the inverse normal cumulative distribution function, which obtains a PDF that is Gaussian to up to 9.1\xCF\x83.\nThe core was designed using synthesizable Verilog code and can be delivered as a soft-IP targeted for any FPGA device and ASIC technology. C/MATLAB models and corresponding test benches are also available.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Period of generated noise sequence is about 2^176\n- Random distribution in the range of \xC2\xB19.1\xCF\x83\n- Noise is quantized to 16 bits with 5 bits of integer and11 bits of fraction\n- Internal 64-bit uniform random number generator with configurable initial seeds\n- Based on a piecewise polynomial approximation of the inverse normal cumulative distribution function\n- High throughput, over 300 MHz clock rate and output sample rate in advanced FPGA\n- Fully synchronous design using single clock\n- Design optimized for Xilinx & Altera FPGA technology\n\n \n\n\n \n \n \n\n===== \n Applications =====\n\n- Communication system requiring accurate emulation of an AWGN channel\n- Bit error rate measurement system\n\n \n\n\n \n \n \n\n===== \n Synthesis results =====\n\nXilinx\n- Device: Virtex-6 XC6VLX240T-2ff1156\n- Number of occupied Slices: 97\n- Number of RAMB36E1:\t 1\n- Number of DSP48E1s:\t 2\n- Maximum frequency:\t 311.8 MHz\n\nAltera\n- Device: Stratix IV GX EP4SGX230KF40C3\n- Total LABs: 34\n- M9K blocks: 2\n- DSP block 18-bit elements: 4\n- Maximum frequency: 376.8 MHz" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: gng status: FPGA proven svn-updated: Jan 29, 2015 updated: Feb 1, 2015 wishbone-compliant: 0 - category: Other created: May 22, 2014 description: "===== \n Description =====\n\nGNSS Signal Generator writen by Verilog.\nThis Signal Simulator generate signal as IF signal. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Written in SystemVerilog, and fully synthesisable\n- Wishbone bus compliant\n- Repetitive interrupt mode, Programmed to provide 3 different interval interrupt requests" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - doka name: gnss_sim status: Empty updated: Jun 2, 2014 wishbone-compliant: 0 - category: ECC core created: Oct 13, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tonyscam name: golay_24_12_codec status: Empty updated: Oct 13, 2013 wishbone-compliant: 0 - category: Crypto core created: Mar 13, 2014 description: "===== \n Description =====\n\nThe GOST block cipher, defined in standard GOST 28147-89, is a Soviet and Russian government standard symmetric key block cipher.\nDeveloped in the 1970s, the standard has been marked \xE2\x80\x9DTop Secret\xE2\x80\x9D and the downgraded to \xE2\x80\x9DSecret\xE2\x80\x9D in 1990. Shortly after the dissolution of the USSR, it was declassified and it was released to the public in 1994.\nwikipedia: http://en.wikipedia.org/wiki/GOST_%28block_cipher%29\n \n\n\n \n \n \n\n===== \n Modes =====\n\nCore supported ecb, ecb pipeline, cfb, mac.\n \n\n\n \n \n \n\n===== \n Status =====\n\nCore was tested on a Altera Cyclone II\necb mode needs ~200 LUTs\necb pipeline need ~3k LUTs" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - fanatid name: gost28147-89 status: FPGA proven svn-updated: May 8, 2014 updated: Mar 13, 2014 wishbone-compliant: 0 - category: Crypto core created: Apr 17, 2012 description: "===== \n Description =====\n\nThis is a implementation of the GOST 28147-89 - a Soviet and Russian government standard symmetric key block cipher. \nGOST 28147-89 has a 64-bit blocksize and 256-bit keysize. \n\nThis implementation provide trade off size and performance. The goal was to be able to fit in to a low cost Xilinx Spartan series FPGA and still be as fast as possible. As one can see from the implementation results below, this goal has been achieved. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- SystemVerilog RTL and TB code is provided \n - Implements both encryption and decryption in the same block\n - GOST 28147-89 algorithm focusing on very low area applications\n - Implementation takes about 32 cycles to encrypt/decrypt a block\n - EBC-cipher mode support\n - The core complies to use of S-box according to RFC4357/GOST R34.11-94 or RFC5830 (by synthesis), or S-box switch \"on the fly\" (realtime).\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Core implementations have been tested on a Xilinx Spartan-3E FPGA succesfully\n - This core is done. Initial Release: Apr. 17, 2012 \n \n\n\n \n \n \n\n===== \n Employment =====\n\nFor run synthesize design using Synplify tool use command:\n\n $ make synthesis\n\nTo compile and run simulation RTL-design using ModelSim with CLI:\n\n $ make sim \n\nTo compile and run simulation RTL-design using ModelSim with GUI:\n \n $ make sim-gui \n\n\nIn order to determine which S-box will be used for synthesis/simulation you must to pass apropriate define by command line argument: \n\n GOST_R_3411_TESTPARAM - for RFC4357 S-box using\n GOST_R_3411_CRYPTOPRO - for RFC5830 S-box using\n GOST_R_3411_BOTH - both RFC4357 and RFC5830 S-boxes using with switch \"on the fly\"\n \n \n\n\n \n \n \n\n===== \n Synthesis =====\n\nSample Synthesis Results for the ECB-mode GOST 28147-89\n\nTechnology \t Size/Area \tSpeed/Performance\n==============================================================\nXilinx Spartan-3E 525 LUTs 75 Mhz (150 Mbits/sec)\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Limitations =====\n\nThis design uses SystemVerilog as language for RTL-implementation therefore your design tools must should support SystemVerilog for synthesis and simulation.\n \n\n\n \n \n \n\n===== \n ToDo =====\n\n- Implementation testing with support Botan crypto-lib. It can be used in a VPI-based testbench as golden model or test vector generator.\n- Support for following cipher modes: CBC, CFB, OFB (and CTR maybe). \n- Adding SoC-buses compatibility for seamless integration." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - doka name: gost28147 status: FPGA proven svn-updated: Mar 19, 2014 updated: Mar 17, 2014 wishbone-compliant: 0 - category: Communication controller created: Nov 25, 2012 description: "===== \n Description =====\n\nProject content:\n\ntrunk/vhdl - source of this open core\ntrunk/prototype_1 - example prototype using the GPIB core\ntrunk/prototype_1/fpga - xilinx project using trunk/vhdl as SVN external\ntrunk/prototype_1/PC_software - PC test software\ntrunk/prototype_1/PCB - schematic diagram and PCB for prototype\n\nPrototype board uses minimodule MMfpga12 (http://www.propox.com/products/t_154.html?lang=en).\nThe value added by the board is phisical GPIB interface and USB interface to connect to PC.\n\nTo run prototype download trunk/prototype_1/fpga, build it and configure FPGA.\nNext Download trunk/prototype_1/PC_software, edit (const char *portName = \"/dev/ttyUSB0\";) in file GpibRegAccess_linux.c to port of your USB adapter. Run software with \"ge\" (Gpib Explorer) parameter." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - Andrewski name: gpib_controller status: Design done svn-updated: Jan 11, 2013 updated: Jan 6, 2013 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Description =====\n\nThe GPIO IP core is user-programmable general-purpose I/O controller. Its use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals. \n \n\n\n \n \n \n\n===== \n Features =====\n\nThe following lists the main features of GPIO IP core: \n\n- Number of general-purpose I/O signals is user selectable and can be in range from 1 to 32. For more I/Os several GPIO cores can be used in parallel. \n- All general-purpose I/O signals can be bi-directional (external bi-directional I/O cells are required in this case). \n- All general-purpose I/O signals can be three-stated or open-drain enabled (external three-state or open-drain I/O cells are required in this case). \n- General-purpose I/O signals programmed as inputs can cause interrupt to the CPU. \n- General-purpose I/O signals programmed as inputs can be registered at raising edge of system clock or at user programmed edge of external clock. \n- All general-purpose I/O signals are programmed as inputs at hardware reset. \n- Auxiliary inputs to GPIO core to bypass outputs from RGPIO_OUT register. \n- Alternative input reference clock signal from external interface. \n- WISHBONE SoC Interconnection Rev. B compliant interface \n\nMore information about the WISHBONE SoC and a full specification can be found here.\n\nFor further information, questions and general discussions related to the GPIO core, please visit the Cores Mailing list.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- verilog RTL and verification suite are finished (see Downloads section)\n- specification document is finished (see Downloads section)" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - lampret name: gpio status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: DSP core created: May 11, 2012 description: "===== \n Description =====\n\nThis is a behavioral SystemC model for Polyphase Decimation filters. It can be used as for system design and functional verification. It has been tested with Matlab and Octave as well. If you need any further illustrations or further modifications, don't hesitate to contact me. It can be used effectively for class instruction. It is a good practice for SystemC beginners and DSP student/engineers as well.\n\nFeel free to contact me whenever you have further requests or comments." language: SystemC license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: gppd status: Stable svn-updated: May 11, 2012 updated: May 11, 2012 wishbone-compliant: 0 - category: Processor created: Feb 8, 2015 description: "===== \n Description =====\n\nThe graphics processed by the GPU are defined as a set of vertices that contain spatial information, i.e. vectors with coordinates [x y z] in three-dimensional Cartesian space, and additional information of color or texture coordinates.\n\nThe processing that is performed has 4 phases:\n\n1. A group of vertices is processed as a point list, a line list, a line strip, a triangle list, a triangle strip or a triangle fan.\n2. The given vertices are transformed three-dimensionally based on a 4x4 transformation matrix, being able to translate them, rotate them, scale them and/or project them.\n3. Depending on whether the vertices correspond to a set of points, lines or triangles, the visible region of these figures is calculated by cutting the parts that are in front of the near view plane, and the parts that are behind the far plane of vision.\n4. The information contained in the vertices is mapped in the area defined by these, at this stage it is assumed that the vertices already been projected from three-dimensional space to a space bidimencional.\n\nThe area mentioned in step 4 of processing corresponds to a section of memory that can be read and then sent to a screen for viewing." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - diegoandres91b name: gpu status: FPGA proven svn-updated: Feb 10, 2015 updated: Feb 10, 2015 wishbone-compliant: 0 - category: Crypto core created: Nov 22, 2008 description: "===== \n Description =====\n\nThis project has been moved to bitbucket: https://bitbucket.org/vahidi/grain" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vahidi name: grain status: FPGA proven svn-updated: Mar 10, 2009 updated: Nov 3, 2014 wishbone-compliant: 0 - category: Video controller created: Dec 16, 2003 description: "===== \n Description =====\n\nThis core is used to provide a wishbone compliant interface to a graphical LCD. Currently it supports the Crystalfontz CFAG12864 family which is based on the KS0108B controller.\n\nOther graphical LCDs may be supported at a later date.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Wishbone compliant\n- Interfaces with KS0108B graphical LCD controller\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Sythesized and tested" language: VHDL license: unknown maintainers: - maihde name: graphicallcd status: Beta svn-updated: Mar 10, 2009 updated: Aug 27, 2010 wishbone-compliant: 1 - category: Video controller created: May 16, 2011 description: "===== \n Description =====\n\nThis project is a group of hardware units that perform graphics algorithms.\nFor testing purposes, beside the Units that perform these algorithms, there is a Frame Buffer that holds the image drawn and a Video Controller that outputs the image to a screen. In addition to the user interface which consists of switches and push buttons that selects the color, position, function performed, .. etc.\n \n\n\n \n \n \n\n===== \n Current State =====\n\nTill now we have the Bresenham Line Drawing Algorithm.\nDue to the Limitations of the FPGA that I am working on, the Frame Buffer is only 170x120 pixels x 8 Colors.\n \n\n\n \n \n \n\n===== \n Demo =====\n\nThis video shows a test for using the current project where I write my name using Lines with different colors.\nhttp://www.youtube.com/watch?v=siI4f6GxyM4" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - OmarMokhtar name: graphicsaccelerator status: FPGA proven svn-updated: May 17, 2011 updated: May 20, 2011 wishbone-compliant: 0 - category: Video controller created: Mar 20, 2007 description: "===== \n Overview =====\n\nThe MiniGA is a small graphics adapter for microcontrollers. It outputs a video signal for TVs, VCRs and TFTs with video input. MiniGA features a SPI interface which makes interfacing to most microcontrollers easy. A cycle-shared-RAM interface coordinates read and write accesses to the RAM so the user needn't take care about data collisions which simplifies the usage. Moreover MiniGA generates all needed timings and outputs a digital video which is converted to analog by a 10Bit DAC externally.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- PAL Encoder Core written 100% in VHDL\n- No Xilinx/Altera specific IP core used (except DCM/PLL for clock generation)\n- 100% digitally synthesized PAL video @ 45MHz sampling rate\n- Almost exact PAL timing and frequencies\n- 780x576px @ 16Bit color depth\n- 1MByte asynchronous video RAM (Two standard 512k*8 SRAM organized as 512k*16, access time 15ns)\n- Cycle shared memory interface performance: 60MByte/sec (30MByte/sec per bus, writing of >25 full frames/sec should be possible but not tested yet)\n- RGB to YUV conversion\n- FIR-Lowpass filter for U and V color components\n- SPI-Interface\n- Small PCB size of 86x53mm\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Version 1.00 finished\n\n \n\n\n \n \n \n\n===== \n Results =====\n\nThe following two images are result pictures from MiniGA. The first was photographed from a TV, the second was captured with a TV capture card.\n \n\n\n \n \n \n\n===== \n Platform =====\n\nMiniGA has been developed/tested on following platforms:\n- Custom PCB with Xilinx XC3S200 (~85% system resources used)\n- Development Board with Altera EP1C12 (~30% system resources used)\n\nThe pictures below show my Custom Board (prototype). \nNote: There are newer board and schematic files in the CVS.\n\n\n \n\n\n \n \n \n\n===== \n To Do =====\n\n- Faster SPI Interface.\n- Maybe shrink the core. The core is quite large because most calculations are too precise. The core outputs a 16Bit video and just 10Bits are used.\n- Maybe Wishbone interface\n \n\n\n \n \n \n\n===== \n IMAGE: blockschaltbild.png =====\n\nFILE: blockschaltbild.png\nDESCRIPTION: Simplified Block Diagram\n\n \n\n\n \n \n \n\n===== \n IMAGE: thumb_tflowers.jpg =====\n\nFILE: thumb_tflowers.jpg\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n IMAGE: thumb_flowers.jpg =====\n\nFILE: thumb_flowers.jpg\nDESCRIPTION: Captured with TV capture card\n\n \n\n\n \n \n \n\n===== \n License =====\n\nLicense: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License\n\nIf you want to use MiniGA for commercial purposes please contact the project maintainer.\n \n\n\n \n \n \n\n===== \n Maintainer's Homepage =====\n\nhttp://www.pcb-dev.com\n \n\n\n \n \n \n\n===== \n IMAGE: thumb_graphiti.jpg =====\n\nFILE: thumb_graphiti.jpg\nDESCRIPTION: My XC3S200 Custom PCB (prototype)\n\n \n\n\n \n \n \n\n===== \n IMAGE: thumb_graphitib.jpg =====\n\nFILE: thumb_graphitib.jpg\nDESCRIPTION: Back side (prototype)\n\n \n\n\n \n \n \n\n===== \n Planned =====\n\nI plan to minimize the necessary PCB and the FPGA. The next PCB will be equipped with a EP2C5 because Altera FPGAs are easier to use (power supply, ...). Additionally everythink should become cheaper.\n\n\n \n\n\n \n \n \n\n===== \n IMAGE: thumb_testbild.jpg =====\n\nFILE: thumb_testbild.jpg\nDESCRIPTION: Captured with TV capture card" language: VHDL license: CC BY-NC-SA 2.0 DE licenselink: http://creativecommons.org/licenses/by-nc-sa/2.0/de/ maintainers: - pototschnig name: graphiti status: Beta svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Prototype board created: Feb 14, 2011 description: "===== \n Description =====\n\n Griva Basic 1.2v - FPGA development kit\n\n\n\n\n\n\n\n\n Highlights \n\n- Power Supply\xC2\xA0 * 3.3 Volt - DC/DC-buck MAX1626 \xC2\xA0 * 2.5V LM1117-ADJ\xC2\xA0 \xC2\xA0 * 1.2V LM1117-ADJ - FPGA\xC2\xA0 * Xilinx Spartan3E XS3S250E or XC3S500E -PQG208 -Flash\xC2\xA0 * Atmel AT45DB041D - 4Mb SPI Data Flash memory - USB\xC2\xA0 * FT245RL - USB interface - Full Speed - Misc\xC2\xA0 * 4x LED\xC2\xA0 \xC2\xA0 * 2x 7 segment LED\xC2\xA0 \xC2\xA0 * 4x SwDip switch\xC2\xA0 \xC2\xA0 * 2x Button\xC2\xA0 \xC2\xA0 * 2x IDC-2x20 header GPIO\xC2\xA0 \xC2\xA0 * Xilinx JTAG header\xC2\xA0 \xC2\xA0 * Xilinx SPI header \xC2\xA0 * Oscillator - 50MHz" language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Arek name: griva status: Stable svn-updated: Feb 26, 2011 updated: Feb 26, 2011 wishbone-compliant: 0 - alternate-download: http://cc.doc.ic.ac.uk/projects/GROUNDHOG/DISTRIBUTIONS/groundhog2009_web_distrib.tar.gz category: Other created: Feb 20, 2009 description: "===== \n Status =====\n\n- [Match 3rd - 2009] Initial RTL benchmark downloads from Imperial College added\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nGroundHog 2009 is a benchmark suite for reconfigurable architectures in the mobile domain. The benchmark suite can be downloaded from http://cc.doc.ic.ac.uk/projects/GROUNDHOG/ .\n\nThe benchmark suite includes designs described in a high-level format that is non-synthesizable. For this reason, this project on OpenCores is a space where individuals in the community can release synthesizable (and compilable) versions of their implementations of the 6 benchmarks.\n\nThe benchmarks are:\n\nGH09.B.1 - Port expander and keypad controller\nGH09.B.2 - Glue Logic\nGH09.B.3 - AES encryption cypher\nGH09.B.4 - Data compression using Lempel-Ziv\nGH09.B.5 - Bridge chip\nGH09.B.6 - 2D convolution\n\nHardware test bench and example RTL for the design cases can be found at \nhttp://www.cs.tut.fi/projects/GroundHog2009/index.html .\n\nTo view synthesizable designs check the download section.\n\nAlso, to contribute your designs to the repository please contact us." homepage: http://cc.doc.ic.ac.uk/projects/GROUNDHOG/ language: Verilog license: MIT / unknown maintainers: - drpaj - fallow name: groundhog2009_repository status: FPGA proven svn-updated: Mar 10, 2009 updated: Nov 2, 2011 wishbone-compliant: 0 - category: Other created: Jul 31, 2007 description: "===== \n Description =====\n\nDescription of project..\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - samuelgoto name: gsc status: Stable svn-updated: Mar 10, 2009 updated: Feb 22, 2011 wishbone-compliant: 0 - category: Communication controller created: Jun 8, 2013 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: gsm_module_controller status: Empty updated: Jun 9, 2013 wishbone-compliant: 0 - category: Processor created: Apr 2, 2008 description: "===== \n Gator Microprocessor (GuP) Overview =====\n\n- Motorola/Freescale 68xx Architecture\n - Source-code and machine-code compatible 68HC11 cpu core\n - Compatible with all HC11 C/C++ compilers including GNU GCC\n - Up to 100MHz operation in modern FPGAs\n - 2.5 times faster per clock cycle than a HC11 on average\n\nVisit the official website at:\nwww.mil.ufl.edu/projects/gup\n \n\n\n \n \n \n\n===== \n Status =====\n\nVersion 0.9a: Released\nVersion 1.0: Released\nVersion 2.0: Coming Soon" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dundee name: gup status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 5, 2011 wishbone-compliant: 0 - category: Communication controller created: Mar 6, 2012 description: "===== \n Architecture =====\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nHardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packets transmitting and receiving should be implemented by PTP SW protocol stack (PTPd) with existing MAC function; This IP Core implements the Real-Time Clock (RTC) and Time Stamping (TSU) of PTP event packets.\n\nFeature Description\n\nRTC: Real Time Clock.\n * Standard PTP clock output with 2^48s and 2^32ns time format.\n * 1PPS output for clock accuracy measurement.\n * Tunable accumulator based clock with 2^-8ns time resolution and 2^-32ns period resolution.\n ** Direct time write, with 2^-8ns resolution.\n ** Direct frequency write, with 2^-32ns resolution.\n ** Timed temporary time adjustment, with 2^-8ns resolution and 32bit timer.\n * Variable input clock frequency.\n * Clock Domain Crossing hand-shaking, for SW read and write access.\n \nTSU: Time Stamping Unit.\n * Two-Step PTP operation.\n * GMII/MII interface monitor with line-speed PTP packet parsing.\n * Variety of PTP packet formats supported.\n ** Layer2 IEEE 802.3 PTP packet, with stacked VLAN tags.\n ** Layer4 IPv4/UDP and IPv6/UDP PTP packet, with stacked VLAN tags and/or stacked MPLS labels.\n * Configurable 8bit one-hot mask to selectively timestamp PTP event packet based on message type value.\n ** mask bit 0: Sync\n ** mask bit 1: Delay_Req\n ** mask bit 2: Pdelay_Req\n ** mask bit 3: Pdelay_Resp\n ** mask bit 4 to 7: Reserved for future PTP event message types\n * 32bit packet parser datapath for easier timing closure.\n * 15-entry timestamp queue. \n * 128bit timestamp format.\n ** 16bit extra information.\n ** 80bit timestamp.\n ** 32bit packet identity data.\n\nSystemVerilog DPI based simulation environment is included for SW driver development and co-simulation.\n(sim/top/ptp_drv_bfm/ptp_drv_bfm.c) (sim/top/ptp_drv_bfm/ptp_drv_bfm.v)\n\nPCAP file based stimulus input is included for verification with real-world traffic.\n(sim/top/nic_drv_bfm/ptpdv2_tx.pcap) (sim/top/nic_drv_bfm/ptpdv2_rx.pcap)\n\nThe IP Core can be used as an IP Component in Altera Qsys, Xilinx XPS or WishBone.\n(rtl/bus/qsys) (rtl/bus/xps/pcores) (rtl/bus/wishbone)\n\nThe only FPGA vendor dependent module is the timestamp queue. Both Altera and Xilinx's DCFIFOs are provided in the PAR folder.\n(par/altera/ip/dcfifo_128b_16.v) (par/xilinx/ip/dcfifo_128b_16.v)\n\n \n\n\n \n \n \n\n===== \n Bonus Tool =====\n\nA tool to analyze the transaction timing of captured PTPv2 packets. The tool is written and run in Scilab. The captured PTPv2 packets are results of running PTPdv2 between two PCs.\n(doc/tool/ptpv2_timing_analyzer/ptpv2_timing_analyzer.sce) \n \n\n\n \n \n \n\n===== \n TODO =====\n\nIt is complained that there is a lack of documentation for the HA1588 project. This will be fulfilled for the next release. Here are two requests for those who requested:\n1. Read the RTC and TSU memory map under the /doc folder, with the detailed operation procedure in the /sim/top/ptp_drv_bfm/ptp_drv_bfm.c \n2. Give feedback of what should be included in the documentation as bug-fix requests" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ash_riple name: ha1588 status: Design done svn-updated: Jun 3, 2014 updated: Feb 9, 2015 wishbone-compliant: 1 - category: ECC core created: Jun 11, 2004 description: "===== \n Description =====\n\nHamming (7,4) Encoder: This core encodes every 4-bit message into 7-bit codewords in such a way that the decoder can correct any single-bit error.\n\nThe encoder uses the generator matrix:\n\nG=[ 1110000\n 1001100\n 0101010\n 1101001]\n\nThe codewords are generated by\n\nC = M * G\n\nwhere M=[m1 m2 m3 m4] is the 4-bit message." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - soneryesil name: hamming status: Specification done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: ECC core created: Oct 27, 2006 description: "===== \n Description =====\n\nThis C++ program generates VHDL package with hamming encoder and decoder. It also generates a simple testbench that can be used to evaluate the generated Hamming code.\n\nmy email is ale_amory@opencores.org\n \n\n\n \n \n \n\n===== \n Features =====\n\n- It is a easy to use command-line program \n - HammingGen \\ \\ \\\n- It generates two types of Hamming code\n - SEC - Single Error Correction\n - SEC-DED - Single Error Correction and Dual Error Detection\n- It is easy to modify the original design\n\n\n\n \n\n\n \n \n \n\n===== \n Examples =====\n\nGenerated Code for a Hamming SEC with 32 bits\n\n- FUNCTION hamming_encoder_32bit(data_in:data_ham_32bit) RETURN parity_ham_32bit;\n- FUNCTION hamming_decoder_32bit(data_parity_in:coded_ham_32bit) RETURN data_ham_32bit;\n\nConsider the folowing resgister description\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is\n port (\n datain : in std_logic_vector(15 downto 0);\n clock : in std_logic;\n dataout : out std_logic_vector(15 downto 0);\n error : out std_logic_vector(1 downto 0)\n );\nend entity;\n\narchitecture test of test is\n signal temp : std_logic_vector(15 downto 0);\n\nbegin\n\n process(clock)\n begin\n if (clock'event and clock='1') then\n temp end if;\n end process;\n\n dataout end architecture;\n\n\nThe fault-tolerant version of this code is:\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse WORK.hamm_package_16bit.all;\n\nentity test is\n port (\n datain : in std_logic_vector(15 downto 0);\n clock : in std_logic;\n dataout : out std_logic_vector(15 downto 0);\n error : out std_logic_vector(1 downto 0)\n );\nend entity;\n\narchitecture test of test is\n signal temp : coded_ham_16bit;\n\nbegin\n\n process(clock)\n begin\n if (clock'event and clock='1') then\n temp hamming_encoder_16bit(datain);\n end if;\n end process;\n\n dataout hamming_decoder_16bit(temp);\n \nend architecture;\n\n \n\n\n \n \n \n\n===== \n Future Features =====\n\n- Support correction of more than one faults" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ale_amory - ghanashyam_prabhu name: hamming_gen status: Stable svn-updated: Mar 10, 2009 updated: Mar 21, 2013 wishbone-compliant: 0 - category: Testing / Verification created: Nov 23, 2005 description: "===== \n HASM Description =====\n\nHASM is a simple instruction simulator for use in the verification of FPGA/CPLD designs that must attach to a processor bus. HASM is meant to attach to a bus model that mimics the device attached to the FPGA or CPLD under test. HASM can be used as though it were a processor within the simulation environment without the tremendous increase in simulation times due to the overhead involved in simulating a real processor. \n\nThe HASM instruction simulator is comprised of two components: a Windows-based IDE and a VHDL module capable of reading the vector file generated by the HASM IDE. HASM 'programs' are written using assembler-like instructions. These instructions include Calls and Jumps to allow the testbench vector listing to be traversed linearly or recursively. \n\nHASM is meant to attach to a bus-specific VHDL core. The HASM VHDL module incorporates a simple, generic bus to ease the creation of the bus-specific module. This generic bus supports single and burst-oriented accesses. In addition, the HASM core contains an interrupt line that causes the HASM core to jump to a user-defined location in the HASM source program.\n\nCurrently HASM has completed bus models for VME bus, Marvell Discovery Device Bus, Xilinx's IPIF bus, Analog Devices' ADSP-21160 Sharc bus and the 68K-based Motorola QUICC.\n \n\n\n \n \n \n\n===== \n HASM Features =====\n\n- Instruction-Based Testbench Vector Generator\n - Includes Instructions to Alter Vector Flow:\n - Call, Jump, Return\n - Comparison Instructions Useful in Verification of DUT responses:\n - Compare Less, Compare Greater, Compare Equal\n - Single and Burst Oriented Data Transfer Instructions \n - Stack Based Instructions\n - Push, Pop\n - Boolean Instructions\n - AND, OR\n - Math Instructions\n - Add, Subtract\n - Interrupt Support\n - Single Interrupt Input to HASM Module\n - .ORG Directive for Creation of a Interrupt Service Routine in Vector File\n\n- Four General Purpose Registers\n- One General Purpose Register Routed out of HASM Module to be used as GPIO\n- Internal 256-word Scratch-Pad memory for Burst data Storage and Verification\n- 8 bit, 16 bit, 24 bit and 32 bit Transactions Alterable by Instruction Modifiers (wr.b, wr.w, rd.b, rd.w)\n- Currently Executing Instruction Visible within Simulator (allows vector file debug)\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- HASM Windows GUI Complete\n- HASM Cycle Simulator Model Complete\n- Discovery 3 HASM-to-Bus Model Complete\n- QUICC HASM-to-Bus Model Complete\n- XILINX IPIF HASM-to-Bus Model Complete\n- VME Bus HASM-to-Bus Model Complete" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rhirsch81 name: hasm status: Stable svn-updated: Mar 10, 2009 updated: Oct 19, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Apr 8, 2003 description: "===== \n Description =====\n\nHierarchical Carry Save Algorithm (HCSA) is a modification of well known adder algorithm. Comes as VHDL IP core, shows good timing and small area requirements. \nThe Generic HCSA ALU VHDL IP Core presents an example of HCSA methodology.\n\nHCSA adder and ALU with HCSA implemented as VHDL soft IP cores. Algorithm implemetation bases on recursion method.\n\nBasic Idea: Every Bit of the Result is calculated twice simultaneously :\n\n 1. As if there IS NO carry from LSB ( less significant bit )\n S(i) = A(i) + B(i) + 0;\n 2. As if these IS a carry from LSB\n S(i) = A(i) + B(i) + 1; \n\nReal Carry (i-1) used as a Selector for these intermediate sums and precalculated Carry for the next stage (which ones to output). The iteration applies for every bit of the sum. Generic ALU implemented on HCSA method has very good performance/area characteristics due to all Athithmetic operations are made within HCSA module. Logic operations and Command decoder are light weight modules. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- small area requirements for HCSA Adder - 1965 cells ( conditions: 128 bit operands, 0.35u Std Cell Library, typical conditions) \n- good performance 6.64ns ( same conditions ).\n- flexibility and reusability ( written completely in VHDL, no hardcoded macros used )\n \n\n\n \n \n \n\n===== \n Links =====\n\nThis core is provided by ASIC reseach department members of DeverSYS Corp., Visit this page. There are more usefull fundamental (and not only) FREE IP Cores at www.deversys.com." language: VHDL license: unknown maintainers: - vladvas name: hcsa_adder status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Other created: Oct 26, 2012 description: "===== \n Description =====\n\nThis simple HD44780 LCD Driver takes care of the most basic commands such as clear screen, cursor home and writing characters with single bit inputs. It uses the 8-bit data tranfer mode, 4-bit is not supported. The user can supply a number of timing parameters to taylor the timing between the driver and the LCD. Both Busy Flag reading and non-BF reading are supported." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jodb name: hd44780_driver status: Alpha svn-updated: Oct 12, 2014 updated: Oct 26, 2012 wishbone-compliant: 0 - category: Processor created: Dec 20, 2013 description: "===== \n Description =====\n\nThis project provides a synthesizable IP core compatible with HITACHI HD63701 processors." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - thasega name: hd63701 status: FPGA proven svn-updated: Feb 15, 2014 updated: Feb 15, 2014 wishbone-compliant: 0 - category: Communication controller created: Apr 27, 2003 description: "===== \n Description =====\n\nThis \xE2\x80\x9Ccore\xE2\x80\x9D is actually two cores \xE2\x80\x93 an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.\n\nNote: HDB2 and B3ZS are different names for the same encoding.\n\nHDB3 is typically used to encode data at 2.048 (E1), 8.448 (E2) and 34.368Mb/s (E3)\nB3ZS is typically used to encode data at 44.736Mb/s (T3)\n \n\n\n \n \n \n\n===== \n Features =====\n\n- HDB3 / HDB2 selected by a generic.\n- Code Error output on decoder.\n- P and N outputs (on encoder) or inputs (on decoder) may be active high or active low, selected by a generic.\n- P and N outputs on encoder may be controlled to be \xE2\x80\x9Cfull width\xE2\x80\x9D (NRZ) or \xE2\x80\x9Chalf width\xE2\x80\x9D (RZ) to suit the external LIU.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Alpha tests look good.\n- Code and documentation available in the HDBN project in CVSWeb" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - allanh name: hdbn status: Stable svn-updated: Mar 10, 2009 updated: Oct 29, 2014 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Features =====\n\n- 8 bit parallel backend interface\n- use external RX and TX clocks\n- Start and end of frame pattern generation\n- Start and end of frame pattern checking\n- Idle pattern generation and detection (all ones)\n- Idle pattern is assumed only after the end of a frame which is signaled by an abort signal\n- Zero insertion \n- Abort pattern generation and checking\n- Address insertion and detection by software\n- CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used)\n- FIFO buffers and synchronization (External)\n- Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)\n- Q.921, LAPB and LAPD compliant.\n- For complete specifications refer to spec document\n \n\n\n \n \n \n\n===== \n IMAGE: HDLC_top.jpg =====\n\nFILE: HDLC_top.jpg\nDESCRIPTION: Core top block diagram\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe VHDL code is ready in the opencores CVS. The code needs verification contact me if you are intrested in helping me. \n\n- also see Download section\n\n \n\n\n \n \n \n\n===== \n Resource usage =====\n\nRx Channel Block: which includes HDLC Framing extraction, zero removal and conversion from serial to parallel.\n\n\nVendor\n\nDevice\n\nSize\n\nFrequency\xC2\xA0\n\nBoard Tested\n\nFunctional Test\n\nNotes\n\n\n\nAltera\n\nEP20K100BC356-3\n\n108 LCs\n\n91.48MHz\n\n-\n\n-\n\nNo optimization was peroformed, using Quartus II\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n \nTx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial.\n\n\nVendor\n\nDevice\n\nSize\n\nFrequency\xC2\xA0\n\nBoard Tested\n\nFunctional Test\n\nNotes\n\n\n\nAltera\n\nEP20K100BC356-3\n\n100 LCs\n\n112.42MHz\n\n-\n\n-\n\nNo optimization was peroformed, using Quartus II \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nHDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers.\n\n\nVendor\n\nDevice\n\nSize\n\nFrequencies (MHz)\n\nBoard Tested\n\nFunctional Test\n\nNotes\n\n\n\nAltera\n\nEP20K100BC356-3\n\n630 LCs, 2 ESBs\n\nCLK_I=74.02, RxClk=101.86, TxClk=106.42\n\n-\n\n-\n\nNo optimization was peroformed, using Quartus II\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Links =====\n\nhttp://www.rad.com/networks/1994/hdlc/hdlc.htm\nhttp://www.erg.abdn.ac.uk/users/gorry/course/dl-pages/hdlc-framing.html\nhttp://members.tripod.com/~vkalra/hdlc.html\nhttp://goanna.cs.rmit.edu.au/~ivan/cs361/lec/lec5.pdf\nhttp://www.inicore.com/____pdf/inihdlc.pdf\nhttp://www.mentorg.com/inventra/netlist_program/actel/ds/hdlccoreA1_pd.pdf" language: VHDL license: custom licensetext: "This VHDL design file is an open design; you can redistribute it and/or\nmodify it and/or implement it after contacting the author\nYou can check the draft license at\nhttp://www.opencores.org/OIPC/license.shtml\n" maintainers: - khatib name: hdlc status: Stable svn-updated: Mar 10, 2009 updated: Dec 24, 2013 wishbone-compliant: 1 - category: Video controller created: Mar 30, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mohammad - ENGHaitham name: hdmivideodataencdec status: Empty updated: Aug 27, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Oct 14, 2012 description: "===== \n Description =====\n\nThis project implements a sorter able to sort a continuous stream of data, consisting of records labeled with \"sort keys\".\nSorter sorts one record every two clock cycles.\nSorter is based on the heap sort algorithm. Efficient implementation is assured thanks to the use of internal dual port\nRAM in FPGA.\nThe required size of heap is equal to the expected maximum distance between unsorted records in the data stream.\n \n\n\n \n \n \n\n===== \n Detailed description =====\n\nThe sorter implemented in this project is designed for sorting of stream of constant length records.\nThe main supposed application area are the multichannel data acquisition systems, where data records\nlabelled with time stamps are transmitted through multiple channels with different latencies \nto the data concentrator, which should sort data according to their time stamps and source identifiers\nbefore sending them to further processing.\n\nEach record contains the \"sort key\" and the payload.\nIn the simplest case, the sort key may be a N-bit bit vector, treated as unsigned integer number.\nOf course in case of lengthy data stream, the sort key will reach its maximum\nvalue of 2^N-1 and then wrap to 0.\nFor the sorter it is fully acceptable, as long, as the capacity of the sorter (maximum number of data records\nstored in the sorter) summed with the maximum distance between unsorted records in the input data stream is less than half of the maximum value of the sort-key.\nIn this case we may compare sort keys of the newly received data record and data records stored in the sorter\nusing simple operation:\n\n\n\n\nsignal unsigned sort_key1(N-1 downto 0);\nsignal unsigned sort_key2(N-1 downto 0);\nsignal signed sort_key_diff(N-1 downto 0);\n[...]\n\nsort_key_diff \n\n\n \n\nCorrect operation of the sorter requires, that the heap is initially filled with the records labelled\nwith smallest possible values of the sort key. Similarly, when all data are sent to the sorter, it is necessary to send to the input of the sorter records with the biggest possible value of sort key.\n\nThe \"smallest possible\" and the \"biggest possible\" values are implemented using additional bit fields \"init\" and \"valid\". This implementation allows as also to mark temporary interruptions in the stream of data, as shown below:\n\n\n\n init=1, valid=0 - \"initial record\"\n The sorter is filled with initial records on the beginning of operation. The \"initial record\" is \"smaller\" than any data record. On the output of the sorter initial records may be discarded.\n \n \n init=1, valid=1 - \"end record\"\n When all data are transferred to the sorter, you should feed the sorter with \"end records\" to keep the data flowing through the sorter, and to \"flush\" last sorted data out of the sorter. The \"end record\" is \"bigger\" than any data record. When first \"end record\" appears on the output, all data are sorted.\n \n \n init=0, valid=1 - \"standard data record\"\n This record contains the useful data. The time-stamp is stored in the \"sort-key\" and user data in the \"payload\".\n \n \n init=0, valid=0 - \"empty data record\"\n When in the particular sorting cycle there are no valid data on the input of the sorter, the last data records remain in the sorter. Therefore you may feed the sorter with \"empty data records\" with sort key equal to to the highest recent sort key, to keep data flowing through the sorter. On the output the \"empty data records\" may get discarded.\n \n\n\nThe main entity of the sorter is defined as follows:\n\n\n\nentity sorter_sys is\n generic (\n NLEVELS : integer := SYS_NLEVELS -- number of levels in the sorter heap\n );\n\n port (\n din : in T_DATA_REC;\n we : in std_logic;\n dout : out T_DATA_REC;\n dav : out std_logic;\n clk : in std_logic;\n rst_n : in std_logic;\n ready : out std_logic);\nend sorter_sys;\n\n\n\n\nTo customize it to your needs, you should adjust definition of the T_DATA_REC type in the sorter_pkg.vhd file.\nAdditionally you may also need to modify functions for converting data records into the std_logic_vector and from the std_logic_vector (tdrec2stlv and stlv2tdrec).\nYou may also change definition of the T_SORT_KEY type, but then probably you should also change the function sort_cmp_lt used to compare sort keys in two data records.\n\n\nThe sources provide also complete testbench for my sorter. To check it, you should simply adjust parameters given in the \"sort_test_gen.py\" file and run \"make\".\nThe Python script will generate the sorter configuration and input records. Then the makefile will compile the testbench and run the simulation.\nFinally the records on the output will be analysed. If everything works fine, the \"Test passed!\" message will be displayed.\nThe simulation is prepared for the Linux system, and uses the ghdl simulator.\n\nIf you want to synthesize the sorter for use in real FPGA, you should replace the implementation found in dpram4.vhd with implementation based on:\nhttp://danstrother.com/2010/09/11/inferring-rams-in-fpgas/ The source is available in dpram_inf.vhd\n\n\nAll my sources in this archive are published under the BSD license. You can use them and modify them, however you should keep the information about the original author.\nFirst implementation of the sorter has been described in my paper:\nWojciech M. Zabo\xC5\x82otny, \"Dual port memory based Heapsort implementation for FPGA\", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281.\nI'll be glad if you cite my paper, when you publish something based on my sources.\n\nThe archive contains also some sources (dpram4.vhd, dpram_inf.vhd) which were obtained from sources with unclear licensing conditions - so I simply provide them for completeness, but I'm not able to set any specific licensing for them.\n\nI don't know whether my sorter infringes any patents. If you want to use it for commercial purposes, you should check it yourself. I also don't know if my sorter works correctly in all possible conditions. I provide it \"AS IS\" without any warranty. You use it on your own risk!\n\nFirst version of the sorter is available on my own website:\nhttp://www.ise.pw.edu.pl/~wzab/fpga_heapsort/." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - wzab name: heap_sorter status: Beta svn-updated: Jul 4, 2013 updated: Oct 15, 2012 wishbone-compliant: 0 - category: Testing / Verification created: Dec 6, 2011 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - aitzol name: hex2vhd status: Empty updated: Feb 5, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Jul 21, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tuqiaolin name: hicc-mcu status: Empty updated: Jul 21, 2011 wishbone-compliant: 0 - category: Processor created: May 22, 2008 description: "===== \n HiCoVec - a configurable SIMD CPU =====\n\nThe HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD operations.\n\nThe amount of data simultaneously processed in the vector unit can be configured as well as the amount of vector registers to hold the data. It is also possible to activate/deactivate some functions (like hardware multiply) of the CPU to gain performance or decrease logic required.\n\nThe processor has its own instruction set. One instruction word is divided into a scalar and a vector part. This makes it possible to execute two commands (each in one unit) at the same time. It is also possible to execute commands that require cooperation of scalar and vector unit.\n\nThe processor comes with its own on-chip-debugging-unit as well as an assembler. It has been validated and tested in a Xilinx Spartan 3 FPGA.\n\nHiCoVec was originally developed within the scope of Harald Manske's diploma thesis under the guidance of Prof. Dr. Gundolf Kiefer. It is further developed at the Computer Engineering Lab at the University of Applied Sciences in Augsburg. \n\nMore information and the latest updates can be found here: http://www.hs-augsburg.de/~kiefer/hicovec\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- standalone 32 bit scalar cpu\n\n- configurable vector extension\n\n- memory interface for SRAM\n\n- on-chip debugging unit\n\n- assembler availiable\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nHiCoVec is validated and ready to use!\n\nThere still is documentation that has to be translated into english. However, the most important documents are done.\n \n\n\n \n \n \n\n===== \n Instructionset =====\n\n- SCALAR COMMANDS:\n - LD - load\n - ST - store\n - ADD - add\n - ADC - add with carry\n - INC - increment\n - SUB - subtract\n - SBC - subtract with carry\n - DEC - decrement\n - AND - logic and\n - OR - logic or\n - XOR - logic xor\n - LSL - shift left, insert 0\n - LSR - shift right, insert 0\n - ROL - shift left, insert carry\n - ROR - shift right, insert carry\n - MUL - multiply (optional command)\n - JMP - jump\n - JAL - jump and link (for subprograms)\n - JZ - jump if zero \n - JNZ - jump if not zero\n - JC - jump if carry\n - JNC - jump if not carry\n - CLZ - clear zero\n - SEZ - set zero\n - CLC - clear carry\n - SEC - set carry\n - HALT - stop execution of commands\n - NOP - no operation\n\n- VECTOR COMMANDS:\n - VNOP - no vector operation\n - MOV - copy data from vector to scalar unit\n - MOV - copy data from scalar to vector unit\n - MOVA - copy data k times into vector unit\n - VLD - vector load \n - VST - vector store\n - VMOV - copy vector registers\n - VMOL - shift datawords in vector register one word left\n - VMOR - shift datawords in vector register one word right\n - VADD - vector add\n - VSUB - vector sub\n - VAND - vector logic and\n - VOR - vector logic or\n - VXOR - vector logic xor\n - VLSL - vector shift left, insert 0\n - VLSR - vector shirt right, insert 0\n - VMUL - vector multiply\n - VSHUF - shuffle data of two vector registers" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - hmanske - kiefer name: hicovec status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 25, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Jul 10, 2003 description: "===== \n Description =====\n\nBefore You read\nThis is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed algorithms please refer to the full article... (see PDF file from downloads).\n\nOverview\nOperation of multiplication is very important in microelectronics. Each modern microprocessor has this operation within its instruction set, and advanced microprocessors have special multiplication units, that perform multiplication during 1 synchronization period(cycle). Especially valuable multiplication is in DSP processors, where it is practically main operation. Performance of any DSP processor is defined with delays in it MAC (multiply and accumulate) unit. So efficiency of multiplication is very important.\n\n\n\n\nMethodology Overview.\nThe idea of algorithms is as follows. Unsigned multiplicands A and D may be represented in following form: A*D = (B * 2n + \xC3\xB3) * (E * 2n + F), where n \xE2\x80\x93 any number that is satisfied with following conditions:\n\n2n 2n \xC3\xB3 n; \nF n.\n\nThis approach is applied recursively to all multiplicands until multiplication result may be calculated easily (for example, until multiplicands have dimension of one or two bits). \n\n\n\n\xC2\xABHierarchical\xC2\xBB algorithm.\nAs it follows from theory of algorithms maximum of timing efficiency should be expected when dimensions of operands B, C, E and F (see basic formula) are equal at every algorithm call, i.e. n=m/2. In this case number of recursions will be minimal and number of sums that take part in final result also will be minimal.\n\n\n\n\nModified \xC2\xABhierarchical\xC2\xBB algorithm.\nThis algorithm is an attempt to improve \xE2\x80\x9Chierarchical\xE2\x80\x9D algorithm for long-dimensional operands by substitution of one multiplication with some of addition operations. But for dimensions commonly used (8 - 64 bit) the result was not as expected. Algorithm advantages supposed to appear on m \xE2\x86\x92 [128..\xE2\x88\x9E) where possibly the algorithm may be preferable than the prototype. \n \n\n\n \n \n \n\n===== \n Features =====\n\n \"Hierarchical\" integer multiplication unit characteristics\nThe algorithm was written in VHDL, synthesized within Synopsys Design Compiler on 0.35u CMOS library. The data of the allocation areas are given only for a combinational part of algorithm.\n\n\t OperandsWidth\n\t Delay(ns)\n\t Gates allocated\n\n\t8\n\t9.56\n\t760\n\n\t16\n\t15.15\n\t2505\n\n\t32\n\t23.12\n\t9355\n\n\t64\t\n\t35.43\n\t33805\n\n\n\n\n\n\"Optimized Hierarchical\" multiplication IP core characteristics\nThe algorithm was written in VHDL, synthesized within Synopsys Design Compiler on 0.35u CMOS library. The data of the allocation areas are given only for a combinational part of algorithms.\n\n\t Operands Width\n\t Delay(ns)\n\t Gates allocated\n\n\t8\n\t14.28\n\t1015\n\n\t16\n\t21.76\n\t3585\n\n\t32\n\t33.85\n\t11240\n\n\t64\t\n\t56.48 \n\t30368\n\n\n \n\n\n \n \n \n\n===== \n Links =====\n\nThese cores are developed and provided by ASIC reseach department member of DeverSYS Corp., Vladimir V.Erokhin. More usefull fundamental (and not only) FREE IP Cores can be found at DeverSYS web www.deversys.com." language: VHDL license: unknown maintainers: - vladvas name: hierarch_unit status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Crypto core created: Jan 21, 2015 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - chetu177 name: high_performance_rc6_algorithm status: Empty updated: Jan 21, 2015 wishbone-compliant: 0 - category: Testing / Verification created: May 13, 2014 description: "===== \n Description =====\n\nThe project is intended for checking FPGA-based device for high consumption power.\nNumber of parameter gives possibility to change number of used LC/DFF, DSP, RAM and I/O.\nIt can operate at 200 MHz in Cyclone 5E FPGA.\n1 LC core is about 1500 LUT4/FF (with default parameters)\n1 DSP core is 7 DSP 18*18.\nEach LC core also demands 4*N RAM blocks (32 bits width).\n\nTo maximize power consumption:\n1) Find parameters for maximum FPGA resource usage\n2) Fed maximum frequency clock to CLK input (directly or via PLL instantiated in top level)\n3) Fed random data to inputs (lower ADC bits or data from PRBS generator)\n4) Connect maximal outputs count. Be careful: They are switching simultaneously.\n\n**** USE HIGH LOAD PROJECT AT YOUR OWN RISK ****" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - alexadmin name: highload status: Beta svn-updated: Mar 11, 2015 updated: Feb 19, 2015 wishbone-compliant: 0 - category: Crypto core created: Nov 5, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - truemind - ellakim name: hight status: Planning svn-updated: Apr 20, 2015 updated: Feb 20, 2015 wishbone-compliant: 0 - category: DSP core created: Dec 28, 2008 description: "===== \n Description =====\n\nThe Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented.\nThe detailed discussion can be found in \"Digital Hilbert Transformers or FPGA-based Phase-Locked Loops\" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). \n\nThe design is fully pipelined for maximum throughput. \n\n\n\n\n\n\n\nIf you find something interesting, feel free to contact me: pluto[at]ls68.de" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - plutonium name: hilbert_transformer status: FPGA proven svn-updated: Apr 5, 2013 updated: Apr 3, 2013 wishbone-compliant: 0 - category: Processor created: Jun 22, 2013 description: "===== \n Description =====\n\nQuick link to the Excel simulator v06.01: http://www.mediafire.com/download/4vy7d202xu7fdbs/HIVE_SIM_2014-10-08.xls\nQuick link to the design document v06.01: http://www.mediafire.com/view/ghtn03wqe4a6k0z/Hive_Design_2014-07-15.pdf\nQuick link to the SystemVerilog code v06.01: http://www.mediafire.com/download/9iloxic8535cdt7/HIVE_SV_2014-07-13_v06.01.zip\n\nv06.01 - 2014-07-13\n- Major changes in hive_main_mem.sv to support 16 & 32 bit aligned and unaligned access for literals and memory R/W.\n- Main memory BRAM now a dual entity to provide separate addressing of high and low and to circumvent bootcode init issues.\n- R/W immediate field offset is based on 16 bit access.\n- New / different opcodes:\n - op_cpy_ls : 16 bit copy low signed\n - op_cpy_lu : 16 bit copy low unsigned\n - op_lit : 32 bit literal \n - op_lit_ls : 16 bit literal low signed\n - op_lit_lu : 16 bit literal low unsigned\n - op_mem_ir : 32 bit memory read\n - op_mem_irls : 16 bit mememory read low signed\n - op_mem_iw : 32 bit mememory write\n - op_mem_iwl : 16 bit memory write low\n- Some juggling of opcode order to hopefully ease decode.\n- hive_alu_logical.sv rearranged a bit, removed a and default path.\n- Passes all boot code verification & functional tests.\n\n=============\n\nQuick link to the SystemVerilog code v05.04: http://www.mediafire.com/download/zry439dg14rz6ab/HIVE_2014-06-13_v05.04.zip\n\nv05.04 is now written in synthesizable SystemVerilog! Lots of minor edits, magic numbers are all in packages.\n\n=============\n\nQuick link to the Excel sim v05.03: http://www.mediafire.com/download/ypii57k6c6z713h/HIVE_SIM_2014-06-08.xls\nQuick link to the verilog code v05.03: http://www.mediafire.com/download/1niwno3c2ncnbxq/HIVE_2014-06-07_v05.03.zip\nQuick link to the design document v05.03: http://www.mediafire.com/download/1tjszeo0kmy14ym/Hive_Design_2014-06-07.pdf\n\nv05.03 has more extensive interrupt support, 32 bit register access, and an updated design document. Footprint is a bit smaller and top speed is a bit faster than previous versions due to cleanup / rewrite / edits. \n\n=============\n\nWith v04.05 Hive now has 8 stacks per thread and a UART!\n\n=============\n\nHive is a general purpose soft processor core intended for instantiation in an FPGA when CPU functionality is desired but when an ARM or similar would be overkill. The Hive core is complex enough to be useful, with a wide data path, a relatively full set of instructions, high code density, and good ALU utilization \xE2\x80\x93 but with very basic control structures and minimal internal state, so it is simple enough for a human to easily grasp and program at the lowest level without any special tools. It fits in the smallest of current FPGAs with sufficient resources left over for peripherals (as well as other unrelated logic) and operates at or near the top speed of the device DSP hardware.\n \nHive isn\xE2\x80\x99t an acronym, the name is meant to suggest the swarm of activity in an insect hive: many threads sharing the same program and data space, individually beavering away on separate tasks, and cooperating together to accomplish larger goals. Because of the shared memory space, thread intercommunication is facilitated, and threads can all share a single instance of code, subroutines, and data sets which enables code compaction via global factoring.\n\nThe novel hybrid stack / register construct employed reduces the need for a plethora of registers and allows for small operand indexes in the opcode. This construct, coupled with explicit stack pointer control in the form of a pop bit for each stack index, minimizes the confusing and inefficient stack gymnastics (swap, pick, roll, copying to thwart auto-consumption, etc.) normally associated with conventional stack machines, and also minimizes the saving and restoring of register contents normally associated with conventional register machines.\n\nHive employs a naturally emergent form of multi-threaded scheduling which eliminates all pipeline hazards and provides the programmer with as many equal bandwidth threads \xE2\x80\x93 each with its own independent interrupt \xE2\x80\x93 as pipeline stages. Processors that employ this form of pipelining are classified as \xE2\x80\x9Cbarrel\xE2\x80\x9D processors.\n\nHive is a largely stateless design (no pipeline bubbles, no registered ALU flags that may or may not be automatically updated, no reserved data registers, no pending operations, no branch prediction, etc.) so subroutines require no overhead and interrupts consume a single branch cycle, and their calculations can be performed directly and immediately with complete disregard for what may be transpiring in other contexts." language: Verilog license: unknown maintainers: - ericw name: hive status: Stable svn-updated: Sep 16, 2014 updated: Oct 10, 2014 wishbone-compliant: 0 - category: Processor created: Mar 28, 2002 description: "===== \n Description =====\n\nHyperMTA is a multithreaded processor capable of having up to 256 threads. In today's super computing/high end world more and more processors are going to multithreading to get a performance benefit. More and more applications are also becoming multithreaded and for that reason we are designing a super computing/high end computing processor and its chip sets. The system is organized in such a way that each processor will interface to one memory router. Each memory router connects to several other memory routers making it possible to access any of a number of memory banks instantly. The design also enables us to implement a memory routing system that will take many clock cycles to access. Each processor is implemented with a vliw instruction set and contains no cache in order to prevent corruption of data between cross accesses to memory banks. Though each memory router has a cache of it's own current memory bank. This system will make for an easy to implement high speed/high performance computer. When the chips are finished we will design example schematics for using xilinx fpga's to implement such a computer. We will also take on writing the compiler/assembler and an operating system for this chip.\n \n\n\n \n \n \n\n===== \n Status =====\n\nPreliminary Specifications available on CVS just checkout the hmta directory or visit:\n\n http://www.opencores.org/cvsweb.shtml/hmta/docs/\n\nComments are wanted: ali@alikat.org\n\nMuch is missing, mainly the little details that make all the difference ;) but I will post it ASAP. I have little snippets that I have typed about things and the instruction set, the rest of the specifications is still in my head. Any suggestions on opcodes will be great.\n \n\n\n \n \n \n\n===== \n Jobs =====\n\nHere are a current list of jobs wanted for this project:\n\n- This is an opensource project, I'm doing this because I feel like it, please can the capitalists stop asking how much I will pay them. If that was the case I would start a company. Secondly, You can do this and gain experience and have a reference for when you apply for a job.\n\n- If you fit multiple descriptions listed below just list that in your email. Don't forget to either list/give links to projects you have worked on.\n\n- I really need programmers rather than designers now. Although designers are still welcome.\n\nVerilog Designer: Experiance in CPU design required RISC, CISC, LIW, or VLIW. Or in FPU or Vector co-processor design. Please email me at ali@alikat.org.\n\nVerilog Designer: Experiance in high speed interconnect networks or in hardware routing chips. Please email me at ali@alikat.org.\n\nVerilog Designer: Experiance in high speed busses. Please email me at ali@alikat.org.\n\nVerilog Designer: Other fields of experiance are welcome please email me at ali@alikat.org and list some of what you have worked on.\n\nProgrammer: Compiler designer for VLIW instruction set wanted. Experience in compiler design is recommended. Email me at ali@alikat.org.\n\nProgrammer: Assembler designer for VLIW instruction set wanted. Experience wanted. Please email me at ali@alikat.org.\n\nChips Needed to be designed:\n- HyperMTA Processor\n- Memory Interconnect Controller (Memory interface to DDR/QDR)\n- Processor Control Network Controller\n- Device controller bridge\n- Devices such as ethernet, vga console, serial console/serial port, etc. Many of these will be taken from already done projects on the open cores website and will be interfaced with a device controller bridge.\n\nSoftware Needed to be designed:\n- Assembler/Compiler\n- Operating System" language: Verilog license: unknown maintainers: - alikat - sumeetsuri - darrin - yyzbest - harshit - nihar name: hmta status: Empty svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Sep 1, 2005 description: "===== \n ToDo =====\n\n- Isolate bus-controlling logic from Monolithic control-unit fsm \n- adding support for other SoC buses (atleast AMBA) \n- 2-pass assembler design (still pending).\n \n\n\n \n \n \n\n===== \n Description =====\n\nSimple 16-bit microprocessor, 16-general purpose registers. custom instruction set, load-store RISC but current implementation \"impl0\" non piplined, control unit hardwired, 64K address space, total 16-interrupts (10 maskable), memory mapped i/o. Design wishbone (wb b.3) compatible bus cycles (currently single read/write), soon will add RMW. RTL (VHDL) completed & posted working for Verilog, prelim. documentation posted. Testing, fpga provening in progress and working for 2-pass assembler design (require your help!). The customized instruction set is mostly dervied from x86 subset. Also for procedure call and return follow x86 conventions, for interrupt handling use hybrid msc51 and x86 style. Due to these conventions pipelined impl would be difficult (any ideas...). Since many implementations are possible, these implementations will be organized as \"impl\", currently \"impl0\" specs and its vhdl implementation is completed, i'm also working for verilog version of \"impl0\". \n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 16-bit Load-store RISC\n- 64K addressable memory\n- total 16 interrupts, 10 available to user\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- RTL (VHDL) complete, also trying for verilog\n- testing (almost!) complete\n- not fpga proven" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - umairsiddiqui name: hpc-16 status: Design done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Other created: May 1, 2012 description: "===== \n Description =====\n\nI will not be working on this project at all.\nThere should be a way to delete the project if the developer wishes to.\nOne way traffic is highly irritating !!" language: Other license: unknown maintainers: - kaluoota name: hpc_openrisc_noc status: Empty updated: May 24, 2013 wishbone-compliant: 0 - category: Memory core created: Oct 26, 2008 description: "===== \n Description =====\n\nHPDMC is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\nFast DDR SDRAM controller with features targeted at high-bandwidth burst-oriented applications such as live video processing. The core has been re-used by several projects and institutions, such as the NASA as part of a software-defined radio system for the ISS (CoNNeCT experiment).\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Current design is targeted at 32-bit wide DDR SDRAM.\n- Dedicated non-standard high-speed bus for efficient memory access (FML).\n- Pipelined accesses to hide DRAM latencies.\n- WISHBONE to FML bridge available with cache support.\n- FML arbiter with pipelining support available for high-speed DMA.\n- Fully synchronous controller (memory clock = controller clock) to avoid clock domain crossing latencies.\n- CSR bus interface for configuration.\n- Low level interface to the SDRAM chip is possible (\"bypass\" mode).\n- SDRAM initialization sequence performed by the system CPU to save hardware resources and maximize flexibility.\n- Timing parameters configured at runtime.\n- Page hit detection supports multiple open banks.\n- Automatic refresh with programmable refresh interval.\n\n \n\n\n \n \n \n\n===== \n Technical documentation =====\n\n- HPDMC specifications\n- CSR bus specifications\n- FML bus specifications" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: hpdmc status: FPGA proven svn-updated: Aug 26, 2010 updated: Aug 26, 2010 wishbone-compliant: 0 - category: Memory core created: Feb 19, 2008 description: "===== \n Description =====\n\nHSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.\n\nHSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. \n\nHSSDRC IP core is licensed under MIT License\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe main features of HSSDRC IP core are :\n\n- Adaptive SDRAM bank control: command sequence is depending upon previous accesses to the RAM.\n\n- Adaptive command pipeline control: bank control commands for following memory access commands are pipelined into previous command processing chain whenever possible.\n\n- Controller structure is adapted to SDRAM parameters referenced by static timings as parameters\n\n- Configurable time interval for bus turnaround (BTA)\n\n- Overlapping command and data processing\n\n- Variable transaction burst from 1 to 16\n\n- Full SDRAM bandwidth usage for linear sequential access without bus turnaround, bank or row change\n\n- Interfaces configurable via parameters\n\n- Registered input and output control signals except command response line\n\n- Registered data control signals\n\n- Internal timer for auto-refresh process\n\n- Two configurable auto-refresh windows\n\n- Internal logic for transaction ordering ID tags\n\n- Flexible choose of trade-offs between bandwidth/frequency/resources\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested in software simulation with Modelsim \n\n- Some synthesis results: \n - Quartus 7.2sp1 Cyclone II 710LC @ 144MHz (full performance) \n - Quartus 7.2sp1 Cyclone II 630LC @ 185MHz (least performance) \n\n\n \n\n\n \n \n \n\n===== \n TODO =====\n\n- Test in hardware with Altera Cyclone II/III and Xilinx Spartan3e FPGA\n\n- Create common ram wrappers for use HSSDRC IP Core \n\n- Create wishbone interface unit for use HSSDRC IP Core \n\n- Create AMBA AXI interface unit for use HSSDRC IP Core \n\n- Create DDR/DDR2 memory controllers IP Core based upon HSSDRC IP Core" language: Verilog license: MIT licenselink: http://opensource.org/licenses/MIT maintainers: - des00 name: hssdrc status: Design done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Dec 8, 2005 description: "===== \n Description =====\n\nA HyperTransport Tunnel controller written in SystemC. HyperTransport (HT) is a high-performance chip-to-chip interconnect architecture. A tunnel has two HT ports to allow it to be used inside a chain of components.\n\nMore information about HyperTransport can be found at the HyperTransport Consortium web site.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Written in synthesisable SystemC\n- Designed with the HyperTransport 2.0b specification\n- Core configurable options include:\n - Retry mode\n - DirectRoute\n - In-vc packet reordering\n - Extendable configuration register space\n - Buffer size\n - Either internal or external deserializer data alignment\n - 2, 4 or 8-bit link support\n- Platform independent\n- Throughput of 32 x Core Frequency bits/s (An FPGA running at 100 Mhz could have an 8-bit link at 400 MT/s, an FPGA running at 75 Mhz could have a 4-bit link at 600 MT/s or an ASIC running at 250Mhz could have an 8-bit link running at 1000 MT/s)\n \n\n\n \n \n \n\n===== \n Status =====\n\n- High level documentation currently being worked on\n- Complete, but not prototyped\n- There are many testbenches, most of them are self-checking but others only produce output that must be manually inspected. The testbenches were designed to quickly validate the design, not for full coverage of limit cases.\n \n\n\n \n \n \n\n===== \n Acknowledgements =====\n\nThis project was done at l'\xC3\x89cole Polytechnique de Montr\xC3\xA9al in the microelectronic research group (Groupe de recherche en micro\xC3\xA9lectronique - GRM) by Ami Castonguay and Yvon Savaria, in collaboration with Bernard Racine, Jean-Fran\xC3\xA7ois B\xC3\xA9langer and many others. Financial support was provided by the National Sciences and Engineering Research Council of Canada. Tools support was provided by CMC Microsystems." language: C++ license: Mozilla Public License Version 1.1 licenselink: https://www.mozilla.org/MPL/1.1/ maintainers: - acastong name: ht_tunnel status: Design done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Dec 18, 2009 description: "===== \n Description =====\n\nHuffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the code have to adapt. \n\nThe state machine is controlled by the jpeg baseline markers.\n Jpeg header is parsing for quantization and Huffman tables. It is re-programmable in each picture header. The implementation of dynamic Huffman table is very practical. If no information in the header is found the tables from the last picture are used again. \nIn the stream the stuffing bits are removed and recognized the codeword and after catch the mantissa bits.\nThis bits are used together with the quantization table to calculate the coefficients in the matrix.\n\nHigh speed decoding for streaming application. After the End maker 0xFFD9 the decoder is restarted for decoding the next picture.\n\n\n Simple 8Bit CPU input interface for small softcores." language: VHDL license: custom licensetext: "If you use this code for simulation there are only one restrictions. You have to mention the core \norigin in your documentations and publications in a valuable position. Of cause you can send me \nalso a publication.\nIf you fit this code into hardware components like FPGA, ASIC or analogous proceeding then is the \nlicense GPL. \nIt is not allowed to put this code with commercial code together in hardware. If you have a problem \nwith this restriction you can contact me.\n" maintainers: - dose name: huffmandecoder status: Alpha svn-updated: Dec 29, 2009 updated: Nov 14, 2011 wishbone-compliant: 0 - category: Testing / Verification created: Jul 9, 2013 description: "===== \n Description =====\n\nThis project aims to create a synthesisable coverage-driven constrained randomisation testbench library. The core uses the hardware TLM approach for bus interfaces between the tester and the DUT. Many concepts used in this project are similar to the OS-VVM framework, such as the intelligent coverage methodology, only that we have made them synthesisable to hardware so this library can be reused as hardware testers in hardware testbench environments." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: hw_cov_crv status: Empty updated: Jul 9, 2013 wishbone-compliant: 0 - category: Other created: Apr 16, 2004 description: "===== \n Hardware looping unit =====\n\nTha main purpose of the hardware looping unit (HWLU) is to enhance program control units found in modern microprocessors, by efficiently handling loop increments and branches in nested loop structures. It is based on recently published work (details can be found in the specification document). The main advantage of the presented architecture is that successive last iterations of nested loops are performed in a single cycle. This architecture can be useful in the case that all data processing in context of a nested loop structure is performed in the inner loop, which is rather often in multidimensional signal processing applications as performance-critical code in image coding and video compression standards.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nFind more details at:\nhttp://www.nkavvadias.com\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- status1\n- status2" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - kavi name: hwlu status: Stable svn-updated: Apr 3, 2010 updated: Jul 9, 2011 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Description =====\n\nI2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol.\nThe OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus.\nIt is an easy path to add I2C capabilities to any Wishbone compatible system.\n\nYou can find the I2C specifications on Phillips web Site. \nWork was originally started by Fr\xC3\xA9d\xC3\xA9ric Renet. You can find his webpage here. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Compatible with Philips I2C bus standard\n- Multi-Master Operation\n- Software programmable timing\n- Clock stretching and wait state generation\n- Interrupt or bit-polling driven byte-by-byte data-transfers\n- Arbitration lost interrupt, with automatic transfer cancelation\n- (Repeated)Start/Stop signal generation/detection\n- Bus busy detection\n- Supports 7 and 10bit addressing\n- Fully static and synchronous design\n- Fully synthesisable\n \n\n\n \n \n \n\n===== \n Documentation =====\n\n- Revision 0.8 of the WISHBONE I2C Master Core specifications are available here.\n- Also see the FAQ page.\n \n\n\n \n \n \n\n===== \n Licensing =====\n\nCheck the FAQ page for information regarding Philips I2C/SMBus licensing information.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Design is available in VHDL and Verilog from OpenCores SVN via this link\n\n \n\n\n \n \n \n\n===== \n Synthesis results =====\n\nPush-button synthesis results for various targets.\n\nActel:\n- A54SX16ATQ100-std: 352Modules@58MHz\n\nAltera:\n- FLEX: EPF10K50ETC144-3: 294LCELLs@82MHz\n- ACEX: EPF20K30ETC144-3: 257ATOMs@74MHz\n\nXilinx:\n- Spartan-II: 2S15CS144-5: 229LUTs@82MHz\n- Virtex-E: XCV50ECS144-8: 230LUTs@118MHz\n \n\n\n \n \n \n\n===== \n Users =====\n\n- CATC \"Computer Access Technology Corporation is a user and supporter of the OpenCores I2C Soft IP Core\"" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - rherveille name: i2c status: ASIC and FPGA proven svn-updated: Jun 6, 2010 updated: May 5, 2015 wishbone-compliant: 1 - category: Communication controller created: Apr 22, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: SystemC license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: i2c_bus_using_systemc status: Empty updated: Apr 23, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Dec 30, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qzh name: i2c_core_vhdl status: Empty updated: Dec 30, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Jan 7, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jimmy_tag name: i2c_master_apb_interface status: Empty updated: Jan 7, 2014 wishbone-compliant: 0 - category: Communication controller created: Jan 12, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - prasadp4009 name: i2c_master_controller_apb_bridge status: Empty updated: Jan 13, 2014 wishbone-compliant: 0 - category: Communication controller created: Oct 29, 2008 description: "===== \n Description =====\n\nSince lots of people ask me questions about my core, i want to clarify some things:\n1) the master works, the slave is not entirely thought-through, i used it in simulation only.\n2) i'm adding a diagram, that explains how to control the core.\n3) adding a file name i2c_master_v01.vhd, that containes the master only.\n4) since i have some time now, i will try to work on the slave.\n\nhave fun!\nEli.\n\nThe file name is V02 because V01 contained only an unwilling to work master.\nit will not be posted here.\nMaster:\n *supports burst writes and reads\n *fully controlled by interface\nfor now i build a different interface for each use of the core.\nin he future i plan to build a generic controller, that will act as a bridge from the PCI PLB to I2c." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - vassago057 name: i2c_master_slave status: FPGA proven svn-updated: Jun 5, 2012 updated: Jun 10, 2012 wishbone-compliant: 0 - category: Communication controller created: May 22, 2008 description: "===== \n Description =====\n\nDescription of project..\n\nThis design is Wishbone compatible I2C core. This core can work as I2C master as well as slave.\nVMM Test-bench is also available.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nBoth Master and slave operation\n\n Both Interrupt and non interrupt data-transfers\n\n Start/Stop/Repeated Start generation\n\n Fully supports arbitration process\n\n Software programmable acknowledge bit\n\n Software programmable time out feature\n\n programmable address register\n\n Programmable SCL frequency\n\n Soft reset of I2C Master/Salve\n\n Programmable maximum SCL low period\n\n synthesis core\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nDesign: Done\nVMM based verification Environment Creation: Done" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - toomuch name: i2c_master_slave_core status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Communication controller created: Apr 22, 2013 description: '' language: SystemC license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - prabu28 name: i2c_protocol status: Empty updated: May 20, 2013 wishbone-compliant: 0 - category: Communication controller created: May 19, 2010 description: "===== \n Description =====\n\nI2C slave to WishBone master interface." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qaztronic name: i2c_to_wb status: Alpha svn-updated: Mar 29, 2011 updated: Sep 15, 2010 wishbone-compliant: 1 - category: System on Chip created: Nov 3, 2008 description: "===== =====\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nShort: virtually convert an I2C slave into a WISHBONE slave\n\nThis is a wrapper for the I2C controller core by Richard Herveille (http://opencores.org/project,i2c) which transparently converts a WISHBONE transaction into an I2C operation.\n\nExample: a WB read/write of the WB address 09h of this core would schedule and execute the (long) list of commands needed to make an I2C read/write of reg 09h of an I2C device connected to the I2C controller core in OpenCores, and return the result transparently into the WB bus.\n\nIMPORTANT: The current wrapper is for 16 bits I2C slaves, that is I2C reads and writes are composed of two bytes.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- WISHBONE wrapper for the \"I2C controller core\" by Richard Herveille\n- Fully transparent I2C WISHBONE operation\n - A WB read/write of address X becomes an I2C read/write of reg. X and the I2C slave's response is sent back to the WB bus.\n- Designed for 16 bits I2C slaves\n- FPGA proven and works perfect (if you run into problems: take into account this I2C controller's bug solution: http://www.opencores.org/ptracker.cgi/view/i2c/370 )\n- Limitations: the I2C slave's address is fixed, so that it may be used to control only one slave (can be overriden with minor modifications).\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 03/11/2008: Project created on OpenCores" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - galland name: i2c_wb_wrapper status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Communication controller created: Dec 21, 2009 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - siva12 name: i2cgpio status: Alpha svn-updated: Dec 22, 2009 updated: Dec 21, 2009 wishbone-compliant: 0 - category: Testing / Verification created: Dec 7, 2009 description: "===== \n Description =====\n\ni2clcd is a minimalist i2clcd IP core that provides the basic framework for the implementation of custom i2clcd devices. The core provides a means to write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. A full Icarus Verilog test bench is available. Test it for yourself, using the free Icarus Verilog simulator and the free GTKWave wave form viewer.Download and install Icarus Verilog. - Download and install GTKWave. - Download the project files. - For executing the testbench just run the Makefile on the bench folder.In GTKWave, use \"Search >> Signal Search Tree\" to view more waves.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Standalone. No microprocessor required. For master side we need an microntroller\n- Create your own custom i2clcd peripheral.\n- Easily configurable for different input clock frequencies.\n- Full Icarus Verilog test bench.\n- This is to be tested with Our Zkit-51( 8 bit microcon board),a lcd(16x2) and Xilinx Spartan 3A FPGA board\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- To be tested in Zkit - 51 (8 bit microcontroller board) with Xilinx Spartan 3A FPGA board and (16x2) LCD\n- To be tested in simulation\n- To be tested waveform in GTK wave" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - siva12 name: i2clcd status: Planning svn-updated: Dec 22, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Jul 25, 2003 description: "===== \n FEATURES =====\n\n- Captures I2C 2 wire serial bus activities into an external RAM\n- Applicable to Atmel 2 wire serial bus format:\n This includes (1) Random byte write\n (2) Page write\n (3) Random byte read\n (4) Multiple start\n- End of a transition after the stop bit is followed by an 8 bit count for simple time stamp.\n- Code witten for 32K byte capacity, can be modified to higher capacity.\n- Requires an external 2MHz to 5MHz clock. \n \n\n\n \n \n \n\n===== \n I2C Bus Traffic Logger =====\n\nDESCRIPTION\n\n Two wire serial I2C bus is designated as the communication standard in physical layer (PHY) transponders for link status monitoring purposes. The host routinely queries the transponder for informations such as errors, temperatures and configuration settings. The host also exercise controls to the transponder by writing into registers. \n\n A complete specification of I2C bus can be found in Philips semiconductor web site semiconductors.philips.com/buses/i2c/index.html) . The implementation of the I2C bus protocol varies with vendors. This traffic logger dsign is compliant to the ATMEL serial EEPROMS data 2 wire serial bus format. \n\n The use of a bus traffic log is primarily for monitoring and diagnostic link failures. In order to be useful, the traffic logger has to be able to capture large volumes of time stamped transactions for analysis.\n\n \n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Project started" language: Verilog license: unknown maintainers: - blackdiamond name: i2clog status: Mature svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Jul 6, 2011 description: "===== \n Description =====\n\nThis is a quick module I hacked together to connect two I2C buses to work around a hardware bug on a board.\n\nIt mostly works, and I'm posting it in case others find it useful. I wouldn't use it in a production system as it stands.\n\nIt is written in SystemVerilog, so you'll need to change some \"logic\" declarations to \"reg\" if your compiler can't handle SystemVerilog. There are probably some other SystemVerilog features used, also.\n\nI suggest toggling the reset signal between I2C transfers, if possible." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - egallimore name: i2crepeater status: Beta svn-updated: Jul 7, 2011 updated: Nov 28, 2011 wishbone-compliant: 0 - category: Communication controller created: Nov 7, 2008 description: "===== \n Description =====\n\ni2cSlave is a minimalist I2C slave IP core that provides the basic framework for the\nimplementation of custom I2C slave devices. The core provides a means to read and write\nup to 256 8-bit registers. These registers can be connected to the users custom logic,\nthus implementing a simple control and status interface. A full Icarus Verilog test bench is available. \nTest it for yourself, using the free Icarus Verilog simulator and the free GTKWave wave form viewer. Only 6 simple steps!\n- Download and install Icarus Verilog.\n- Download and install GTKWave.\n- Download the project files. \n- Execute sim/build_icarus.bat and sim/run_icarus.bat\n- Execute sim/viewWave.bat and check out the results.\n- In GTKWave, use \"Search >> Signal Search Tree\" to view more waves.\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Standalone. No microprocessor required.\n- Create your own custom I2C peripheral.\n- Only 143 macrocells in CPLD.\n- I2C bus speeds of 100Kbps and 400Kbps.\n- Easily configurable for different input clock frequencies.\n- Full Icarus Verilog test bench.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested in FPGA\n- Tested in simulation\n \n\n\n \n \n \n\n===== \n News =====\n\nNow available, Altera Quartus project for Base2Designs FPGA-DEV-KIT and test software for the\nAardvark I2C Host Adapter. Download the latest project files now." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - sfielding name: i2cslave status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 18, 2013 wishbone-compliant: 0 - category: Communication controller created: Mar 22, 2004 description: '' language: VHDL license: unknown maintainers: - lhou name: i2s status: Design done svn-updated: Mar 10, 2009 updated: Jan 10, 2014 wishbone-compliant: 0 - category: Communication controller created: Jul 28, 2004 description: "===== \n Features =====\n\n- Separate transmitter and receiver.\n- Operates in either slave or master mode.\n- Configurable sample buffer size.\n- Supports 16bit to 32bit resolution.\n- Supports 16bit and 32bit Wishbone data bus.\n- Interrupt capability.\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nI2S is an industry standard (invented by Philips) 3-wire interface for streaming stereo audio between devices. Typical applications include digital audio transfer between a CPU/DSP and a DAC/ADC. The I2S core allows a Wishbone master to stream stereo audio to and from I2S capable devices.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Core is complete and released." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - gedra name: i2s_interface status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 23, 2014 wishbone-compliant: 1 - category: Communication controller created: Jan 20, 2009 description: "===== \n I2S to Parallel Interface =====\n\nThis module provides a bridge between an I2S serial device (audio ADC, S/PDIF Decoded data) and a parallel device (microcontroller, IP block).\n\nIt's coded as a generic VHDL entity, so developer can choose the proper signal width (8/16/24 bit)\n\nInput takes:\n-I2S Bit Clock\n-I2S LR Clock (Left/Right channel indication)\n-I2S Data\n\nOutput provides:\n-DATA_L / DATA_R parallel outputs\n-STROBE and STROBE_LR output ready signals.\n\nAs soon as data is read from the serial I2S line, it's written on the proper parallel output and a rising edge of the STROBE signal indicates that new data is ready.\nSTROBE_LR signal tells if the strobe signal was relative to the left or right channel.\n\nParallel data (DATA_L / DATA_R) remain valid for the whole cycle (until next data is processed)\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Supports arbitrary data width (through the generic width parameter)\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 2009/01/20 : Uploaded Rev 1.0 and Testbench" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - primiano name: i2s_to_parallel status: Design done svn-updated: Mar 10, 2009 updated: Mar 17, 2011 wishbone-compliant: 0 - category: Communication controller created: Mar 28, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qaztronic name: i2s_to_wb status: Planning svn-updated: Mar 29, 2011 updated: Mar 28, 2011 wishbone-compliant: 0 - category: Communication controller created: Dec 17, 2005 description: "===== \n I2S to Paralell ADC/DAC controller =====\n\nThis provides a bridge between a paralell device (such as a microcontroller (uC) and an I2S (!not! I2C) audio bus, generally used for ADC's and DAC's, such as in DVD & MP3 players\n\nNominal target is a CPLD, 128-cell variants will hold the entire project for bidirectional (ADC & DAC) operation simultaneously with 24-bit I/O's. Removing either side or reducing bus width allows operation in 64-cell devices (the core was actually tested in this configuration).\n\nOrigonally written in VHDL for Xilinx ISE - project & constraints file included.\n \n\n\n \n \n \n\n===== \n Caveat =====\n\nThis project may have bugs due to adaptation / cleanup from origonal production core into something of more general interest. Origonal core only used 8 of 24-bits for fitting into 64-cell devices.\n \n\n\n \n \n \n\n===== =====" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - franksdevel name: i2sparalell status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Feb 18, 2015 description: "===== \n Description =====\n\nA Verilog RTL implementation of the venerable IBM 650 computer.\n\n\n\n\nThe goal of this project is to use available source materials to recreate a 650 as accurately as possible.\n\n \n \n\n\n \n \n \n\n===== \n Status =====\n\nUnder active development. Control is currently being implemented and debugged in simulation.\n \n\n\n \n \n \n\n===== \n About the IBM 650 =====\n\nAnnounced in 1953, the IBM 650 was a decimal, digit-serial vacuum tube computer. Main memory was a magnetic drum storing 2000 10-digit signed-decimal numbers. Machine logic was implemented using crystal diodes and vacuum tubes. It was arguably the most popular vacuum tube machine, with almost 2000 650's built and shipped.\n\n\n\n\n\nIBM's practice at the time was to patent their computers in complete detail. US patent 2,959,351, \"Data Storage and Processing Machine\", filed Nov. 2, 1955, granted Nov. 8, 1960, includes complete schematics for the basic IBM 650 CPU, broken into many page-sized pieces. I have reassembled the original drawings and included them in this project.\n\n\n\n\n\nDuring its lifetime, the 650 was upgraded with a number of features, including magnetic tape and RAMAC, one of the first hard drives.\n\n \n \n\n\n \n \n \n\n===== \n Latches to Flip-Flops =====\n\nThis implementation is fully synchronous, using D flip-flops for sequential logic throughout. This has required reworking 650 sequential logic, beginning with basic timing. I have retained a four-phase clock, but with different semantics; all flip-flops are now triggered by the rising edge of one of the clock phases.\n\n\n\n\n\nPhase A is considered a setup phase. Registers RAMs are read during phase A, making their early and on-time outputs available at posedge B, C and D. Timing pulses based on drum angular position are available at all phase posedges.\n\n\n\n\n\nB, C and D phases are available for sequential logic based on values read from register or general storage. RAMs are written during phase D. In the original when multiple latches are cascaded, the cascaded result appears subject to the latch delays. In an equivalent synchronous sequential logic circuit, a full clock delay is imposed for each level of flip-flops. To afford maximum flexibility, the earliest possible posedge is chosen for each individual flip-flop. Paths through cascaded latches constitute the critical paths for the converted implementation; none may exceed 4 levels.\n\n\n\n\n\nAll early pulses, where \xE2\x80\x9Cearly\" indicated a rising edge coincident with the D pulse, have been eliminated. The 650 used these to reset latches and then delay setting until the D pulse of the subsequent digit time, providing reset and ensuring that new inputs had time to settle before latching them." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eightycc name: i650 status: Planning svn-updated: May 2, 2015 updated: Mar 26, 2015 wishbone-compliant: 0 - category: Communication controller created: Nov 14, 2009 description: "===== \n Description =====\n\nComplete implementation\nof i8255 PPI in fpga.\nYou may find some\ndatasheets about here.\nVerilog code has some\nmodules:\nPORTS - matches to the\na,b,c. External world - inout tri-state bus. Internal circuit -\ndatain and dataout buses.\n port c divided by two\nparts - high and low.\nGROUPS - represent\ngroup A and group B like in the real device. Group A controls port A\nand hight 4 bits of port C.\n Group B controls port B\nand low 4 bits of port c.\n Groups connected to\nports with input/output data buses and control lines.\ni8255 core - all\nexternal inputs and outputs like in real device. Operates groups.\nConnected to them with input/output buses.\nDevice doesn't use\nclock! It's main problem in realization. Issue pulls up with\nassignment delay to inout bus in iSim if we try to enable output to\nit from always block.ModelSim handles this stuff just fine.\n\nP.S. Please, read news))\n \n\n\n \n \n \n\n===== \n Why? =====\n\nIt's my first project on the FPGA scene. I want to improve myself in verilog and fpga.\nAnd this project will be good testbench for my parallel project - easy to create simple gui controls( like LEDs, buttons, displays, etc)\nin Python for famous simulators." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Malasar name: i8255 status: Alpha svn-updated: Nov 22, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Dec 16, 2005 description: "===== \n emulating the IC6821 =====\n\nOne day my partern says lets make this old board smaller. But a lot of IC6821. So emulate them into an FPGA. So i developed the code in VHDL. The 6821 is a peripheral from MOTOROLA. It has two bidir ports PA,PB and four interrupt inputs, two of them also can be configured for handshake.\n\n \n\n\n \n \n \n\n===== \n Not time to write yet. =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2\n \n\n\n \n \n \n\n===== \n Status early yet =====\n\n-- On 16 december 2005 i finished the coding and some basing simulation using the QUARTUS web edition.\n \n\n\n \n \n \n\n===== \n FILE: VHDL6821.vhd =====\n\nFILE: VHDL6821.vhd\nDESCRIPTION:" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ttsenis name: ic6821 status: Design done svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Oct 7, 2012 description: '' language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - sleary name: ide2sd status: Empty updated: Oct 21, 2012 wishbone-compliant: 1 - category: Crypto core created: Sep 25, 2001 description: "===== \n Description =====\n\nThe IDEA (International Data Encryption Algorithm) is a symmetric-key block cipher that can encrypts 64-bits plaintexts to 64-bit ciphertexts using a 128-bit key, used for secure communications. It is also can do decryption with the same block using the same key. \n\nIt consists of 8 computationally identical rounds and an output transformation. A 64-bit input block is divided into four 16-bit blocks which become the input blocks to the first round of the algorithm. In each of the eight total rounds, the four sub-blocks are XOR-ed, added, and multiplied with one another and with six 16-bit sub-keys. \n\nIDEA runs 177 Mbps in speed on hardware implementation. \n\nThe IDEA block cipher was found by J. L. Massey and X. Lay.\n \n\n\n \n \n \n\n===== \n Specifications =====\n\n- Operates on 64-bit plain text block \n- Uses 128-bit key \n- Can do encryption and decryption using the same block cipher (like DES). \n- Be referred to be compatible with PCI bus \n- Uses 1 micron technology \n \n\n\n \n \n \n\n===== \n Design stages =====\n\n- Making core specifications\n- Capturing and the verification of the behavioral and structural view using Alliance tools\n- Implementation to symbolic layouts\n- Last verification (current stage)\n- Converting symbolic layouts to real layouts with a specific technology\n- Making the full report\n \n\n\n \n \n \n\n===== \n IMAGE: IDEA core block.GIF =====\n\nFILE: IDEA core block.GIF\nDESCRIPTION: Figure 1. The Block Diagram of IDEA Core\n\n \n\n\n \n \n \n\n===== \n IMAGE: IDEA mechine block.GIF =====\n\nFILE: IDEA mechine block.GIF\nDESCRIPTION: Figure 2. The IDEA Mechine Block\n\n \n\n\n \n \n \n\n===== \n Links =====\n\n- To get files of IDEA core from cvsweb \n- To see the Alliance documentations\n- To download free Alliance tools" language: VHDL license: unknown maintainers: - marta - sarwono - sigit name: idea status: Planning svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Jan 20, 2015 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - prabhat003 name: idea_virtex6 status: Empty updated: Jan 20, 2015 wishbone-compliant: 0 - category: Communication controller created: Jan 7, 2011 description: "===== \n Description =====" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: ieee_802_15_4_phy status: Stable svn-updated: Apr 16, 2013 updated: Jun 10, 2013 wishbone-compliant: 0 - category: Prototype board created: Dec 31, 2009 description: "===== \n Norwegian University of Science and Technology =====\n\nThis project came to be because of the course \"TDT4295 - Computer Design, Project\", due to the Institute of Computer and Information Science at The Norwegian University of Science and Technology. The project was supervised by Assoc. Prof. \nMorten Hartmann\n \n\n\n \n \n \n\n===== \n What is this? =====\n\nIGOR is in a complete system including:\n* A PCB with all the components of the system: FPGA, AVR microcontroller, IO-units, Memory... the works.\n* An implemented processor running on the FPGA.\n* Several IO units, connected to the main processor through an AVR mircrocontroller through a parallel bus.\n\nThe processor is a microprogrammed processor, and the ISA resembles Lisp. The processor running the microprogram is RISC-like, and there are currently two versions in the repository: a multicycle processor which has been run in the FPGA on the full system, and a pipelined processor which has not been tested on development boards.\n\nCalling it a complete LISP-machine at the lowest level is a misnomer, as you might expect. Even though there are some customizations like support for type-checking of operands, the lowest level remains a rather straight-forward MIPS-like RISC machine and the microinstruction-set are not far from what you would come to expect from any RISC processor. Features like all the original LISP-machines had, like hardware-supported GC is not present. The microprogram and thus the ISA, however, is very much a Lisp machine: it implements garbage collection, dynamic typing and many other features one has come to except from a LISP.\n \n\n\n \n \n \n\n===== \n Who contributed, and will it grow? =====\n\nThe original project (hereby dubbed IGORv1) was started by a group of students in the fall of 2008 as a school-project. The project finished successfully. The participants were: \xC3\x98ystein Skarts\xC3\xA6terhagen, William Wai Man Young, Tor Arne Lye, Ruben Spaans, Martin Tverdal, Maria Johansen, Odd Rune S. Lykkeb\xC3\xB8, Ulf Lilleengen, Kjetil W. Oftedal, Kai Hugo H. Endresen, Jens \xC3\x85dne Rydland, Georgy Ushakov, Eirik A. Nygaard, Thomas K. Adamcik.\n\nAfter this project finished, there was an additional project in the fall of 2009, where Odd Rune S. Lykkeb\xC3\xB8 took out the processor implementation and implemented a pipelined design and built a file system.\n\nThe current state of the project is what is available here. There will be more work done on the platform, and everyone is invited to join in if they can manage to get things running. Since we created an original PCB for the project, getting things up and running in a test system is potentially hard to do. Odd Rune will however assist anyone who wishes to do modifications to IGOR and run them on the original PCB. Of course, you're free to print your own-- gerbers and everything is included in the source files." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - atypic name: igor status: Beta svn-updated: Jan 3, 2010 updated: Jan 6, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Oct 27, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - deflypig name: iic_master status: Empty updated: Oct 27, 2011 wishbone-compliant: 0 - category: Prototype board created: Jul 1, 2005 description: "===== \n Description =====\n\nThe IIE-PCI Development Platform board is a low cost PCI device card with a programmable logic chip (Altera ACEX), dynamic ram, and expansion capabilities.\n\nThe main purpose of the IIE-PCI board is to test PCI designs in a educational environment. Cost was a primary concern. The fabrication cost for the prototype board was U$S 330, if 10 boards are made, the cost will drop to U$S 230 per unit.\n\nMore information is available at the project website:\n - http://www.mondueri.com/iiepci (mondueri.com/iiepci) (original site in spanish)\n - http://translate.google.com/translate?u=http%3A%2F%2Fwww.mondueri.com%2Fiiepci&langpair=es%7Cen&hl=es&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools (english version) (google autotranslation)\n\nThe IIE-PCI Development Platform is part of a final degree project in Electrical Engineering in the Universidad del la Rep\xC3\xBAblica - Facultad de Ingenier\xC3\xADa - Uruguay.\nThe whole project contains the following parts:\n - IEE-PCI board.\n - Target PCI Core toolkit (written in VHDL).\n - Linux device driver toolkit for the core and the device card.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- PCI 32 bit, 3.3V and 5V compatible\n - 128Mbit SDRAM memory on-board\n - ALTERA FPGA ACEX EP1K100PQ208\n - Expansion header\n - 31 general propouse signals\n - Clock source: on-board crystal, PCI conector. Jumper selectable.\n - PLL for clock regeneration and frequency multiplication. Jumper selectable.\n - FPGA configuration using (jumper selectable):\n - on-board ALTERA EPC2 EPROM\n - JTAG header through ALTERA ByteBlasterMV\n - External power connector\n \n\n\n \n \n \n\n===== \n Status =====\n\n- two prototype assembled and fully functional\n - boards are being used at under-graduate http://iie.fing.edu.uy/ense/asign/dlp/ (courses) in our University.\n - schematics, gerber, bill of materials available at http://opencores.org/pdownloads.cgi/list/iiepci (Downloads) section\n - documentation, user manual and other information available at http://opencores.org/project,iiepci,links (Links) section\n\n \n\n\n \n \n \n\n===== \n Authors =====\n\n- Sebasti\xC3\xA1n Fern\xC3\xA1ndez | sebfer at opencores.org\n - Ciro Mondueri | ciro at opencores.org\n \n\n\n \n \n \n\n===== \n IMAGE: iie_pci_front.jpg =====\n\nFILE: iie_pci_front.jpg\nDESCRIPTION: IIE-PCI board (front)\n\n \n\n\n \n \n \n\n===== \n IMAGE: iie_pci_back.jpg =====\n\nFILE: iie_pci_back.jpg\nDESCRIPTION: IIE-PCI board (back)\n\n \n\n\n \n \n \n\n===== \n IMAGE: iie_pci_diagram.jpg =====\n\nFILE: iie_pci_diagram.jpg\nDESCRIPTION: IIE-PCI board (diagram)" language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - sebfer - ciro name: iiepci status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: DSP core created: Sep 17, 2011 description: "===== \n Description =====\n\nThe IMA ADPCM audio compression algorithm belongs to the Adaptive Differential Pulse Code Modulation type algorithms. The algorithm is based on a simple adaptive quantization of the difference between the input and a predictor. Each 16-bit input sample is converted to a 4-bit coded information which yields a compression ratio of \xC2\xBC. We will not go through detailed description of the algorithm in this document. There are many online pages describing the algorithm, just Google \xE2\x80\x9CIMA ADPCM\xE2\x80\x9D.\n\nThe main advantage of the IMA ADPCM compression algorithm is its simplicity. The algorithm is not limited to voice signals and can operate at any input sampling rate thus enabling compression of high quality audio as well. \n\nThe implementation in this project does not follow any standard protocol format for the compressed information. The encoder uses a very simple interface to input 16-bit samples and output coded information nibbles (4-bits). A similar interface is used by the decoder to input the coded information nibbles and output 16-bit reconstructed samples. \n\nA bit exact fixed point Scilab implementation of the algorithm is supplied with the core and is used to generate files used during verification. Detailed description of the verification process is given in the Test Bench Description chapter.\n\n." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - motilito name: ima_adpcm_enc_dec status: Stable svn-updated: Sep 23, 2011 updated: Dec 12, 2014 wishbone-compliant: 0 - category: Other created: Nov 5, 2008 description: "===== =====\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.\n\nThe core acts as a slave WISHBONE device.\n\nThe output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. \n\nCompression ratio is fixed for IMA-ADPCM, being 4:1.\n\nPLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes. \n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- IMA ADPCM Compression (4 bits per sample)\n - Input must be 16 bits PCM sound samples\n - Only one channel (mono)\n - Output includes standard WAV headers\n - Selectable sample rate and number of seconds of recording\n- Fully Wishbone compliant core (acts as a Wishbone slave)\n- Testbench included that takes a 16 bits PCM Mono WAV file and writes to disk another WAV file of the sound compressed with IMA ADPCM.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 05/11/2008: Project created" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - galland name: ima_adpcm_encoder status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 27, 2011 wishbone-compliant: 1 - category: System on Chip created: Aug 6, 2014 description: "===== \n INFO =====\n\nThe project is RT level design of image component labeling and feature extraction. The design is captured in VHDL. The architecture is parallel and pipelined.\n\nThe project is posted under LPGL license. User need to give reference to the publishes work when used in design.\n\nHardware Architecture for Real-time Component Feature Descriptors on a FPGA\nAbdul Waheed Malik, Benny Th\xC3\xB6rnberg, Najeem Lawal, Muhammad Imran\npublication in Internal Journal of Distributed Sensors, special issue on\n\xE2\x80\x9CRecent advances in Wireless Visual Sensor Network (WVSN)\xE2\x80\x9D\n\nComparison of Three Smart Camera Architectures for Real-Time Machine Vision\nSystem\nAbdul Waheed Malik, Benny Th\xC3\xB6rnberg and Prasanna Kumar\npublication in International Journal of Advanced Robotic Systems" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - malikpearl name: image_component_labeling_and_feature_extraction status: Mature svn-updated: Sep 28, 2014 updated: Sep 28, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Dec 18, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: implementation status: Empty updated: Dec 18, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Mar 27, 2014 description: '' language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - maheshpalve - mgharish005 - aravindhk name: instruction_list_pipelined_processor_with_peripherals status: Planning svn-updated: Apr 13, 2015 updated: Mar 30, 2015 wishbone-compliant: 0 - category: Video controller created: Nov 16, 2007 description: "===== \n Description =====\n\nThis VHDL macro is a Text Mode Monochrome Video Display Adapter for VGA monitors. It can be used as a peripheral for a soft-processor, external microcontroller or other non-programmable hardware. It's not much better than the original IBM MDA card appeared in 1981 ;-)\n \n\n\n \n \n \n\n===== \n Features =====\n\n- resolution is 80x40 characters, dot resolution is 640x480 pixels at 60Hz so the core needs a clock signal of 25MHz. I prefer 80x40 instead the classical 80x25, in my opinion, the latter is an annoyance.\n- monocrome, it hasn't \"attribute\" memory to store the color of each character. The unique output color is selectable among 8 different colours\n- the video text buffer is an external memory (or BRAM inside the FPGA) of 80\xC3\x9740 = 3200 bytes. The character at (column, row) = (0, 0) is at the RAM address 0, the character at (79, 39) is at 3199. \n- 8-bit ASCII codes (iso-latin-0 or other that you prefer)\n- the ROM that store fixed-width bitmap font is also external, the bitmap can be changed modifying the COE file. The COE file provided is iso-8859-15 (also called iso-latin-0), is very similar to the iso-8859-1 but with the Euro (\xE2\x82\xAC) symbol added.\n- hardware cursor, with two different shapes; with enable/disable control.\n- simple IO interface. Three registers\n - CRX. Position (column) for HW cursor\n - CRY. Position (row) for HW cursor\n - CTL. Control register for de/activate the HW cursor, change its shape, de/activate VGA signal, output colour, etc. \n- uses 100 slices in a Xilinx Spartan-3.\n- the design is vendor-agnostic. You can use it in Xilinx/PicoBlaze, Altera/NIOSII or with other non-programmable hardware. \n \n\n\n \n \n \n\n===== \n Documentation =====\n\nYou can find the documentation for this macro in the downloads section and also at www.javiervalcarce.eu. \n\n\n\n \n\n\n \n \n \n\n===== \n Downloads =====\n\nSee \"Downloads\" in the menu bar. There is VHDL design files plus documentation." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - javg name: interface_vga80x40 status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 11, 2014 wishbone-compliant: 0 - category: Other created: Mar 17, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Bjarneorn name: interrupt_controller status: Mature svn-updated: Mar 21, 2014 updated: Mar 18, 2014 wishbone-compliant: 0 - category: Video controller created: Feb 3, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - HDT name: intra_predection_h264 status: Empty updated: Feb 3, 2012 wishbone-compliant: 0 - category: Processor created: Jan 25, 2011 description: "===== \n WARNING =====\n\nThis project is in the middle of a major refactor, being conducted in a new GitHub repository.\n\nThe refactor involves rewriting from scratch the most intractably messy parts of the RTL (the cache and memory controller and parts of the CPU), implementing Wishbone as the main bus interface and upgrading the core to MIPS32r1 compatibility, among many other changes. The aim is to make the core actually useable.\nEventually the project will be backported here.\n\n\nIn short, I wouldn't recommend paying much attention to this version of the core...\n\n\n \n\n\n \n \n \n\n===== \n Overview =====\n\nThis is a MIPS-I compatible CPU, aiming at compatibility with IDT\xE2\x80\x99s R3000 MIPS derivative.\n\n\n\nKey features:\n\n1. Binary compatible to R3000 series of CPUs.\n2. Kernel/user mode operation as per the architecture definition.\n3. Exception handling compatible to MIPS-I standard.\n4. 4KB direct-mapped code cache.\n5. 4KB direct-mapped, writethrough data cache.\n6. Simplified CP0, mostly compatible to R3000.\n7. All unimplemented opcodes trigger the proper traps.\n8. Includes minimalistic memory handler with interfaces for external SRAM (or FLASH)\non 8- and 16-bit data bus.\n9. Size and speed comparable to other free MIPS cores.\n10. Fully synchronous (rising clock edge only). No latches.\n11. Source HDL is fully vendor independent (Only tested on Xilinx and Altera synthesis\ntools).\n\n\n\nThis project inherits heavily from Steve Rhoads' Plasma, though it is not meant as a replacement or improvement -- the name of this project attempts to convey that idea.\nBesides using Plasma as a benchmark and model, I have used parts of Plasma in this project. This includes the multiplier/divider unit and the software simulator, both of which have been extensively modified -- details are covered in the source comments and the documentation.\n\nPlease see the included documentation (/doc/ion_project.pdf) for a more detailed explaination of the core features and its current status.\n\n\nThe project ships with a few demos, including a port of Adventure for a bare-metal system and a SD card bootloader.\n\n\n\nWhile this project may eventually produce a useful MIPS CPU core, and is not bad in area and clock rate performance, the real reason I took all this trouble is that it's lots of fun :)\n\n\n\nImportant: While the core can already run almost any arbitrary code, it is not mature enough to be of any immediate use in real-life applications. If you are looking for a mature, well supported and well tested MIPS core, you need to look elsewhere.\nThere's already quite a few MIPS cores out there to choose from, including some in OpenCores.\n\n\nFeedback: Though I don't expect this core to be used at all at this early stage, you can contact me with any doubt and/or correction. Bear in mind that neither the source code nor the documentation have ever been reviewed -- all criticism and feedback is welcome!\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe core is still a work in progress. The main missing features are these, in order of priority:\n\n\n1. Real documentation (specs doc & data sheet) missing.\n2. Logic is too messy, specially the cache-cpu interface. It needs a refactor.\n3. Hardware interrupts not implemented.\n4. Memory handler does not support dynamic RAM.\n5. Integration with MIPS toolchains is poor -- cannot yet use a standard libc.\n6. Caches are not configurable or parametrizable.\n\n\n\nI have found much more trouble than I expected setting up a toolchain for this core. All the MIPS toolchains generally available (and, most importantly, all the libc libraries) target the MIPS32 architecture. \nI have been able to temporarily overcome this problem by emulating the most common mips32-only opcodes (in trap routines) but clearly I need to set up a proper toolchain if this project is to be of any practical use. I may have painted myself into a corner by choosing the mips-I architecture...\n\nAnother thing holding me back is the lack of a suitable FPGA platform for development (one with sufficient memory, for instance).\n\n\nIn short, this being a leisure project, I will complete the work as time permits. Don't hold your breath :)\n\n\n\n \n\n\n \n \n \n\n===== \n Performance =====\n\nSynthesis Results\n\nThese are the synthesis results for the current revision of the core using Altera and Xilinx tools:\n\n\n\n\n\nDeviceSynthesis OptionsClock RateArea (excluding memory blocks)\n\n\nAltera Cyclone-2 (-7)Balanced50 MHz2349 LEs\nXilinx Spartan-3 (-5)Speed51 MHz3173 LUTs\nXilinx Virtex-5 (-1)Speed104 MHz2017 LUTs\n\n \n\nThese results include the CPU core with its default cache and a small, hardwired UART. They have been obtained with Quartus-2 11.1 sp2 and Xilinx ISE WebPack 14.3. The synthesis has been performed unconstrained and the results must be considered illustrative only.\n\nI haven't yet ported any standard benchmark but anyway the system is not geared towards performance (the cache in particular is too simple) so speed results will not be outstanding. \n\n\n\n \n\n\n \n \n \n\n===== \n Updates =====\n\nLast 'known good' revision is rev. 242.\nWith 'known good' I mean it has been checked out and all the code samples have been simulated and run on real hardware.\n\nI use to commit changes piecemeal, so any given revision may contain inconsistent files. You are advised to checkout the last known good revision of the project through SVN, instead of using the download link. Just in case you catch me in the middle of a multi-commit update.\n\nRevision 250 has been tried on the development board but not verified on simulation.\n\nRevisions:\nNovember 15 2012 -- rev. 250\nAdded a new demo, a bootloader that can load a binary from the DE-1 SD card onto RAM and run it from there. Already tested with a new version of the Adventure demo (precompiled binary included).\nThere is also a port of Elm-Chan's FAT32 library, modified to work on a bit-banged interface.\nAnd a new link script meant for applications that run from RAM at address 0x0. The only demo using it right now is Adventure, that can now be compiled to run from flash of from RAM via the SD card.\n\nNovember 15 2012 -- rev. 242\nFixed an erratic behavior detected in the 'Hello World' demo: sometimes, the system crashed immediately after reset.\n\nThe problem has been traced to a corner condition in the cache-cpu interface logic that is briefly explained in the bugtracker page.\n\nThe fix involves a minor change in the I-Cache logic interfacing the CPU: the CPU will not load its IR with a code word from the cache unless it knows the code word is valid, which will only happen after the first code refill (the first after a reset).\n\nAlso fixed a few loose ends: the test bench had not been updated for some of the latest changes in the mini-SoC, so the simulation has been broken for I don't know how long...\n\nAnyway, the logic is way too messy and could use some refactoring.\n\n\nJune 20 2012 -- rev. 231\nCreated new SoC entity built around the CPU and a hardwired UART. Good enough as a demonstration platform. \nThis SoC module replaces an earlier MCU module which was similar but more complex and difficult to set up. \nAdded new tool for VHDL package generation, used to configure the simulation and the synthesis, including the initialization of the simulated and inferred memories. This new tool is now used in all software samples.\n\nThese changes have entailed some major reorganization of the code; this revision has been checked out and tested but if you encounter any trouble, please revert to revision 214!\n\n\nNote: A long list of updates, dating back to the start of the project, used to be present in this page but was lost in a page editing accident as of revision 231. For details on earlier revisions please refer to the SVN logs." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ja_rd name: ion status: Mature svn-updated: Jan 15, 2014 updated: May 17, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Dec 15, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tejasbavarva1111 name: ip-soft_core status: Empty updated: Dec 15, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Dec 19, 2013 description: '' language: SystemC license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - scim name: ips status: Empty updated: Dec 20, 2013 wishbone-compliant: 0 - category: Communication controller created: Jan 5, 2010 description: "===== \n Description =====\n\nVHDL implementation of a component that can be connected to the input port of the Virtex-5 Ethernet MAC Local Link Wrapper and that allows for transmission of IPv4 ethernet packets. \n\nThe complete UDP/IP core that uses this component is the UDP/IP Core project." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - NikosAl name: ipv4_packet_transmitter status: Stable svn-updated: Dec 21, 2010 updated: Mar 7, 2014 wishbone-compliant: 0 - category: DSP core created: Feb 23, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Abraxas3d name: iqcorrection status: Beta svn-updated: Mar 6, 2011 updated: Mar 6, 2011 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Description =====\n\nIrDA core that utilizes uart16550 core for 115.2Kbit/s IrDA communication. Required bit encoding/decoding is performed.\nThe 115.2 (SIR) mode should work alright.\n\nThere's also a lot of code for MIR and FIR, much faster communication modes. Yet they are not fully tested and are sure to contain a lot of bugs.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\xE2\x80\xA2 Designed for all standard IR transceivers.\n\xE2\x80\xA2 Implements WISHBONE bus interface\n\xE2\x80\xA2 Up to 4Mbit communication speed\n\xE2\x80\xA2 Programmable clock selection\n\xE2\x80\xA2 Loopback option for testing\n\xE2\x80\xA2 Works with WISHBONE bus clock\n\xE2\x80\xA2 Can request DMA transfers\n \n\n\n \n \n \n\n===== \n Status =====\n\nCurrently, only 115.2 (SIR) mode is done well. Use irda_top_sir_only.v top-level module.\nFaster modes (MIR, FIR) are not tested well but the specs and most of the code for them exist, just not tested and debugged well." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - gorban name: irda status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Communication controller created: Jul 1, 2003 description: "===== \n Description =====\n\nThis project's aim is to provide the smart-card side of an ISO 7816-3 interface.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Detects reset and sends ATR (Answer to Reset).\n- Translates between the raw ISO7816-3 serial data and a Wishbone compliant format.\n- Provides examples modules that interpret commands sent over the interface.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- A working prototype is ready.\n- No work is currently being done.\n- Current version available for download from http://www.opencores.org/pdownloads.cgi/list/iso7816-3 (the download tab)." language: Verilog license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - blaisegassend name: iso7816-3 status: Planning svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: Jan 9, 2011 description: "===== \n Description =====\n\nThis project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine.\nThis is a work in progress. Currently, a draft implementation is being crafted just to identify the design challenges.\nOnce it is completed, the plan is to make a precise spec of a final version and then implement it.\n\nCurrently the IP supports only T=0, in direct and inverse convention. It does not handle T=0 parity error signaling / retry mechanism yet.\n\nFPGA test included only the UART, not the master module." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - acapola name: iso7816_3_master status: FPGA proven svn-updated: Apr 18, 2011 updated: Apr 18, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Jul 28, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: C/C++ license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - HyunsooKim name: isp status: Empty updated: Jul 29, 2014 wishbone-compliant: 0 - category: Processor created: May 4, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this).\n \n\n\n \n \n \n\n===== \n jmr16f84 =====" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - jkr115 name: jmr16f84 status: Empty updated: May 6, 2013 wishbone-compliant: 0 - alternate-download: https://github.com/jop-devel/jop/archive/master.zip category: Processor created: Feb 19, 2004 description: "===== \n Status =====\n\n- VHDL files and and supporting tools for the design are available from OpenCores CVS.\n- Actual updates are now in a git repository, see http://www.jopwiki.com/Download\n- Further information can be found at http://www.jopdesign.com\n- A wiki is available at http://www.jopwiki.com/\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Very small core:\n - about 2000 LCs - 3000 LCs (configurable)\n - fmax is 100 MHz in a Cyclone EP1C6\n- Real-time features:\n - architecture designed to simplify WCET analysis\n - cycle accurate time interrupt (not tick based)\n - real-time enhanced thread model\n- WISHBONE master\n \n\n\n \n \n \n\n===== \n Description =====\n\nJOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design has been sucessfully implemented in low cost FPGA devices from Altera (ACEX 1K50, Cyclone) and Xilinx (Spartan II and Spartan-3).\n\nJOP is open-source under the GNU General Public License, version 3.\n \n\n\n \n \n \n\n===== \n Source checkout =====\n\nThe latest version of JOP can be obtained with anonymous GIT:\n\n git clone git://www.soc.tuwien.ac.at/jop.git" homepage: http://www.jopdesign.com/ language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - martin - edanuff - rasped - nelkamp - 9914pich - enca - liesen - jeunes2 - paulo - stefant - jwhitham - visq name: jop status: FPGA proven svn-updated: Mar 31, 2009 updated: Sep 5, 2011 wishbone-compliant: 1 - category: Video controller created: Jan 3, 2005 description: "===== \n Description =====\n\nThis project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz).\n \nIMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers.\n\nA testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code.\n\nIn order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd.\n\nIf you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is:\n victor.lopez [(at)] ono [(dot)] com\n\nPLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- JPEG (ISO standard compliant)\n - Baseline DCT\n - Huffman Encoding\n - JFIF Header\n - Three quantization (compression) levels\n\n- Hardware resources\n - Xilinx Coregen DCT core (2D Forward DCT, needs to be generated)\n - Total BlockRAMs: 11\n - Total LUTs: 3969 (38% of XC2V1000-4)\n - Clock Freq: 41.2 MHz for XC2V1000-4" language: VHDL license: CC BY-NC-SA 3.0 licenselink: http://creativecommons.org/licenses/by-nc-sa/3.0/ maintainers: - galland name: jpeg status: FPGA proven svn-updated: Mar 10, 2009 updated: May 9, 2014 wishbone-compliant: 0 - category: Video controller created: Jul 21, 2010 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: jpeg_ls status: Empty updated: Oct 25, 2010 wishbone-compliant: 0 - category: Video controller created: Nov 15, 2009 description: "===== \n Description =====\n\nThis core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a jpeg image. The core was written in generic, regular Verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores, instead all of the functions required to implement the JPEG encoder are written in Verilog and the code is entirely self-contained. This core has been simulated on many raw images with different quantization and Huffman tables." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - davidklun name: jpegencode status: Alpha svn-updated: Feb 15, 2010 updated: Mar 17, 2012 wishbone-compliant: 0 - category: Other created: Sep 25, 2001 description: "===== \n Description =====\n\nThis implementation of the Test Access Port (TAP) is fully IEEE 1149.1 compliant. It includes a TAP controller, a 4-bit instruction register and three test data registers: idcode register, bypass register and boundary scan register. Boundary scan register is connected to eight pins (2 inputs, 2 outputs, 2 tristatable outputs and 2 bidirectional pins). Besides the Verilog code, a BSDL file is also provided. The number of pins can be easily increased by following the instructions. The design had been tested with the JTAG Technologies testing equipment (The TAP controller was implemented in Xilinx 95144XL). The design will be expanded in the future to support additional instruction and debug capabilities. \n \n\n\n \n \n \n\n===== \n Status =====\n\n- New release of the TAP controller. Sections used for debugging were put in a separate project (dbg_interface)\n- New release of the specification document.\n- A description of a Boundary Scan Implementation(57KB) is avaliable in Adobe PDF format (see Downloads). \n- JTAG debug interface for the OR1k processor is finished. \n- Verilog and BSDL files can be accessed via cvsweb. \n\n \n\n\n \n \n \n\n===== \n Next step =====\n\n- nothing at the moment" language: Verilog license: GPL and LGPL maintainers: - igorm name: jtag status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Communication controller created: May 26, 2010 description: "===== \n Description =====\n\nThis is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.org/project,jtag)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - wesche name: jtag_master status: Alpha svn-updated: Feb 6, 2011 updated: Jun 8, 2010 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/jtag_slave-r5.tar.gz category: Communication controller created: Jan 30, 2011 description: "===== \n Description =====\n\nproject is closed at the moment." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - wesche name: jtag_slave status: FPGA proven svn-updated: Jul 24, 2012 updated: Jul 24, 2012 wishbone-compliant: 0 - category: Processor created: Feb 21, 2003 description: "===== \n Description =====\n\nThe k68 is a 68k binary compatible CRISC processor. It supports all twelve (12) addressing modes and most of the instructions for a 68000. It has 32-bit external address and data busses. It has eight (8) data and eight (8) address registers where the last address register also acts as a Stack Pointer. It has only one mode of operation and makes no distinction between user mode and supervisor mode.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Supports all twelve 68000 addressing modes.\n- Binary compatible with the standard 68000.\n- Capable of executing most 68000 instructions.\n- 32-bit external busses.\n- 8 Data and 8 Address Registers where the last address register is the SP.\n- Single mode of operation, no user and supervisor modes.\n- Internal Harvard architecture.\n- CRISC Architecture.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Not optimized. (I figure that the architecture could be further optimized).\n- Files available in CVS\n- Many unresolved bugs (if you intend to work on it, please email me to get a head start).\n- I'm still working on improving it bit-by-bit (pun intended)\n- It is prototyped and working on a Spartan2-200 at 20+MHz without hardware MUL/DIV." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - sybreon name: k68 status: Alpha svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Dec 29, 2013 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: kalman_filter status: Empty updated: Jul 26, 2014 wishbone-compliant: 0 - category: DSP core created: Nov 19, 2013 description: "===== \n Description =====\n\nThis is an implementation of the Kalman Filter for FPGA. It uses fixed point arithmetics and a state dimension of 2." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - joancarles name: kalmanfilter status: Empty updated: Nov 21, 2013 wishbone-compliant: 0 - category: Other created: Jul 1, 2005 description: "===== \n Description =====\n\nThe controller scans the keyboard by making a different column in \"rows\" logic-0\ntherefor the inputs \"cols\" have to be PULL-UP high. It processes the inputs \"cols\" and\nthe newly found keychange (keypress or keyrelease) is converted to the corresponding\nscancode (translated set2). Note that an interrupt pin is attached as well to make it\npossible to connect this controller to a PIC. \n \nAlso note that the keyboard_controller uses an internal clock divider to divide\nthe system clock of 50 Mhz to 100 kHz. Should you want to use an other frequency\nthan 100 kHz please do not forget to change Constants.vhd \n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Simple debounce algorithm, it checks for stable inputs in last #nr samples\n- Ghosting protection\n- Module is easy to understand and build out of sub-modules\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Currently used for input processing of a toy-keyboard" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - wouterw name: keyboardcontroller status: FPGA proven svn-updated: Mar 10, 2009 updated: May 3, 2011 wishbone-compliant: 0 - category: Other created: Apr 1, 2003 description: "===== \n Description =====\n\nThis is a very small and simple module, which scans through an X-Y matrix of keys, and produces a \"snapshot\" of bits which represent the sampled state of the keyswitches during the scan.\n\nThere is memory in the module, so that the outputs are held constant during a scan, and updated simultaneously. The keys are sampled sequentially, but the memory stores up all of the keyswitch data until the final output \"snapshot\" is produced.\n\nThis module is parameterized Verilog, and is recommended for use with small matrix type keypads. It has been tested in real hardware.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Parameterized Verilog code, tested in hardware\n- Commented code, but no testbench\n- Small module, easy to use and understand\n- No support for \"ghost key\" detection (when three or more keys are pressed, a fourth \"phantom key\" can sometimes appear. This is true for most matrix type keyboards.)" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jclaytons name: keypad_scanner status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Prototype board created: May 28, 2006 description: "===== \n Description =====\n\n\n\n \n[Keep It Simple,Stupid] Board.\nThe board was evaluated like [or1k/orp project].\n\nBOARD consists of two pieces. One is FPGA board. Another is MOTHER board. \nThe device on the FPGA board is ANY(xilinx or altera ...).\nOnly connected specification of the board is important.\n \n\n \n\n\n \n \n \n\n===== \n Board snapshots =====\n\n\n\n\n MOTHER board\n \n \n \n \n \n \n\n FPGA board\n \n \n \n \n \n \n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n\n\n\n Assembly\n \n It's planning(more cheap!)\n \n\n Evaluation\n \n It's finished(commit code,RTL8019AS Evaluation is done)\n \n\n Simulation\n \n It's finished(commit code,checkout-test is done)\n \n\n Design\n \n It's finished(commit code,checkout-test is done)\n \n\n\n \n\n\n \n \n \n\n===== \n Evaluation =====\n\n\n\n\n\n Benchmark\n \n Program Outline\n \n \n- Draw1Test:Normal render(Read,Write)\n- Draw2Test:RGB565->YUV,Y:modulation,YUV->RGB565(Read,Calculation,Write)\n- EraseTest:Clear VRAM(Write)\n \n \n\n Sytem Condition\n \n \n- Case 1:CPU=25MHz,WB=25MHz,EXT_MEM=50MHz\n- Case 2:CPU=30MHz,WB=30MHz,EXT_MEM=50MHz\n- Case 3:CPU=25MHz,WB=25MHz,EXT_MEM=60MHz\n \n \n\n OR1200 Condition\n \n \n- Case A:IC=no-used,DC=no-used\n- Case B:IC=4KByte ,DC=no-used\n- Case C:IC=no-used,DC=4KByte\n- Case D:IC=4KByte ,DC=4KByte\n \n \n\n MISC condition\n \n \n- VramRenderRoutine on EXT_FLASH[.text section](include Cache)\n- InterruptsHandler on QMEM[.icm section]\n- ImageDataSize(40x50pixel) is 4000byte(include Cache)\n- The byte_order of QMEM is enable.\n \n \n\n \n\n Demonstration\n \n\n phots\n \n\n VIEW:ALL(zoom)\n \n \n\n VIEW:Connector(zoom)\n \n \n\n VIEW:Draw1Test(zoom)\n \n \n\n VIEW:Draw2Test(zoom)\n \n \n\n \n\n Results\n \n\n VIEW:Draw1Test(zoom)\n \n \n\n VIEW:Draw2Test(zoom)\n \n \n\n VIEW:Erase(zoom)\n \n \n\n \n\n \n\n\n\n\n\n \n \n\n\n \n \n \n\n===== \n TODO =====\n\n\n\n \n- Reduce cost\n - This is Expensive or Cheap?\n - How to do?(thinking)\n- The examination point is put out. \n - How is the Debug-Interface-pin?\n- This WEB page is maintained\n - Add Board electrical information\n - Add Teaching material information\n \n\n\n \n\n\n \n \n \n\n===== \n Design =====\n\n\n\n\n Hardware\n \n PCB Architecture\n \n How to name the board (pdf-file)\n Connectors (pdf-file)\n The circuit of Mother Board as reference (pdf-file)\n The circuit of FPGA Board as reference (pdf-file)\n \n\n SOC Architecture\n \n System block (pdf-file)\n System hierarchy (pdf-file)\n OR1200 block (pdf-file) >>> Please refer the OpenRisc 1000 project\n \n \n \n\n Software\n \n\n Functions\n \n function hierarchy (pdf-file)\n \n \n\n Sections\n \n Section Usage\n .reset InstractionCode at Start \n .vectors InstractionCode at Exception\n .text InstractionCode(normal)\n .icm InstractionCode(early)\n .data DataCode(initialization)\n .bss DataCode(no-initialization)\n .extdata ExtendDataCode(initialization)\n .extbss ExtendDataCode(no-initialization)\n .stack StackArea\n \n Memory\n \n Device Address Usage\n InternalSRAM0 0x00000000 Exception\n InternalSRAM1 0x01000000 NotImpliment \n ExternalSDRAM0 0x02000000 ---\n ExternalSDRAM1 0x03000000 VRAM\n ExternalFlash 0x04000000 BIOS\n \n Interrupts\n \n Core Location Exception Interface\n TickTimer OpenRisc1000(OR1200) 0x500 Internal\n UART16550 SOC-Peripheral 0x800 MemoryMapIO\n WB_DMA SOC-Peripheral 0x800 MemoryMapIO\n \n \n\n \n\n\n \n \n \n\n===== \n Assembly =====\n\n\n\n\n Manual\n \n You can get the hardware-manual.I did upload it here.\n \n \n\n More information\n \n If you have a question,you can contact us,please refer to following web-page. Tessera WebSite(Japanese) Tessera WebSite(English)\n \n \n\n\n \n\n\n \n \n \n\n===== \n Simulation =====\n\n\n\n\n CrossCompiler Environment\n \n Source binutils-2.16.1.tar.gz\n >wget ftp.gnu.org/gnu/binutils/binutils-2.16.1.tar.gz\n >gzip -dc binutils-2.16.1.tar.gz | tar xvf -\n \n Patch to binutils-2.16.1\n >wget www.opencores.org/cvsget.cgi/or1k/binutils/binutils-2.16.1/binutils-2.16.1-unified.diff.bz2?do_download=now\n >bzip2 -d binutils-2.16.1-unified.diff.bz2\n >cd binutils-2.16.1\n >patch -p1 cd ..\n \n Build CrossCompiler\n >mkdir binutils_build\n >cd binutils_build\n >../binutils-2.16.1/configure --target=or32-uclinux --prefix=/opt1/or32-uclinux\n >make all \n >make install\n >cd ..\n \n \n\n Generated boot-image Environment\n \n bmp2c(SmallProgram)\n Description:Convert bmp-file to c-file.\n InputFile :BMP(only24bitBGR,RGB888)\n OutputFile :C(RGB565)\n WorkingDir :./kiss-board/kiss-board_soc/sw/bmp2c\n >cd ./kiss-board/kiss-board_soc/sw/bmp2c\n >make\n \n utils(SmallProgram)\n Description:Convert boot-rom,etc\n WorkingDir :./kiss-board/kiss-board_soc/sw/utils\n >cd ./kiss-board/kiss-board_soc/sw/utils\n >make\n \n boot_uart\n Description:Example1 to compile,execute object from uart\n WorkingDir :./kiss-board/kiss-board_soc/sw/boot_uart\n >cd ./kiss-board/kiss-board_soc/sw/utils\n >make\n \n boot_flash\n Description:Example2 to compile,boot from rom\n WorkingDir :./kiss-board/kiss-board_soc/sw/boot_flash\n >cd ./kiss-board/kiss-board_soc/sw/boot_flash\n >make\n \n \n\n Simulation Environment\n \n pan\n Description:VerilogPLI($pan=>like a popen())\n WorkingDir :./kiss-board/kiss-board_soc/sim/c/pan\n >cd ./kiss-board/kiss-board_soc/sim/c/pan\n >make\n \n hex2ver\n Description:IntelHEXtoVerilog(PLI?)\n WorkingDir :./kiss-board/kiss-board_soc/sim/c/pan\n >cd ./kiss-board/kiss-board_soc/sim/c/convert_hex2ver\n >make -f Makefile.cygwin.modeltech\n >make -f Makefile.linux.modeltech\n >make -f Makefile.linux.ncverilog\n \n ram\n Description:GTK application,VRAMScreen\n WorkingDir :>./kiss-board/kiss-board_soc/sim/c/ram\n >cd ./kiss-board/kiss-board_soc/sim/c/ram\n >make" language: Verilog license: various maintainers: - fukuchi name: kiss-board status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 1 - category: Processor created: Oct 5, 2011 description: "===== \n Description =====\n\nKLC32 is a 32 bit non-pipelined processor. This project is in the first stage of it's evolution and has a long ways to go yet, hence descriptions are a bit lacking. Read the code. First coding was Oct 4, 2011.\n \n\n\n \n \n \n\n===== \n Programming Model =====\n\nThere a 32 x 32 bit registers with register R0 always reads as zero.\n\nThere are two processor modes, user and system, each with it's own stack pointer. Some instructions are restricted to system mode only.\n\nThere is a group of eight condition code registers cr0 to cr7, each of which contains four status flags: carry,overflow,negative, and zero. The compare instruction can set any one of the group of condition codes.\nMany instructions update cr0 automatically.\n\nTwo address modes are supported: register indirect with displacement, and indexed addressing." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: klc32 status: Planning svn-updated: Apr 9, 2012 updated: Oct 6, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Sep 29, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: kp_dsp status: Empty updated: Sep 30, 2014 wishbone-compliant: 0 - category: Other created: Sep 29, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: kp_functions status: Empty updated: Sep 30, 2014 wishbone-compliant: 0 - category: Other created: Sep 29, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: kp_library status: Empty updated: Sep 30, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Mar 6, 2014 description: "===== \n Description =====\n\nkvcordic is a collection of files comprising an implementation of a universal CORDIC algorithm (rotation/vectoring direction, circular/linear/hyperbolic mode) high-level synthesis benchmark by Nikolaos Kavvadias. \n\nThe design is a universal CORDIC IP core supporting all directions (ROTATION, VECTORING) and modes (CIRCULAR, LINEAR, HYPERBOLIC). The I/O interface is similar to e.g. the CORDIC IP generated by Xilinx Core Generator). It provides three data inputs (xin,yin, zin) and three data outputs (xout,yout, zout) as well as the direction and mode control inputs. The testbench will test the core for computing cos (xin), sin (yin), arctan(yin/xin), yin/xin, \xE2\x88\x9Aw, 1/\xE2\x88\x9Aw, with xin = w + 1/4, yin = w \xE2\x88\x92 1/4, but it can be used for anything computable by CORDIC iterations. The computation of 1/\xE2\x88\x9Aw is performed in two stages: a) y = 1/w, b) z = \xE2\x88\x9Ay. \n\nThe design is a monolithic FSMD that does not include post-processing needed such as the scaling operation for the square root. The FSMD for the CORDIC uses Q2.14 \xEF\xAC\x81xed-point arithmetic. The core achieves 18 (CIRCULAR, LINEAR) and 19 cycles (HYPERBOLIC) per sample or n + 4 and n + 5 cycles, respectively, where n is the fractional bitwidth. A single-cycle per iteration constraint imposes the use of distributed LUT RAM, otherwise 3 cycles are required per sample (distinct load, compute, store cycles). \n\nAll design files except cordic.c, cordic.nac, and cordic_test_data.txt have been automatically generated using HercuLeS HLS (http://www.nkavvadias.com/hercules/ . The original cordic.vhd has been optimized via (manual) operation chaining. operpack.vhd, \nstd_logic_textio.vhd are simulation/synthesis library files, copyrighted by their respective authors.\n\nIMPORTANT: Please go through the license agreement (CORDIC-EULA.txt) to ensure proper use of the CORDIC IP CORE.\n\nFor documentation, consult the README, README.html, README.pdf files in /doc.\n\nSPECIAL THANKS: Go to MSc and PhD candidate Mrs. Vasiliki Giannakopoulou for explaining to me how CORDIC works and for implementing a hand-coded optimized version to compare with! Her hand-written CORDIC is also blazing fast for a portable non-Xilinx or non-Altera specific design." language: VHDL license: custom licensetext: "CORDIC IP CORE END-USER LICENSE AGREEMENT\n=========================================\n\n1. Definitions\n1.1 \"Generated IP-Core\", \"IP-Core\", \"IP-CORE\", \"IP CORE\" or \"Licensed Materials\" \nshall mean all design data files distributed within the \"cordic-v1.0.0\" package.\n1.2 \"Licensor\" shall mean the following people: Nikolaos Kavvadias \n1.3 \"Copyright holder\" shall mean: Nikolaos Kavvadias\n1.4 \"Licensee\" or \"You\" shall mean any recipient of the Licensed Materials \nin any applicable for. The Licensee accepts to obtain the CORDIC IP CORE \nsubject to the terms and conditions of this Agreement.\n1.5 \"Agreement\" shall mean this document.\n\n2. Restrictions\nLicensee shall not use the Licensed Materials for any purpose that involves \ncommercial or for-profit activity. Licensee shall use the Licensed Materials \nsolely for non-commercial, non-profit, demonstration-only personal use. Licensee\nmay use the \"Licensed Materials\" for performance evaluation with his/her or \nthird-party IP-Core(s). Performance evaluation results may be published as part \nof scientific publications without reproduction of any part of the IP-Core. \nLicensee may make unlimited copies of the Licensed Materials solely for backup \nor archival purposes. \n\n3. Non-Transferable\nLicensee shall not distribute, rent, lend, loan, lease, sublease, assign, \ntransfer, license, or sublicense the Licensed Materials in whole or in part to a \nthird party without express written permission from Licensor.\n\n4. Intellectual Property Rights\n4.1 The Licensee acknowledges that Copyright Holder shall retain sole right, \ntitle, and ownership of the IP-Core and all intellectual property rights \n(including patents, copyrights, trade secrets, trade names, trademarks and \ninvention disclosures) related to the IP-Core, including, but not limited to, \nany and all improvements, modifications or derivatives thereof.\n4.2 This Agreement does not grant the Licensee any rights to any patents, \ncopyrights, trade secrets, trade names, trademarks, or any other rights or \nlicenses with respect to the IP-Core except those granted in Section 2.\n4.3 The Licensee agrees to maintain the secrecy of the contents of the IP-Core \nand to implement adequate safeguards to prevent and protect the contents of the \nIP-Core from unauthorized use or disclosure.\n\n5. Termination\nThis License Agreement is effective until terminated. Licensee may terminate it \nat any time by destroying all copies of the Licensed Materials. In the event \nLicensee fails to comply with any term of this License Agreement, this License \nAgreement will terminate immediately, and Licensee must destroy all copies of \nthe Licensed Materials.\n\n6. Critical Applications - Limitation of Liability\nTHE IP-CORE IS NOT INTENDED TO BE FAIL-SAFE, OR FOR USE IN AN APPLICATION \nREQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFESUPPORT SYSTEMS, SAFETY DEVICES, \nNUCLEAR FACILITIES, WEAPONS OR WEAPONS SYSTEMS, HAZARDOUS SUBSTANCE MANAGEMENT \nOR MEANS OF MASS TRANSPORTATION. FURTHERMORE, LICENSOR SHALL NOT BE LIABLE FOR \nANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF THE IP-CORE IN ANY \nAPPLICATION WHERE THE FAILURE OR INACCURACY OF THE IP-CORE MIGHT RESULT IN \nDEATH, PERSONAL INJURY, OR DAMAGE TO EITHER PROPERTY OR THE ENVIRONMENT. YOU \nAGREE TO INDEMNIFY AND HOLD HARMLESS LICENSOR FROM ANY CLAIMS, LOSSES, COSTS,\nDAMAGES, EXPENSES OR LIABILITY, INCLUDING LEGAL FEES, ARISING OUT OF OR IN \nCONNECTION WITH SUCH USE.\n\n7. Limited Warranty and Disclaimer\nEXCEPT AS EXPRESSLY STATED ABOVE, THE LICENSED MATERIALS ARE PROVIDED TO \nLICENSEE \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, \nINCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR \nA PARTICULAR PURPOSE.\nLICENSOR DOES NOT WARRANT THAT THE IP-CORE WILL MEET THE LICENSEE'S REQUIREMENTS \nOR THAT THE OPERATION OF THE IP-CORE WILL BE UNINTERRUPTED OR ERROR FREE. \nFURTHERMORE, LICENSOR DOES NOT WARRANT OR MAKE ANY REPRESENTATIONS REGARDING USE\nOR THE RESULTS OF THE USE OF THE IP-CORE IN TERMS OF CORRECTNESS, ACCURACY, \nRELIABILITY OR OTHERWISE.\n\n8. Governing Law\n8.1 This Agreement shall be governed by and construed under the laws of Greece \nand the Greek courts shall have exclusive jurisdiction to hear all matters \narising out of this Agreement.\n8.2 If any provision of this Agreement is held by a court of competent \njurisdiction to be void, invalid, unenforceable or illegal, such provision shall \nbe severed from this Agreement and the remaining provisions will remain in full \nforce and effect.\n" maintainers: - kavi name: kvcordic status: Beta svn-updated: Mar 9, 2014 updated: Mar 8, 2014 wishbone-compliant: 0 - category: Processor created: Oct 13, 2010 description: "===== \n Overview =====\n\nSummary\nThis document describes my implementation of a 6502 microprocessor into a Lattice LCMXO2280C FPGA. The hardware is based on an existing PCB leftover from a controller for a soft X-ray generator. It is anticipated that the design can be ported to other FPGA devices. It is written in VHDL and used GNU ghdl for initial development and Lattice ispLeaver to implement the design into the FPGA. The GNU software was found to be significantly faster than Lattice. Files and information is provided to implement the design into both Lattice parts and hopefully other parts.\n\nThe 65C02 instructions have yet to be implemented. The timing bears no relationship with that of a genuine 6502; it is intended to execute the instruction set as fast as possible. This will make it very difficult to use on an Apple 2 or other 6502 based PC.\n\nAlso included are a UART TX and RX and sufficient assembly language firmware to communicate to a dumb terminal (IE Linux gtkterm). This provides a simple OS, Kernel or monitor that is able to display and modify memory and load Motorola S code. This monitor is burnt into the FPGAs ROM. The capability to load and execute a program via the terminal is much faster than re-generating the FPGA each time a program change is required to validate an instruction.\n\nThe status is such that code can be run on a programmed FPGA and instructions verified one by one. I intend to provide two zip files, one with minimum necessary to implement a FPGA and one with all my modules." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - stanley82 name: lattice6502 status: FPGA proven svn-updated: Dec 14, 2010 updated: Dec 17, 2010 wishbone-compliant: 0 - category: System on Chip created: May 1, 2012 description: "===== \n layer[2] SoC =====\n\nComponents\n\nThe following components are implemented and tested on silicon:\n\n\nMIPS I(tm) CPU @ 50MHz\nIntel StratFlash\nPS/2 Keyboard\n100x37 8-Color Text-VGA\n19200/8N1 RS-232 Receiver/Transmitter\n512 MBit DDR Ram\n\n\n\n\n\n\nThe picture to the left shows the start-up screen. With \"void Bootloader\" you can upload program images to the flash and run then on the DDR. \nAn example program is \"Tennmino\" a tetris clone for layer[2]. \n \n\n\n \n \n \n\n===== \n Acknowledgement =====\n\nGeneral Notice\n\nEvery component consists of an implementation and an interface file i*.vhd where I credited (hopefully) all resources.\n\nReference Projects on OpenCores\n\nI learned alot from the projects available on OpenCores. I'd like to list all the projects I consulted the most:\n\n\nPlasma - most MIPS I(TM) opcodes\nZ80 System on Chip\nYet Another VGA\nScratch DDR SDRAM Controller\n \n\n\n\n \n \n\n\n \n \n \n\n===== \n Legal Notice =====\n\nCopyright (C)2012 Mathias H\xC3\xB6rtnagl \n\nThis program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. \n\nThis program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.\n \n\n\n \n \n \n\n===== \n Disclaimer =====\n\nMIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. OpenCores and Mathias H\xC3\xB6rtnagl are not affiliated in any way with MIPS Technologies, Inc." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - idiolatrie name: layer2 status: FPGA proven svn-updated: Jul 15, 2012 updated: Jul 16, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Jul 26, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - vineeshvs name: lc-3b_multi_cycle_implementation status: Empty updated: Jul 26, 2014 wishbone-compliant: 0 - category: Video controller created: Sep 25, 2001 description: "===== \n Description =====\n\nLCD Driver that we want to designed is a CMOS LCD driver capable of driving a multiplexed display of up to 128 segments ( 16 columns by 8 backplanes ). The number of backplanes being driven is programmable from one to eight. Data to be displayed is sent to the chip serially and stored in an internal RAM. An external resistor and capasitor control the frequency of the driving signals to the LCD. The displayed data may also be read serially from the on-chip RAM. \n \n\n\n \n \n \n\n===== \n Specifications =====\n\n- Operates on 22-bits (five bits first is address, the next bit is read and write flags, and 16 bits data ) \n- Can be programmed to accept oscillator output \n- Can be programmed to backplane signals of another LCD Driver for cascading purposes. \n- Can driving a multiplexed display \n- For backplane capacitance under 2000 pF LCD driver guarantees an offset of less than 10 mV. \n- Power supply of VDD is 5 V - 15 V. \n \n\n\n \n \n \n\n===== \n IMAGE: LCD.ht1.gif =====\n\nFILE: LCD.ht1.gif\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n Design Stages =====\n\n- Make core specifications \n- Design the behavioral and structural VHDL using Alliance tools \n- Implementation to symbolic layout \n- Full verifications \n- Converting to real layout \n- Make full report \n \n\n\n \n \n \n\n===== \n Status =====\n\n\n\nMake the behavioral and structural VHDL using Alliance tools\n\nTo know a little bit about Alliance, click this\n\nYou can download our work documentation (Alliance VHDL code) here.\xC2\xA0\n\n \n\n\n \n \n \n\n===== \n Authors =====\n\n\n\nMima@manufel.paume.itb.ac.id\n\n\nhendrag01@s.ee.itb.ac.id\n\n\niyon@s.ee.itb.ac.id\n\n\nssarwono@ieee.org" language: VHDL license: unknown maintainers: - sarwono name: lcd status: Beta svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Video controller created: Jun 17, 2008 description: "===== \n Description =====\n\nSimple memory mapped, character type dot matrix LCD controller for interfacing the Samsung's KS0073.\nThe controller supports the 40SEG extension driver providing a 4-line x 20 character display. It uses a memory mapped 4x20x8 bit matrix, transformed in real-time to the display.\nIt completely takes the responsibility for sending the appropriate sequences of commands to the KS0073. The higher layer needs only to take care of the content of the matrix. This makes its implementation as a microcontroller peripheral unit very comfortable.\nhttp://www-user.tu-chemnitz.de/~dimo/opencores/lcd1_1.GIF\n \n\n\n \n \n \n\n===== \n Features =====\n\n- generic parameterizable features\n - Timing parameters \n - cursor modes \n- additional files and scripts\n - testbench written in VHDL\n - Makefile for\n - synthesis with XST (Xilinx) \n - simulation with Modelsim (Mentor Graphics)\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- The project is completed, but further improvements are always welcome. \n- The project is written after only 3 months of VHDL experience, so even though verified, extra caution is required when using it in serious projects." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dimo name: lcd1 status: FPGA proven svn-updated: Mar 10, 2009 updated: Sep 12, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Sep 18, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ttobsen name: lcd162b_behavior status: Planning svn-updated: Sep 18, 2013 updated: Sep 18, 2013 wishbone-compliant: 0 - category: Other created: May 18, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: lcd_block status: Planning svn-updated: May 24, 2012 updated: May 18, 2012 wishbone-compliant: 0 - category: Video controller created: Oct 8, 2004 description: "===== \n Progress =====\n\n- Display one repeat line (800 pixels) stored in ROM synthesized in FPGA.\n- Self-display word block (designed).\n- (Have problem on hardware integration) Preparing display a frame stored in SSRAM which is on Logic Module.\n- Parameter:\n - VBP/VFP (Vertical-Sync. back/front porch)\n - HBP/HFP (Horizontal-Sync. back/front porch)\n - PPL/LPP (Pixel Per Line/Line Per Panel)\n - I design the width of synchronization to be auto-calculated by the way of how it display.\n\n\\:\n - Improve:\n - Efficiency of data transformation.\n - Support more kinds of display.\n - ..to be continued\n\n - Decrease:\n - Needed size of frame buffer.\n - Chip area.\n - ..to be continued\n \n\n\n \n \n \n\n===== \n Features =====\n\n\\http://www.altera.com/products/devices/apex/overview/apx-overview.html#1.8 (EP20K1000E 1.8V)>\n - Typical Gates 1 million\n - Maximum System Gates 1,771,520\n - Logic Elements (LEs) 38,400\n - Maximum RAM Bits 327,680 = 40KB\n - Phase-Locked Loops (PLLs) 4\n - Speed Grades -3, -2, -1 (-1 is the fastest speed grade.)\n - Maximum User I/O Pins 708\n\n\\\n - Product name TX18D16VM1CAA\n - Effective Display Area (H)152.4 x (V)91.44 [mm]\n - Display Dots (H)(800x3) x (V)480 [dots]\n - (Display Pixels) (H 800 x V 480) [pixels]\n - Pixel Pitch (H)0.1905 x (V)0.1905 [mm]\n - Color Pixel Arrangement R+G+B Vertical Stripe\n - Display Mode Transmissive Mode, Normally White Mode\n - Surface Polarizing Film Polarizing Film with Antiglare Coating\n - Number of Colors 262k [colors]\n - Interface C-MOS, R.G.B x 6 bit Digital each\n - Color Saturation 60%(typ) for NTSC\n - Viewing Angle 12 o'clock. (The direction it's hard to be discolored)\n - Backlight CCFL, 1pc Side-light type (U shape)\n - Dimensions Outline (H)165.0(typ) x (V)106.0(typ) x (t)10.5(max) [mm]\n - Weight Approximately 170 [g]\n\n\\\n ..to be continued\n \n\n\n \n \n \n\n===== \n Index of specification =====\n\n- The presentation of this project is in the download field.\n- http://www.arm.com/products/solutions/AMBA_Spec.html (AMBA Specification Rev2.0)\n- http://www.arm.com/pdfs/DDI0169B_AHB_CPU.pdf (ARM920T AHB Wrapper)\n- http://www.arm.com/pdfs/DDI0236F_ssmc_pl093_r0p3_trm.pdf (PrimeCell\xE2\x84\xA2 Synchronous Static Memory Controller [PL093] Revision: r0p3)\n\n- http://www.arm.com/products/DevTools/IntegratorFamily.html (RealView Integrator Family)\n - http://www.arm.com/products/DevTools/IntegratorAP.html (ASIC Development Platform)\n - http://www.arm.com/miscPDFs/5364.pdf (Part Numbers: INAP1-BD-0109A)\n - http://www.arm.com/pdfs/DUI0098B.zip (AP User Guide)\n - http://www.arm.com/products/DevTools/IntegratorCM920T.html (ARM920T Core Module - No ETM)\n - http://www.arm.com/miscPDFs/5364.pdf (Part Numbers: CM920-BD-0113C)\n - http://www.arm.com/pdfs/CM920T%20User%20Guide%20.pdf (Core Module User Guide)\n - http://www.arm.com/support/integrator_faq.html (Frequently Asked Questions)\n - http://www.arm.com/products/DevTools/IntegratorLM-EP20K1000E.html (Altera Apex EP20K1000E Logic Module)\n - http://www.arm.com/pdfs/DUI0146C_LM600.pdf (Logic Module User Guide)\n - http://www.arm.com/products/DevTools/MultiICE.html (RealView Multi-ICE)\n - http://www.arm.com/pdfs/DUI0048F_MICE2_2.pdf (Multi-ICE User Guide)\n - http://www.arm.com/pdfs/DUI0154B_MICE_2_2_TapOp.pdf (Multi-ICE TAPOp API Reference Guide)\n - http://www.arm.com/support/multi_ice_faq.html (FAQ of Multi-ICE)\n\n- http://hitachi-displays-eu.com/faqs/plist2.asp?moc=colour&sor=screensize&val=%207.0\" (Hitachi 7\" Colour TFT-LCD Panel with Inverter)\n - http://hitachi-displays-eu.com/faqs/pinfo2.asp?pno=TX18D16VM1CAA (TX18D16VM1CAA)\n\n..to be continued" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - cc456 name: lcd_controller status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: ECC core created: Feb 20, 2007 description: "===== \n Description =====\n\nLDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager's A algorithm. See also http://opencores.org/project,ldpc_encoder_802_3an,overview (802.3an LDPC Encoder).\n \n\n\n \n \n \n\n===== \n FILE: ldpc_decoder_802_3an.tar.gz =====\n\nFILE: ldpc_decoder_802_3an.tar.gz\nDESCRIPTION: Verilog 802.3an LDPC Decoder and Testbench" language: Verilog license: MIT (Expat) licenselink: http://opensource.org/licenses/MIT maintainers: - tomahawkins name: ldpc_decoder_802_3an status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: ECC core created: Feb 16, 2007 description: "===== \n Description =====\n\nLDPC Encoder for 10GBase-T Ethernet (802.3an). See also http://opencores.org/project,ldpc_decoder_802_3an,overview (802.3an LDPC Decoder).\n \n\n\n \n \n \n\n===== \n FILE: ldpc_encoder_802_3an.v.gz =====\n\nFILE: ldpc_encoder_802_3an.v.gz\nDESCRIPTION: Verilog 802.3an LDPC Encoder" language: Verilog license: MIT (Expat) licenselink: http://opensource.org/licenses/MIT maintainers: - tomahawkins name: ldpc_encoder_802_3an status: Stable svn-updated: Mar 10, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Apr 8, 2005 description: "===== \n LEM1_9min documentation =====\n\nDescription:\n\nExtremely simple micro-controller allowing easy augmentation of the instruction set (e.g. a Hello World project for FPGA micros). Associated assembler written in C#. Example program displays a scrolling \"Hello UJorld\" on four digit/seven-segment display.\n\nMotivation\n\n* A \xE2\x80\x9CHello World\xE2\x80\x9D for FPGAs\n e.g. a simple microprocessor core for use in a FPGA/VHDL course\n\n* A Core that is easily extended with additional instructions, addressing modes,\n registers, etc.\n\n* Exploits single port distributed RAM\xE2\x80\x99s ability to do both sync write & async read.\n\n* High performance, single pipeline stage micro-controller.\n\n* Efficiently implement slow speed logic via emulation.\n\n* Implement real-time software via compilation to EDIF.\n One processor per interrupt and deterministic timing.\n\nPerformance:\n\n* 100+ Mhz, in a Spartan 3\n* Uses 84 logic LUTs and one-half of a block RAM\n* Single cycle instruction execution.\n\nImplementation:\n\nThe design regimen is single pipeline stage micro-controller. Instruction fetch via block RAM read. Data fetch via distributed RAM asynchronous read. Data store via synchronous write coinciding with next instruction fetch (and register updates).\n\nThe instruction set includes no branches or calls. Program executes sequentially until HALT instruction. Then waits for next \xE2\x80\x9Csystem\xE2\x80\x9D clock.\n\nVery simple assembler via subroutine calls (one subroutine for each unique instruction) which deposit binary into a list. List is formatted and written to text file suitable for pasting into block RAM initialization.\n\nLem1_9min_defs.vhd\t Instruction set\nLem1_9min.vhd\t\t Core\nLem1_9min_hw.vhd\tTest harness for Xilinx/Digilent Spartan-3 board\nForm1.cs\t\t C# source for \xE2\x80\x9Cassembler\xE2\x80\x9D\nLem1_9min_asm.csproj\tC# project for lem1_9min assembler, uses Windows form\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nNo branch instructions. Program executes until reaching HALT instruction. Then waits for next \"system\" clock. Intended for logic emulation.\n\nSingle bit wide accumulator and memory. Carry bit available and with ADC (add with carry) instruction arithmetic is done bit serial.\n\nData memory kept in distributed RAM (Xilinx). Uses async read and sync write. In a single instruction clock cycle: program memory read, instruction address field addresses data memory and data memory read. Then instruction is performed followed by register updates. Register update also does distributed RAM write if enabled.\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nFully functional and tested on Digilent Spartan-3 Starter board (www.digilentinc.com).\n\nConsidering several approaches to variable bit length instructions.\n \n\n\n \n \n \n\n===== \n FILE: trinity_talk_041205.pdf =====\n\nFILE: trinity_talk_041205.pdf\nDESCRIPTION: PDF presentation\n\n \n\n\n \n \n \n\n===== \n FILE: lem1_9min.vhd =====\n\nFILE: lem1_9min.vhd\nDESCRIPTION: micro-controller core\n\n \n\n\n \n \n \n\n===== \n FILE: lem1_9min_hw.vhd =====\n\nFILE: lem1_9min_hw.vhd\nDESCRIPTION: Test harness\n\n \n\n\n \n \n \n\n===== \n FILE: d3_lem1_9min_hw.ucf =====\n\nFILE: d3_lem1_9min_hw.ucf\nDESCRIPTION: Clock constraint and pin assignments\n\n \n\n\n \n \n \n\n===== \n FILE: Form1.cs =====\n\nFILE: Form1.cs\nDESCRIPTION: C# assembler for lem1_9min\n\n \n\n\n \n \n \n\n===== \n FILE: lem1_9min_asm.csproj =====\n\nFILE: lem1_9min_asm.csproj\nDESCRIPTION: C# project file for lem1_9min" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jimbrakefield name: lem1_9min status: FPGA proven svn-updated: May 5, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Processor created: Sep 5, 2011 description: "===== \n Description =====\n\nLeros is a 16-bit processor optimized for FPGAs. It consumes less than 200 logic cells and 1-2 on-chip memories.\nLeros is programmed in assembler and in a restricted subset of Java. Leros is a direct competitor to tiny processor\ncores, such as PicoBlaze.\n \n\n\n \n \n \n\n===== \n Comparison with PicoBlaze =====\n\nLeros targets the same application area as PicoBlaze and\nis about the same size. Following list gives the main differences:\n\n* Truly open source (BSD)\n* Compiles on Altera and Xilinx tools\n* Leros is a 16 bit architectures instead of 8 bit\n* Leros has no restrictions on code and data size\n* Single clock cycle instructions\n* Java based assembler is platform independent\n* Simplified Java compiler for Leros available" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - martin name: leros status: FPGA proven svn-updated: Nov 8, 2012 updated: Mar 6, 2012 wishbone-compliant: 0 - category: Processor created: Mar 27, 2013 description: "===== \n Description =====\n\nLeros-32 is a 32-bit ALU port of the Leros project. It contains an icache and dcache implementation and interface for Xilinx based memory controller access. All of this can be realized inside of ~350 logic cells and 2 brams. This processor achieves > 100mhz running frequency inside of Spartan-6 hardware. A simple assembler is currently implemented and a port of binutils and llvm is in the works. \n\nThe processor core itself is an accumulator based design with an additional register for memory accesses. There are 256 pseudo registers which can be loaded or stored from the accumulator without touching the memory subsystem. All instructions except indirect load/store execute in a single cycle. Regular RISC 3 register codes can be emulated on this architecture using 3 operations. For example \n\nadd r0, r1, r2\n\ncould be translated to:\n\nload r1\nadd r2\nstore r0\n\nSuch a technique is being explored for the LLVM port. In theory this should give leros about 1/3 the DMIPS/mhz as other much larger 32-bit cpus. However optimizations are often possible. For example the code a = b + c + d + e +f +g could be compiled into nearly the same number of instructions on leros-32 and ARM. Additionally, ARM may have several pipeline stalls to execute that code where as Leros-32 will have zero. \n \n\n\n \n \n \n\n===== \n Features =====\n\n\n32-bit ALU\n4GiB addressable memory\nWishbone I/O Port\nIntegral caches\nExtremely small logic footprint\nSingle cycle execution of micro-ops\nUnified memory model\nDelay based simulation coding style\nHigh clock speed\nAssembler included\n\n \n\n\n \n \n \n\n===== \n Getting Leros-32 =====\n\nLeros-32 source is currently hosted at github. \n \n\n\n \n \n \n\n===== \n Status =====\n\n\nRuns in simulator with various test programs\nTODO - port binutils\nTODO - C compiler to generate more elaborate tests\nTODO - Some elaborate race conditions are still know to exist in the d-cache but can be avoided by crafted assembler\nTODO - Hardware verification not yet done" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jonpry name: leros32 status: Empty updated: Apr 3, 2013 wishbone-compliant: 0 - category: Memory core created: Jun 28, 2011 description: "===== \n Description =====\n\nThis project is an implementation of a unified L2-cache for a NIOS II/e processor. The cache is located between the Avalon bus and the SDRAM controller.\n\nKey features are:\n- 4-way set associative\n- 8KB cache size (2KB per way)\n- Up to 128MB of cached memory (limited by the 18-bit tags)\n- 32-bit data bus on the Avalon bus side, 16-bit data bus on the SDRAM controller side\n- 16-byte cache lines (8-word burst on the SDRAM side)\n- Cache can be used as a 8KB boot ROM during startup" language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - theshark2000 name: level2_cache_nios_iie status: Empty updated: Aug 19, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Jul 27, 2010 description: "===== \n Description =====\n\nThe lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The period of sequence generated by a n-bit LFSR is equal to 2^n-1.The tap values used are supposed to create maximum length sequence.\n\nThe size of LFSR is a generic parameter.\nThe core is designed in a way such that the seed of the process can be set from outside.\nAn output enable pin make the output bit to zero's when driven low.\n\nA testbench code is provided along with core.You can use that to verify the results.Also it is advised to create your own testbench code and test the design.If you find any bugs in the design please report them at the Bugtracker section.\n \nSince the sequence generated is not exactly random,please be careful before using this core for cryptographic purposes.\n\nIf you find this design useful please send an email to lalnitt@gmail.com.I would very much appreciate it." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lal87 name: lfsr_randgen status: Design done svn-updated: Aug 17, 2010 updated: Dec 23, 2012 wishbone-compliant: 0 - category: Other created: Jun 22, 2009 description: "===== \n Description =====\n\nLFSR Counter Generator is a command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C and is cross-platform compatible.\n\n\xC2\xA0 There is an online version of the tool at OutputLogic.comIt's more convenient to access, but the online tool is slower to generate the code for large counter values." language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - evgeni name: lfsrcountergenerator status: FPGA proven svn-updated: Jul 9, 2009 updated: Dec 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Feb 16, 2015 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: lib_hwgraphics status: Empty updated: Feb 16, 2015 wishbone-compliant: 0 - category: Processor created: Nov 23, 2012 description: "===== \n Description =====\n\nYet another free 8051 FPGA core.\n\nThis is a 6-clocker-equivalent implementation of the MCS51 architecture, aiming at area performance.\n\nA full description of the core features can be found in the datasheet.\n\nThough the core has already executed a Dhrystone benchmark in actual hardware (see below), it is still immature for actual use. A comprehensive test bench has yet to be developed, for starters. \n\n\n\n\n \n\n\n \n \n \n\n===== \n Performance =====\n\nSynthesis\n\nThese are the synthesis results for the Dhrystone demo:\n\n\n\n\nDeviceSynthesis OptionsClock RateCPUTimerUARTTotal\n\n\nAltera Cyclone-2 (-C7)Balanced62 MHz997 LEs + 29M4Ks + 1MUL985 LEs147 LEs1349 LEs + 29M4Ks + 1MUL9\nXilinx Spartan-3A (-4)Balanced35 MHz1162 LUTs + 10BRAMs + 1MUL1866 LUTs99 LUTs1424 LUTs + 10BRAMs + 1MUL18\n\n \n\nThese results have been produced with Quartus-2 11.1 sp2 and Xilinx ISE WebPack 14.3, using the project files included. The synthesis has been performed with a simple clock rate constraint (Fclk > 50MHz for the Cyclone-2 and > 16MHz for the Spartan-3) and the results must be considered illustrative only.\n\nThe Dhrystone demo includes 12KB of ROM and 2 KB of XRAM, besides the IRAM. The CPU itself uses a single memory block (M4K or BRAM) for the IRAM memory bank, all other blocks are XCODE and XDATA memory which can be configured through generics.\n\nAlso included in the total resource count are the default i/o ports and some amount of glue logic (7-segment encoders, etc.) plus any LUTs used as route-through.\n\nThe CPU includes the optional BCD instructions (DA and XCHD). Excluding them saves about 30 LEs in the cyclone version and does not affect the clock rate.\n\nNote that the number of BRAM blocks in the Spartan-3 version does not add up -- see bug tracker. The Dhrystone demo has worked on a Spartan3A dev board, though.\n\nBear in mind that the timer and the UART included in the demo are not equivalent those of the MCS51; the peripherals have been heavily simplified (UART and timer are independent, for example, and the only UART parameter that is programmable in the current version is the baud rate. More info in the datasheet.).\n\n\nBenchmark Results\n\nThe MCU has executed a version of the Dhrystone 2.1 benchmark, adapted for MCUs by ECROS Technology and slightly modified to suit the light52 core. It has been compiled with SDCC with default options.\nThe benchmark has been executed on a DE-1 development board with a Cyclone-II FPGA clocked\nat 50 MHz using the Quartus-II project file included with this project. The benchmark\nexecutes 25000 iterations over the Dhrystone loop and produces the following results:\n\n\n\nDhrystone 2.1 Benchmark Results\n1646Dhrystones per second @ 50MHz\n0.9368Dhrystone MIPS\n0.0187Dhrystone MIPS per MHZ\n\n \n\n(One Dhrystone MIPS is defined as 1757 Dhrystones per second.)\n\nAccording to the figures that can be found in this description of one of CAST's single-clocker 8051s, the above benchmark results are about twice as fast as an original 12-clocker 8051 in DMIPS/MHz, and about five times slower than a single-clocker (at the same clock rate). So this core can be characterized as a '6-clocker-equivalent'. \n\nThe actual cycle count for the instructions can be found in the core datasheet and ranges from 2 to 8 cycles (except DIV, which takes 10 cycles).\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe core has been tried on two development boards for which support files are included (a top entity, pin constraints file and a project file).\nThe project files are set up to use the Dhrystone demo object code to initialize the XCODE ROM so that they can be tried without installing SDCC or any MCS51 toolchain.\nThey can easily be used with any other program by using the appropriate package, as explained in the datasheet.\n\n\nThe supported boards are Terasic's DE-1 board for Cyclone-II and Avnet's Spartan-3A Evaluation Kit (an old board for which no link is available).\n\n\n\nIn short, this is the current status of the project:\n\n1.- Design and implementation finished.\n2.- Already tried on real hardware (Dhrystone demo on Cyclone-2 and Spartan-3A FPGAs).\n3.- No documentation other than this page, a 'quickstart' file and a draft of the datasheet.\n4.- Has not yet passed a rigorous test bench (so no test coverage info is available).\n\n\n\nThe core has passed a basic test bench that exercises all opcodes and does basic functional tests of the interrupt logic. Also it has already run a non-trivial program like Dhrystone on real chips. This means that probably few bugs remain, if any.\nYet, until a strong test bench is developed, the core must be considered suspect or 'beta'.\n\nThe next step is adding some much-needed design document explaining the internals of the core plus a detailed explanation of how the crudely hacked software simulator (source included) is used as a verification 'golden model'. Usage instructions for the core are missing too.\n\nUntil the core passes a really exhaustive test bench, you use this core at your own risk -- it has worked so far but it probably still has bugs.\nIf you want to try it anyway, check out file /doc/quickstart.txt and don't hesitate to contact me if you need help!\n\n\n\nUpdates\n\nRev. 26 (Dec. 6th 2013)\nFixed a bug affecting bit operations targetting the ACC as an SFR.\nThanks to Stephane Bouyat, who caught the bug and also gave me the solution!\nIt's taken me 3 months to fix it because I\xC2\xB4ve been relocating; now I have a development system again so further bugs will hopefully be fixed in a reasonable time :)\n\nRev. 20 (Feb. 3rd 2013)\nInterrupt handling has been refactored to make it fully compatible to the original.\nRegister IP has been implemented and the irq test code (what little there is of it) has been updated accordingly.\n\nRev. 15 (Jan. 28th 2013)\nFixed bug in DJNZ state 'djnz_dir_0'; instruction 'DJNZ dir' failed when addressing an SFR instead of an IRAM location (see bug tracker). Revision 14 passes the (modified) test bench and runs OK on the DE-1 board with the Dhrystone demo.\nThe test bench was weak enough to let this bug slip through; it has been modified to test DJNZ with both IRAM and SFR addresses but it is still very weak.\nI have modified the CPU test code to use IRAM and SFR addresses when testing direct addressing mode instructions; the new code has not uncovered any new bugs other than the DJNZ bug just fixed.\nThanks to the anonymous user who caught this bug!\n\nRev. 9 (Nov. 27th 2012)\nReplaced the absolute output path in the Quartus-2 project file with an equivalent relative path.\nThankfully, Quartus-2 by default uses relative paths to point to source files...\n\nRev. 8 (Nov. 24th 2012)\nAdded a new project file and top entity for Avnet's Spartan-3A Evaluation Kit.\nAdded a new 'led blinker' mini-demo to be used as a 'sanity check' on a board with no display or serial port, like Avnet's." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ja_rd name: light52 status: FPGA proven svn-updated: Dec 6, 2013 updated: Dec 6, 2013 wishbone-compliant: 0 - category: Processor created: Oct 25, 2007 description: "===== \n Description =====\n\nThis is a simple, small microprogrammed Intel 8080 CPU binary compatible core.\n\n\nThere are already at least two other 8080-compatible cores in Opencores, both of them well proven. This one is different because it emphasizes area instead of cycle-count compatibility or speed.\n\n\nI have tried to minimize logic size and complexity as much as possible, at the expense of speed. At about the same size as a Picoblaze on a Spartan 3 (204 LUTs + 1 BRAM), this is perhaps amongst the smallest 8-bit CPU cores available. On the other hand, it is rather slow in clock frequency and particularly in cycles per instruction (25 to 50% more clocks per instruction than the original, which is an awful lot! -- see the design notes). Besides, the 2 KBytes of dedicated fpga ram it does use may in some designs be more valuable than a large number of logic blocks.\n\n\nThe source is quite simple: a single file with some 1300 lines of straightforward, moderately commented VHDL code; plus a microcode source file from which the microcode table embedded into the vhdl was assembled. However, the simplicity may be deceptive; it can be argued that the complexity of the system has been moved from the RTL to the microcode... \n\n\nA description of the circuit and its microcode is included in the design notes and the respective source files. The microcode assembler (a perl script) is included too, though it is not necessary if you just want to use the core and not modify it.\n\n\nThis is just a fun project I created to learn vhdl; my design goal was to get the simplest possible 8080-compatible core, at the smallest possible size, at any reasonable speed. And above all, at a minimum cost in development time -- so I could get something worthy done in the very limited time available.\nThough I think I accomplished my goal, the resulting core is probably of little practical use: it is certainly no match for a picoblaze in its application niche, and it is not small enough to compensate for its lack of features (the smallest Nios II is only 2 or 3 times larger). And there are better 8080 cores around, as I said.\n\n\nI am in debt with Scott A. Moore for his cpu8080 core. Though I have not used his code in this project, I studied it and did use much of the research and test material that he made available at this site.\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Available in both VHDL and Verilog versions (thanks to Moti Litochevski) -- identical circuit.\n- Microcoded design, very simple circuit.\n - Microcode source and assembler included, though the vhdl microcode table can be edited directly.\n - Slower than original in clocks per instructions (about 25 to 50%, comparative table included in the design notes).\n- 100% binary compatible to original 8080.\n- Synchronized to positive clock edges only.\n- Signal interface very simplified. Not all original status info available (no M1, for instance).\n- Synchronous memory and i/o interface, with NO WAIT STATE ability.\n- INTA procedure similar to original 8080, except it can use any instruction as int vector.\n- Undefined/unused opcodes are NOPs.\n\n\n\n\nPerformance (standalone CPU, synthesis only):\n\n\n\nXilinx XST on Spartan 3 (-5 grade):\n\n\xC2\xA0\xC2\xA0\xC2\xA0204 LUTs plus 1 BRAM @ 80 MHz (optimized for area)\n\xC2\xA0\xC2\xA0\xC2\xA0228 LUTs plus 1 BRAM @ 100 MHz (optimized for speed)\n\xC2\xA0\xC2\xA0\xC2\xA0618 LUTs @ 53 MHz (optimized for area, no block ram)\n\n\nAltera Quartus on Cyclone 2:\n\n\xC2\xA0\xC2\xA0\xC2\xA0369 LEs plus 4 M4Ks @ 67 MHz (balanced optimization)\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe core has already executed some quite large pieces of original code in hardware, including the Microsoft Altair 4K Basic. Interrupt response has been simulated and tested in real hardware.\nThe project includes a small SoC system built around the CPU core that can be useful as an usage example or as the starting point for a real application.\nBesides, thanks to Moti Litochevski the project is now available in both Verilog and VHDL versions.\n\nCompatibility to the original Intel 8080 has not yet been achieved at 100% -- the CY flag undocumented behavior for some logic instructions is slightly incompatible. This is an issue that can't be fixed without a lot of testing with original 8080 chips, or with very accurate simulators.\n\nPlease note that the documented behavior of the CPU is 100% compatible to the original; it's only the undocumented behavior of the original silicon that has not yet been fully replicated -- only almost.\n\n\n\nWe have set up some demos to showcase the core. \n\n\n\nThe development progress can be tracked in the development log." language: Verilog & VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ja_rd - motilito name: light8080 status: FPGA proven svn-updated: Apr 10, 2015 updated: Sep 27, 2012 wishbone-compliant: 0 - category: Communication controller created: Oct 4, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jeaander name: lincontroller status: Empty updated: Jan 2, 2015 wishbone-compliant: 1 - category: Communication controller created: Nov 22, 2007 description: "===== \n Status =====\n\n- Everything was tested and is believed to be bug-free, but no warranties. \n \n\n\n \n \n \n\n===== \n Description =====\n\nVHDL implementation of the AMI --- Alternate Mark Inversion --- and HDB1 --- High Density Bipolar of order 1 line codes. \n\nFor other line code refer to: http://www.opencores.org/projects/hdbn\n \n\n\n \n \n \n\n===== \n Features =====\n\n- AMI\n - encoder\n - decoder\n - simulation files for both encoder and decoder\n- HDB1\n - encoder\n - decoder\n - simulation files for both encoder and decoder" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - ribamar name: line_codes status: Stable svn-updated: Mar 10, 2009 updated: Nov 25, 2007 wishbone-compliant: 0 - category: Arithmetic core created: Sep 27, 2011 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - atalla name: loadbalancer status: Beta svn-updated: Sep 27, 2011 updated: Sep 27, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Dec 10, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ramlogo name: log10 status: Empty updated: Feb 16, 2011 wishbone-compliant: 0 - category: Prototype board created: Nov 26, 2002 description: "===== \n Description =====\n\nThe internal Logic state Analyser (LA) is a simplified version of a standard logic state analyzer, however it is build-in the prototyped circuit and therefore allows for probing internal signals. The LA at first writes probed signals into its internal memory, and then allows for off-line transfer through WISHBONE bus to a PC where the probed data can be watched. As during design prototyping watched signals are very often changed, the LA is mainly intended for FPGAs and works similarly to Xilinx ChipScope.\n \n\n\n \n \n \n\n===== \n Features =====\n\nInternal memory for on-line data probing and off-line probed data transfer.\nGeneric number of probed signals : 8, 16 or 32 bits.\nGeneric depth of acquired data (internal memory size) (16 to 64k).\nSoftware programmable single trigger value (and don\xE2\x80\x99t care).\nSoftware programmable trigger place.\nSeparate trigger bus with generic width 1 to 32 bits.\nAcquired data and trigger clock enable.\nGeneric single or double clock operation (separate or not clock for data acquisition and system interface).\nWISHBONE compatible.\n \n\n\n \n \n \n\n===== \n Status =====\n\ndone but testing is still required" language: VHDL license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jamro name: log_anal status: Beta svn-updated: Mar 10, 2009 updated: Dec 11, 2002 wishbone-compliant: 1 - category: Testing / Verification created: Dec 20, 2013 description: "===== \n Current stable version =====\n\n/logicprobe/tags/LogicProbe-1.1\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nLogicProbe is a very simple logic analyzer which can be run on\nan FPGA in parallel with the \"device under test\". The analyzer\nhas a width of 128 data channels, and is 512 samples deep. It\nhas a trigger (i.e., it starts catching the channels when this\nsignal got active once), and a sample enable (i.e., it does only\nsample the channels when this line is 1). It uses the block RAM\non the FPGA to store the samples in real-time. When the sample\nbuffer is full, it begins to transmit the samples through a UART\n(also included in the code) over the serial line to a PC where\nthe sample values are stored in a file. A simple listing program\nallows to view the samples as hexadecimal values." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - hellwig name: logicprobe status: FPGA proven svn-updated: Dec 26, 2013 updated: Dec 26, 2013 wishbone-compliant: 0 - category: Prototype board created: Jan 4, 2013 description: "===== \n inside pc =====\n\njavascript:alert('');\n \n\n\n \n \n \n\n===== \n top view =====\n\njavascript:alert('');\n \n\n\n \n \n \n\n===== \n bottom view =====\n\njavascript:alert('');\n \n\n\n \n \n \n\n===== \n control_panel =====\n\njavascript:alert('');\n \n\n\n \n \n \n\n===== \n interrupts =====\n\njavascript:alert('');\n \n\n\n \n \n \n\n===== \n testing =====\n\njavascript:alert('');\n \n\n\n \n \n \n\n===== \n pcb samples =====\n\njavascript:alert('');\n \n\n\n \n \n \n\n===== \n part list =====\n\nVarious:\n5V input\tSMT jack 3.5mm (Ebay)\nPROG\t10pin 2.54mm JTAG header (2.5V)\nD1,D2,D3\t0805 led (marking cathode side)\nIO 20pins \t20pins 2.54 double row male header\nTX/RX\t\tPLT133_T6A/PLR135_T10 everlight\nOSC50Mhz\tABRACON_3V3_ASV_SERIE 50Mhz (mouser ASV-50.000MHZ-EJ-T)\nL1,L2,L3\t3.3uH 1.1A inductors 0806 size (mouser ref CKP20163R3)\n\n\nIcs:\nREG1\tASM1117-ADJ(1.25V)\nIC1-IC5\tQS3861PAG8 (IDT) (maybe replaced by compatible part SN74CBTD3861PWR)\nIC6\tXC3S500E PQ208\nIC7\tNCP303LSN29 open drain (DNF not required do not fit*)\nIC8\tFAN2012 for VCCO 3.3V\nIC9\tFAN2012 for VCCAUX 2.5V\nIC10\tFAN2012 for VCCINT 1.2V\nIC11\tM25P16 ST SPI flash memory\n\n\n\n\nResistor:\nR1\tASM1117 resistor adj to ground 2K2\nR2\tASM1117 resistor adj to Vout 1K\nR3,R4,R5\tresistor for 3.3V led (680R)\nR6\tVS1 to ground (0R)\nR7\t4K7 INIT_B to VCCO\nR8\tbus switch enable to ground 0R\nR9-R10\t3.3V reg. gnd-VCCO (R9 1K5 R10 4K7)\nR11-R12 2.5V reg. gnd-VCCAUX (R11 4K7 R12 10K)\nR13-R14 1.2V reg. gnd-VCCINT (R13 3K R14 1K5)\nR15\tVCCO to SPI_SS 10K\nR16\tVCCAUX to DONE 330R\nR17\tVCCAUX to PROG_B 4.7K\n\nCapacitor:\nC1,C2\tASM1117 input capacitor 10uF min\nC3,C4\tASM1117 output capacitor 10uF min\nC5-C10\t100nF decoupling bank2\nC11-C15\t100nF decoupling for bus driver\nC16\t100nf decoupling 50Mhz oscillator\nC17\tcapacitor for NCP303LSN29 1nF (DNF not required do not fit *)\nC18-C23\tinput capacitors for FAN2012 10uF 0805 X6\nC24-C29\toutput capacitors for FAN2012 22uF 0805 x6\nC30-C35 100nF decoupling bank0\nC36-C41\t100nF decoupling bank3\nC42-C47\t100nF decoupling bank1\nC48-C49\t100nF decoupling RX/TX\n\n*The device NCP303 assert FPGA prog_b if power fall below 3.0V. It is not required in normal use.\n\n \n\n\n \n \n \n\n===== \n description1 =====\n\nThe card is a PCI card.\nTested in 2 different PC(1 old intel and 1 recent AMD FX 64bits) , with 2 different PCI core (Raggedstone and mini-pci).\nThe card connect 50 PCI signals and can theorically handle all feature of the PCI bus (bus master, interrupts etc).\nThe FPGA used XC3S500E is very large and the PCI core currently use 2% of LUT space.\nThe card is basically designed from the Raggedstone V1 design from Enterpoint LTD (same bus switch, roughly same PCI connections).\nThe PCB is professionnaly manufactured , but the card is soldered by my hands. 3 units are currently assembled. They is spare PCB available for anyone interested.All the electronic components are available from Digikey or Mouser except for the Xilinx FPGA.\n \n\n\n \n \n \n\n===== \n ucf =====\n\n#Board leds\n\nNET LED_OUT LOC=\"P96\" | IOSTANDARD = LVCMOS33;\nNET LED_OUT LOC=\"P83\" | IOSTANDARD = LVCMOS33;\nNET LED_OUT LOC=\"P82\" | IOSTANDARD = LVCMOS33;\n\n#IO extension connector pin 13 and 14 are 3.3V, pin 19 and 20 are Gnd\n\nNET IO_EXT_1\tLOC=\"P152\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_2\tLOC=\"P153\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_3\tLOC=\"P150\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_4\tLOC=\"P151\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_5\tLOC=\"P146\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_6\tLOC=\"P147\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_7\tLOC=\"P144\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_8\tLOC=\"P145\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_9\tLOC=\"P137\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_10\tLOC=\"P138\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_11\tLOC=\"P128\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_12\tLOC=\"P129\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_15\tLOC=\"P126\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_16\tLOC=\"P127\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_17\tLOC=\"P119\" | IOSTANDARD = LVCMOS33;\nNET IO_EXT_18\tLOC=\"P120\" | IOSTANDARD = LVCMOS33;\n\n\n#TOSLINK fiber optic\n\nNET TOSRX LOC=\"P106\" | IOSTANDARD = LVCMOS33;\nNET TOSTX\tLOC=\"P107\" | IOSTANDARD = LVCMOS33;\n\n#user oscillator\n\nNET CLK_50Mhz LOC=\"P180\" | IOSTANDARD = LVCMOS33;\n\n#PCI bus card edge connector\n\nNET PCI_CLK\tLOC=\"P177\" | IOSTANDARD = PCI33_3;\nNET PCI_REQ\tLOC=\"P179\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P181\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P186\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P189\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P192\" | IOSTANDARD = PCI33_3;\nNET \"PCI_CBE\"\tLOC=\"P196\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P199\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P202\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P205\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P3\" | IOSTANDARD = PCI33_3;\nNET \"PCI_CBE\"\tLOC=\"P5\" | IOSTANDARD = PCI33_3;\nNET PCI_nIRDY\tLOC=\"P9\" | IOSTANDARD = PCI33_3;\nNET PCI_nDEVSEL\tLOC=\"P12\" | IOSTANDARD = PCI33_3;\nNET PCI_nPERR\tLOC=\"P16\" | IOSTANDARD = PCI33_3;\nNET PCI_nSERR\tLOC=\"P18\" | IOSTANDARD = PCI33_3;\nNET \"PCI_CBE\"\tLOC=\"P22\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P24\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P28\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P30\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P33\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P35\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P39\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P41\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P47\" | IOSTANDARD = PCI33_3;\n\nNET PCI_nINT\tLOC=\"P171\" | IOSTANDARD = PCI33_3;\nNET PCI_nRES\tLOC=\"P172\" | IOSTANDARD = PCI33_3;\nNET PCI_GNT LOC=\"P178\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P185\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P187\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P190\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P193\" | IOSTANDARD = PCI33_3;\nNET PCI_IDSEL LOC=\"P197\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P200\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P203\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P2\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P4\" | IOSTANDARD = PCI33_3;\nNET PCI_nFRAME LOC=\"P8\" | IOSTANDARD = PCI33_3;\nNET PCI_nTRDY\tLOC=\"P11\" | IOSTANDARD = PCI33_3;\nNET PCI_nSTOP\tLOC=\"P15\" | IOSTANDARD = PCI33_3;\nNET PCI_PAR LOC=\"P19\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P23\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P25\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P29\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P31\" | IOSTANDARD = PCI33_3;\nNET \"PCI_CBE\"\tLOC=\"P34\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P36\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P40\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P42\" | IOSTANDARD = PCI33_3;\nNET \"PCI_AD\"\tLOC=\"P48\" | IOSTANDARD = PCI33_3;" language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - chipmaker78 name: low_cost_pci_card status: Design done svn-updated: Jan 8, 2013 updated: Jan 10, 2013 wishbone-compliant: 0 - category: DSP core created: Mar 28, 2003 description: "===== \n Description =====\n\nThis project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD's Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the system.\n\nThe power consumption of various arithmetic architectures has been investigated, and the results have been provided in the intial report (FIRLowPowerConsiderations.doc). These results have enabled the correct power/performance optimization for the FIR filter design.\n\nThe design was produced at the gate level, enabling low-power architecture to be implemented using the extracted VHDL netlists. Each part of the design is explained within the design report (FIRLowPowerFinalReport.doc), along with the techniques for the operation of the system.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Simple operation\n- Programmable with up to 15 taps\n- Operates at sample frequency\n- Low power design, low control logic overhead\n- Power considerations and design reports available\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Filter complete and fully tested, VHDL source and testbenches available\n- Low-power analysis report available\n- FIR filter design report available" language: VHDL license: unknown maintainers: - zepler - rocktofakie name: lowpowerfir status: Stable svn-updated: Mar 10, 2009 updated: Jan 28, 2012 wishbone-compliant: 0 - category: DSP core created: Feb 1, 2010 description: "===== \n Description =====\n\nLow-Pass IIR Filter IP core is a unit to perform the Infinite Impulse Responce (IIR) low pass filter which pass frequency is tuned dynamically\n\n\nMain Features:\n\n\nDynamically tuned passband cutoff frequency in the range of 0.1 to 0.4 of the sampling frequency. The frequency is set by the 12-bit code with the linear scale.\nusing 8-staged wave digital filter scheme of the 33-d order provides both sharp frequency responce \xE2\x80\x93 up to 100 db/ octave - and high stopband ripple \xE2\x80\x93 up to 80 db. Besides the passband ripple not succedes -2,5%, or \xE2\x80\x930,23db in the whole frequency range. \nIIR wave digital filters provide both possibility to tune the cutoff frequency and excellent stability.\nFully pipelined structure provide both high clock frequency \xE2\x80\x93 up to 120 MHz, high sampling frequency \xE2\x80\x93 up to 15 MHz \xE2\x80\x93 and low hardware volume \xE2\x80\x93 960 CLB slices and 3 DSP48 units in Xilinx Virtex2P FPGA device.\n\n\nPlease, contact us if you wish to have this IP core modified or adjusted to meet your requirements.\n\n\nThis core is provided by Unicore Systems http://unicore.co.ua. To view our product list of commercial IP cores, please, follow this link" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unicore - aser name: lp_iir_filter status: Stable svn-updated: Feb 2, 2010 updated: Feb 2, 2010 wishbone-compliant: 0 - category: Other created: Apr 24, 2013 description: "===== \n Description =====\n\nHave you ever wanted to add some color to your project? Then this might be your answer. The LPD8806 RGB LED strings are available for low cost from various sites on the internet, and they come in strips which can be cut or joined to the desired length. Since the Red/Green/Blue (RGB) LEDs on the strip are driven by a serial controller IC that is also on the strip, your project can set each LED color independently of the others.\n\nThe connections to the LED strip include 4 wires: +5V, GND, clock and data. It turns out that these LED strips will also work using +3.3V as the supply voltage!\n\nThe format of the serial data stream used to drive the LEDs is given in the comments inside the VHDL code, and it can also be found by browsing the internet. The color settings are 7-bits for each color, for a total of 2^21 combinations, over 2 million different colors.\n\nThe VHDL module in this project was recently used in a Lattice Semiconductor FPGA. However, it does not include architecture specific macros, so it should be easy to use on any given FPGA or CPLD. It is parameterized so that the user can determine how many LEDs to drive, and the desired update rate to the LED string.\n\nThe color data is provided to the module by an input data bus, using an address to select which LED and which color is being loaded.\n\nMy VHDL coding style uses the \"unsigned\" type instead of the \"std_logic_vector\" type. It is easy to translate between the two using functions in \"convert_pack.vhd\", or you can go through and modify the code to use std_logic_vector instead.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe module is ready to simulate and synthesize.\n\nIt was used as part of a larger project... Since I'm not including the full code for the entire project, I am currently only providing the LPD8806 module code plus an example of how it is instantiated and used, but without a nice testbench.\n\nDon't worry, the code works. Just give it a try. If you create a testbench, please send it to me and I'll post it for others to use.\n\nNOTE:\nThere is an \"extra\" module provided in the code, which can be used to send single bytes of data to the LPD8806 string. If you want to use this module, then you'll need to provide the signals \"sel_led\", \"bus_we\" and \"bus_dat_wr(7 downto 0)\". Then you can send individual bytes, and see the separate green, red and blue LEDs light up individually in order as each new byte is received down the chain. However, if you don't want to do that, then just delete that part of the code." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jclaytons name: lpd8806 status: FPGA proven svn-updated: Apr 25, 2013 updated: Aug 20, 2014 wishbone-compliant: 0 - category: Processor created: Jan 30, 2002 description: "===== \n Description =====\n\nThis is a design that mixes processor and memory on a single chip. There are a bunch of operations surrounded by buffers. A central unit tells the data where to go. The operations work on data in certain buffers. Operations are performed by moving the data into the proper buffer. It described in much more detail in the specificaiton attatched at the bottom. I'm working on a C++ model right now. \n \n\n\n \n \n \n\n===== \n Design Flow =====\n\n- Create preliminary spec.\n- Create C++ model\n- Create code to convert x86 commands to native commands\n- Simulate operation of chip\n- Optimize C++ model\n- Convert Model to SystemC\n- Extend SystemC to handle asyncronus logic\n- ...\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Created Preliminary Spec.\n- Working on C++ model" language: C++ license: unknown maintainers: - bkorsedal name: lpu status: Planning svn-updated: Mar 10, 2009 updated: Feb 6, 2002 wishbone-compliant: 0 - category: Video controller created: May 21, 2007 description: "===== \n Description =====\n\nDriver for Sharp LQ057Q3DC02 320x240 QVGA LCD. Driver accurate to datasheet specifications. Will also work for LQ057Q3DC12 (Pb-free version).\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Fully parameterizable and easily adapted to larger LCD screen by simply changing counter register sizes and generic timing parameters.\n\n- All-digital interconnect. No digital to analog converter required. Simply attach the output ports of the top-level entity to the data connector on the LCD.\n\n- Includes specific files for the Xilinx Virtex-II Pro development board available at http://www.digilentinc.com/.\n\n- C application provided to generate the necessary BRAM COE files for Xilinx CoreGen tool.\n\n- Java application provided to generate the expected image that should appear on the screen using the provided COE files.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Design Complete and FPGA Proven" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - jwdonal name: lq057q3dc02 status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 12, 2015 wishbone-compliant: 0 - category: Processor created: Feb 8, 2008 description: "===== \n Description =====\n\nThis ClaiRISC is a soft MCU core which runs PIC 12bits instruction.Compared with PIC16F57 ,This core has the same number of register file while ports and timer are not avilable,but you can map your device register to the REGINSTER_FILE address.It uses about 240LES in ALTERA CYCLONE device. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- The architecture of ClaiRISC is very clair.\n- Written with verilog-2001.\n- Two stages pipeline.\n- Not support interrupt now.\n- Each instruction run in one clock except some \"test and skip\" instructions which run in two clock.\n- Synthesized and tested in ALTERA cyclone device at 50MHZ using 240 LES (4%)and works well.\n \n\n\n \n \n \n\n===== \n Legal =====\n\nI have no idea if implementing this core will or will not violate \npatents, copyrights or cause any other type of lawsuits.\n\nI provide this core \"as is\", without any warranties. If you decide to \nbuild this core, you are responsible for any legal resolutions, such \nas patents and copyrights, and perhaps others ....\n\nTHIS SOURCE FILE(S) IS/ARE PROVIDED \"AS IS\" AND WITHOUT ANY \nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT \nLIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND \nFITNESS FOR A PARTICULAR PURPOSE.\n\n\n\n \n\n\n \n \n \n\n===== \n IMAGE: 200735153855.JPG =====\n\nFILE: 200735153855.JPG\nDESCRIPTION: In the name of Leifeng\n\n \n\n\n \n \n \n\n===== \n IMAGE: we.GIF =====\n\nFILE: we.GIF\nDESCRIPTION: Architecture of ClaiRISC" language: Verilog license: unknown maintainers: - mcupro name: lwrisc status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 13, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Aug 1, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lzc520xm name: lzc_project status: Planning svn-updated: Aug 21, 2012 updated: Aug 1, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Apr 5, 2013 description: "===== \n Description =====\n\nThis IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed data) at the expense of an somewhat lower compression ratio. One byte of uncompressed data can be processed at every second clock\ncycle. A software decoder (decompressor) written in java is included. \nThe core is fully pipelined to allow high clock speeds. 66MHz can easily be achieved on a Spartan6\nFPGA. This results in a maximum compression throughput of almost 32MBytes/sec.\nIt uses a Wishbone compliant slave interfaces to receive uncompressed data and configuration information. A second Wishbone (master) interface is used by the included DMA unit to directly transfer the compressed data to RAM or another Wishbone slave.\nThe project includes a file based test bench which compresses externally generated input files. The compressed file can be verified with an included java tool. Both the VHDL and java code have been tested with an Spartan6 FPGA and several 100MB of hardware generated random data.\nThe core occupies ~500 Spartan6 slices using 1605 FF/LUT pairs of which 44% are fully used." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - habicht name: lzrw1-compressor-core status: FPGA proven svn-updated: Apr 7, 2013 updated: Dec 19, 2013 wishbone-compliant: 1 - category: System on Chip created: Nov 1, 2013 description: "===== \n Description =====\n\nThis project demonstrates the use of the P16C5x soft-processor core, found elsewhere on opencores.org, in a system-on-chip. The project targets a small FPGA, the Xilinx XC3S50A-4VQ100I. The project integrates the P16C5x PIC-compatible processor core an SPI Master module, SPIxIF, a Synchronous Serial Peripheral (SSP) slave module, SSP_Slv, an SSP UART, SSP_UART, and an inferred 4096 x 12 Block RAM program memory. (The SPIxIF, SSP_Slv, and SSP_UART modules are all modules that can be found on opencores.org.)\n\nThe P16C5x module is a PIC-compatible processor core that supports the 12-bit base architecture of the Microchip PIC16 product line. It extends the base architecture by supporting an additional address line into program memory. The base architecture does not implement the PA[2] program bank register in the STATUS register. The P16C5x module implements that bit, and adds an additional bit to the two-level stack so that a complete 4096 x 12 program space is available.\n\nFor compatibility with readily available PIC-compatible tools from Microchip, third-party vendors, and open-source suppliers, the P16C5x core has been parameterized such that the core's reset vector is set to be compatible with the corresponding vector of the PIC16C57/PIC16C59 microcomputer. The internal register/RAM memory map of P16C5x core has been set to be compatible with that of the PIC16C57 microcomputer: (1) I/O ports A, B, C are implemented; and (2) internal RAM is set for 72 bytes. (It is possible to increase the size of internal memory to support the banked switched memory of the PIC16C59, but the size of the FIFOs used for the UART may have to be changed to support the additional processor core RAM in the small FPGA chosen as the target for this project. Changing the FPGA to an XC3S200A-4VQ100I is possible, and that choice would allow the increase of the processor memory, and enable the use of Block RAMs for the UART FIFOs, and adding a second SSP_UART module to the M16C5X soft-microcomputer.)\n\nUnlike a Microchip PIC16C57/PIC16C59 microcomputer, the I/O ports are not built into the M16C5x's P16C5x soft-core processor module. Instead, the P16C5x soft-core provides a parallel data bus with one-hot control signals for writing the three TRIS write-only registers and the three output data registers and reading the three input data registers. This allows the core's integrator the flexibility to create custom peripherals which are tightly integrated with the processor core in a manner that reduces the number of instructions needed to access the custom peripherals.\n\nIn the M16C5x, the SPI master interface module is integrated into the core using the TRIS C register as a write-only register. The SPI transmit and receive data registers are mapped to the Port C data output and data input registers, respectively. Furthermore, to take advantage of the capability of the SPIxIF module to operate with FIFOs connected, two 16x8 distributed RAM FIFOs are attached to the SPIxIF as the transmit and receive data ports. This allows the P16C5x processor core the opportunity to process other (beyond the scope of the demonstration) I/O or perform other computational functions while an SPI transaction is automatically fulfilled by the SPI master peripheral.\n\nBeyond the testing performed with the simulator and various test benches, the M16C5x has been tested in a working board using the XC3S50A-4VQ100I FPGA. A simple test program was written using MPLAB (8.91) that simply converts lower case ASCII alpha characters into upper case characters, and vice versa. After configuring the SPI master and the SSP UART, it simply polls the UART, transforms the data, and writes it back to the UART. Even with all of this activity on the internal SPI bus, the M16C5x is able to process data at rates to 921.6 kbaud without errors or dropouts. \n\nIn the target FPGA, the smallest and lowest speed grade part in the Spartan 3A FPGA family, the M16C5x easily reports post synthesis speeds in excess of 57 MHz, and maps, places, and routes (with only simple period constraints) with reported and verified post-PAR performance better than 60 MHz. Since the core is a single cycle core, this is a substantial improvement over the capabilities of the equivalent Microchip products which are 5 MHz (effective instruction rate) devices.\n\nA final component of the M16C5x project is the demonstration of the use of the Xilinx tool, Data2Mem, that allows specially formatted ASCII hexadecimal files to be written into the block RAMs of the device during the generation of the configuration images, i.e. directly inserted by BitGen. This allows a third party developer to write/modify the contents of the M16C5x program memories without requiring the resulting data to be loaded into the Block RAMs through re-synthesis and MAP/PAR operations. The resulting improvement in the turn around time for non-RTL modifications, i.e. firmware-only mods, is dramatic and far less error prone.\n\nThe TCL script included in the RTL source directory allows the integrator of this core to take advantage of this capability. (This capability is likely available from any FPGA vendor supporting soft-core processors. It is expected that Altera (NIOS-II) and Lattice (Mico-32) toolsets provide the same type of capability, but no verification has been performed to verify that these toolsets support this capability in their base (free) configurations.) The project provides a Block Memory Map (BMM) file, sets the mapper and the configuration bitstream generator (BitGen) to support use the BMM file. The project also provides a Windows executable (and its source code) for a simple filter/console program that converts Microchip MPLAB Intel Hex output files into Data2Mem-compatible MEM files.\n \n\n\n \n \n \n\n===== \n Tool Set Compatibility =====\n\nThis core has been used with MPLAB and the CCS C compiler tools. A utility for converting from Intel Hex to Xilinx MEM files has been provided as part of this SoC project.\n \n\n\n \n \n \n\n===== \n Synthesis/PAR Results =====\n\nThe data provided in this section represents the synthesis/PAR results of building the project for a XC3S50A-4VQ100I FPGA to achieve best performance. Thus, synthesis is performed with speed as its primary objective; resource sharing is used, but register balancing (forward and backward) is allowed. Mapping is performed with an area objective to compress the resulting image as much as possible. Simple timing constraints are applied for the three internal clock domains, with the primary objective being to achieve a minimum operating speed of 60 MHz for the P16C5x core, 66.667 MHz operation for the SPI Master (internal SPI bus), and 100 MHz for the SSP UART. The UART, although capable of operating at higher speeds, is fed a 29.4912 MHz reference clock. \nModule Level UtilizationModule Level UtilizationSun Nov 3 07:42:40 2013ModulePartitionSlicesSlice RegLUTsLUTRAMBRAMMULT18X18BUFGDCM[-] M16C5x/166/110324/60473/12650/2113/30/01/40/1\xC2\xA0\xC2\xA0[-] CPU231/387116/202306/48840/400/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0ALU78/7813/13112/1120/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0IDEC78/7873/7370/700/00/00/00/00/0\xC2\xA0\xC2\xA0[-] ClkGen10/2011/245/81/10/00/01/30/1\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0ClkGen4/44/41/10/00/00/02/21/1\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0FE14/46/61/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0FE22/23/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0[-] SPI5/908/750/1350/340/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0MSTR43/4339/3967/670/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RF21/2114/1433/3316/160/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0TF21/2114/1435/3518/180/00/00/00/0\xC2\xA0\xC2\xA0[-] UART0/4400/2790/5610/1360/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0SSP_Slv50/5037/3728/280/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0[-] UART138/39081/242193/5330/1360/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0BRG15/1513/1326/260/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0[-] INT7/284/255/110/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0FE14/43/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0FE22/23/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RE14/44/41/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RE24/44/41/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RE32/23/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RE45/54/41/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RCV35/3526/2656/560/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RED14/44/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RED23/34/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RED34/44/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RED44/44/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RED55/54/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RF155/5520/2093/9372/720/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0TF151/5120/2085/8564/640/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0TMR20/2017/1726/260/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0XMT28/2820/2033/330/00/00/00/00/0\nTiming ConstraintsTiming ConstraintsSun Nov 3 07:41:40 2013MetConstraintCheckWorst Case SlackBest Case AchievableTiming ErrorsTiming ScoreYesTS_Clk = PERIOD TIMEGRP \"Clk\" 16.666 ns HIGH 50%SETUP\nHOLD0.039ns\n0.834ns16.627ns0\n00\n0YesTS_SPI_SCK = PERIOD TIMEGRP \"SPI_SCK\" 15 ns HIGH 50%SETUP\nHOLD0.337ns\n1.064ns14.326ns0\n00\n0YesTS_Clk_UART = PERIOD TIMEGRP \"Clk_UART\" 10 ns HIGH 50%SETUP\nHOLD1.318ns\n0.785ns8.682ns0\n00\n0\nXilinx Design Summary\n\n\n\nM16C5x Project Status (07/05/2013 - 18:41:59)\n\nProject File:\nM16C5x.ise\nCurrent State:\nProgramming File Generated\n\n\nModule Name:\nM16C5x\nErrors:\n\xC2\xA0\n\n\nTarget Device:\nxc3s50a-4vq100\nWarnings:\n\xC2\xA0\n\n\nProduct Version:\nISE 10.1.03 - Foundation\nRouting Results:\n\nAll Signals Completely Routed\n\n\nDesign Goal:\nBalanced\nTiming Constraints:\n\nAll Constraints Met\n\n\nDesign Strategy:\nXilinx Default (unlocked)\nFinal Timing Score:\n0\xC2\xA0\n\n\n\n\n\n\xC2\xA0\nM16C5x Partition Summary [+]\n\n\n\n\n\xC2\xA0\nDevice Utilization Summary [-]\n\nLogic UtilizationUsedAvailableUtilizationNote(s)\n\nNumber of Slice Flip Flops\n604\n1,408\n42%\n\xC2\xA0\n\nNumber of 4 input LUTs\n1,217\n1,408\n86%\n\xC2\xA0\n\n\nLogic Distribution \xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\n\nNumber of occupied Slices\n692\n704\n98%\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number of Slices containing only related logic\n692\n692\n100%\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number of Slices containing unrelated logic\n0\n692\n0%\n\xC2\xA0\n\nTotal Number of 4 input LUTs\n1,265\n1,408\n89%\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used as logic\n1,006\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used as a route-thru\n48\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used as 16x1 RAMs\n8\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used for Dual Port RAMs\n170\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used for 32x1 RAMs\n32\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used as Shift registers\n1\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\nNumber of bonded IOBs\nNumber of bonded \n20\n68\n29%\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0IOB Flip Flops\n5\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\nNumber of BUFGMUXs\n4\n24\n16%\n\xC2\xA0\n\nNumber of DCMs\n1\n2\n50%\n\xC2\xA0\n\nNumber of RAMB16BWEs\n3\n3\n100%\n\xC2\xA0\n\n\n\n\n\n\xC2\xA0\nPerformance Summary [-]\n\nFinal Timing Score:\n0\nPinout Data:\nPinout Report\n\n\nRouting Results:\n\nAll Signals Completely Routed\nClock Data:\nClock Report\n\n\nTiming Constraints:\n\nAll Constraints Met\n\xC2\xA0\n\xC2\xA0\n\n\n\n\n\xC2\xA0\nDetailed Reports [+]\n\n\n\nDate Generated: 11/03/2013 - 07:36:08\n\nNumber of BUFGMUXs\n4\n24\n16%\n\xC2\xA0\n\nNumber of DCMs\n1\n2\n50%\n\xC2\xA0\n\nNumber of RAMB16BWEs\n3\n3\n100%\n\xC2\xA0\n\n\n\n\n\n\xC2\xA0\nPerformance Summary [-]\n\nFinal Timing Score:\n0\nPinout Data:\nPinout Report\n\n\nRouting Results:\n\nAll Signals Completely Routed\nClock Data:\nClock Report\n\n\nTiming Constraints:\n\nAll Constraints Met\n\xC2\xA0\n\xC2\xA0\n\n\n\n\n\xC2\xA0\nDetailed Reports [+]\n\n\n\nDate Generated: 11/02/2013 - 13:56:37" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelA name: m16c5x status: FPGA proven svn-updated: Dec 6, 2013 updated: Nov 10, 2014 wishbone-compliant: 0 - category: Processor created: Jan 3, 2007 description: "===== \n M1 Core briefly... =====\n\nThe M1 Core is a 32-bit RISC CPU compatible with a popular GCC target.\nIt's been designed for simplicity and it's been used for some didactical activities at the University of catania.\nThe CPU is written in Verilog and it's been tested on FPGA (Xilinx Spartan-3E Starter Kit).\nThe CVS tree includes sources from other two OpenCores projects:\n\n\n\nwb_ddr developed by Joerg Bornschein\nps2_interface developed by John Clayton" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - fafa1971 name: m1_core status: FPGA proven svn-updated: Sep 7, 2009 updated: May 29, 2012 wishbone-compliant: 1 - category: Processor created: Oct 28, 2013 description: "===== \n Description =====\n\nThis project provides a microprogrammed synthesizable IP core compatible with the WDC and Rockwell 65C02 microprocessors.\n\nThis project demonstrates the integration of the core, M65C02_Core, with several components, usually supplied by the core's integrator, so that a complete soft-processor is available. The core itself expects several external components to be supplied by the integrator: (1) interrupt controller, (2) memory, and (3) I/O interface buffers. This project integrates examples of those external components with the core logic into a soft-microprocessor in a Xilinx Spartan 3A FPGA: XC3S50A-4VQ100I.\n\nFor this project, a rudimentary interrupt controller has been implemented that provides a functioning interrupt system compatible with a standard 65C02. A Block RAM is used for implementation of a Boot ROM, and a four cycle external interface is provided for easy interfacing to asynchronous SRAM and Flash EPROM. With the exception of the internal clock generator, which uses a Xilinx Digital Clock Manager (DCM), the design files uses inference for all logic. Any other FPGA family which supports synchronous Block RAMs should be able to support the core and implement the soft-microprocessor demonstrated by this project. (The core of the project has been used to synthesize a similar 65C02 microprocessor for an Altera Cyclone II/III FPGA in the DE0/DE1 FPGA development boards. This particular project is being used in a custom designed board with the Spartan 3A FPGA previously defined.)\n\nThe core of the processor is implemented using a microprogram controller (MPC). The MPC, a reimplementation of the Fairchild 9408 microprogram sequencer, provides all of the microprogram control logic used to implement the instruction sequencer and instruction decoding. The instruction sequencing control microprogram is implemented using a single Block RAM organized as 512 x 32 ROM. Of this ROM, the upper 256 words are are part of the instruction decoder. These ROM locations are used to provide the first microword of an instruction. A second, 256 x 32 Block RAM provides the control signals for the core which are fixed for each specific instruction. This second ROM essentially functions as an instruction decoder/ALU control word ROM.\n\nThe complex addressing modes of the processor requires instruction decoding to determine two components for the execution engine: (1) the addressing mode, and (2) the ALU control signals. The ROMs used in the implementation of this core provide these two functions. Essentially, when the microprogram sequence provided by the first ROM has fetched any operands required by an instruction, then the ALU is commanded to perform the necessary operations as determined by the control word provided by the second ROM. The sequence control ROM is accessed every memory cycle, and the instruction decode/ALU control word ROM is accessed once per instruction cycle. The opcode is applied to both ROMs simultaneously at the completion of the instruction fetch cycle. (Generally speaking, the concept of an instruction decoder is that of a static decoder driven by the contents of an instruction register (IR). That concept is not employed in the M65C02. The instruction opcode is simultaneously applied to both microprogram ROMs on the same cycle it is loaded into the IR. In one ROM, the instruction initiates the fetch of the next instruction, or an operand, or an address. In the other, it looks up the ALU and register control signals. The IR holds the opcode for the instruction, but it is otherwise unused in the M65C02.)\n\nThe instruction fetch cycle of the next instruction is generally overlapped with the execution of previous instruction Read-modify-write instructions break this overlapped execution cycle. Instructions which alter program flow (JMP, Bxx, JSR, RTS, RTI, etc.) also break the overlapped instruction fetch/execution model. A unique feature of this core is that branch instructions execute in 2 cycles regardless of the condition. This feature of the M65C02 core has the potential to provide save a significant number of clock cycles in any program that requires a lot of conditional branching. (The M65C02 microprogram is pipelined, and instruction execution is similarly pipelined whenever possible.)\n\nThe core is divided into four modules: (1) core, (2) MPC, (3) address generator, and (3) ALU. The core module instantiates the other three modules, provides the MPC next address/branch address logic, instantiates the microprogram and instruction decoder ROMs, implements the output data bus multiplexer, and the temporary operand registers.\n\nThe MPC incorporates the microprogram sequencer control logic, a micro-subroutine stack (not actually used in the implementation of the M65C02), and a micro-cycle length controller. The micro-cycle length controller implements a fixed length microcycle of four clocks. It also implements wait state logic which inserts memory cycle extensions of four clock. The inclusion of the micro-cycle length controller significantly reduces the issues encountered when attaching standard asynchronous RAMs and EPROMs to the M65C02 soft-microprocessor. The core logic is able to execute all instructions in a single cycle, but implementing single cycle external memory is simply not feasible at the speeds attainable with the core itself. Since the target is the smallest of the Spartan 3A family, there simply is not enough internal block RAM memory to provide a reasonable soft-microprocessor implementation. With other design constraints, the micro-cycle length could be reduced or eliminated in order to extract additional performance from the core.\n\nThe address generator incorporates the memory address register, and the program counter. Separate address generators are used for the memory address and the program counter. The focus is on overall performance, and the additional logic increases the number of slices/LUTs in the implementation. However, the additional resources allow all dead cycles to be removed. This results in many instructions having a reduced number of memory cycles compared to the W65C02 or R65C02. In fact, there is a reduction of at least 1 memory cycle in approximately 40% of the instructions. A special feature of this core is that all branch instructions require only 2 cycles rather than 2 (branch not taken) or 3 (branch taken) as is the case for a standard 65C02. Since the majority of the branches in a loop are of the branch taken variety, this optimization alone can provide a substantial improvement to a program's execution time.\n\nThe ALU contains all of the logic for the A, X, Y, P, and S registers. The ALU supports both binary and BCD modes. With the micro-cycle length controller setting the basic memory cycle as four clock periods in length, the BCD mode ADC/SBC execute in a single memory cycle. (If configured to operate as single cycle core, the decimal mode instructions automatically insert a single wait state. With the four cycle micro-cycle implementation provided, the extra cycle of the BCD instructions is absorbed into the address output phase of the following memory cycle. Thus, there's no penalty for the decimal mode ADC/SBC instructions.) In the ALU, the stack pointer is implemented as a loadable up/down counter, but it is also augmented with its own dedicated incrementer so that both push and pop operations are only 2 memory cycles in length.\n\nAs implemented in this project, the external memory interface attempts to replicate operational characteristics of the 6502/65C02 memory interface. Due to the fact that all external signals are registered in the IOBs of the FPGA, the address and data are not output until the rising edge of Phi2. This is different than a standard 6502/65C02 where the address and output data are enabled during Phi1, but not considered stable until the rising edge of Phi2. The integral micro-cycle controller acts as the Phi1/Phi2 clock generator. The basic machine/memory cycle is shifted from the micro-cycle to account for the register in the data input path of the IOB. The standard memory cycle is two clock periods for Phi1 and two clock periods for Phi2. On the falling edge of Phi2, the data from the memory is registered into the FPGA in the IOB.\n\nSeveral integral address decoders are included in the design. Although the standard 6502/65C02 R/W signal is provided, the M65C02 also provides separate read (nOE) and write (nWR) strobes signal for direct attachment to SRAMs and EPROMs. These signals do not assert except during Phi2. Thus, they should be used instead of external combinatorial logic to control the nOE and nWR signals on standard SRAMs and EPROMs.\n \n\n\n \n \n \n\n===== \n Synthesis/PAR Results =====\n\n\n Synthesis/PAR Results - XC3S50A-4VQ100I FPGA\n \n Attribute\n Used\n Avail\n %\n \n \n Number of Slice Flip Flops\n 248\n 1408\n 17%\n \n \n Number of 4 input LUTs\n 647\n 1408\n 45%\n \n \n \n \n \n Number of occupied Slices\n 400\n 704\n 56%\n \n \n Number of Slices related logic\n 400\n 400\n 100%\n \n \n Number of Slices unrelated logic\n 0\n 400\n 0%\n \n \n \n \n \n Total Number of 4 input LUTs\n 661\n 1408\n 46%\n \n \n Number used as logic\n 646\n \n \n \n \n Number used as a route-thru\n 14\n \n \n \n \n Number used as Shift registers\n 1\n \n \n \n \n \n \n \n Number of bonded IOBs\n \n \n \n \n \n Number of bonded pads\n 54\n 68\n 79%\n \n \n IOB Flip Flops\n 79\n \n \n \n \n \n \n Number of BUFGMUXs\n 1\n 24\n 16%\n \n \n Number of DCMs\n 1\n 2\n 50%\n \n \n Number of RAMB16BWEs\n 3\n 3\n 100%\n \n\n\n\n \n\nBest Case Achievable: 13.516ns (0.047ns Setup, 1.021ns Hold)\n \n\n\n \n \n \n\n===== \n Test/Verification =====\n\nThe core has undergone significant testing and verification. A Self-checking testbench is provided for the ALU. Self-checking programs, some written by me and some written by third parties, are also provided. The core and the resulting soft-microprocessor have passed all of these tests, and this provides good confidence that the processor core, as provided in this project, is very stable.\n\nKlaus Dormann's extensive 6502 functional test program has been successfully executed in both simulation and on the target HW, i.e. the XC3S50A/XC3S200A Development Board used in this project. Full source and the memory initialization files for the FPGA for this functional test program set are included in the repository. Klaus Dormann maintains this functional test program set on GitHUB.\n\n \n\n\n \n \n \n\n===== \n Limitations =====\n\nIn some applications, certain implementation decisions used in the M65C02 may produce undesired behavior, but otherwise, the core may be considered error free.\n\nFirst, the core does not attempt to replicate in a cycle accurate way the behavior of the original 6502/65C02 microprocessors. The core, as provided here, removes as many dummy memory cycles and overlaps instruction fetch and execution as much as possible. This means that many instructions execute in fewer cycles compared to the 6502/65C02 processors. Furthermore, additional address generation logic has been included so that branch instruction execute in 2 memory cycles rather than the usual 2 (condition false) or 3 (condition true) cycles required by the 6502/65C02 processors.\n\nSecond, the core implements all undefined instructions as single cycle NOPs. This implementation decision will give different results for the M65C02 than either of the 6502 or the 65C02. In the 6502, undefined instructions have side effects, some of which have proven useful to some programmers, and generally result in variable execution times. The 65C02, on the other hand, eliminated the side effects of the undefined instructions, but allowed multiple memory cycles for some undefined instructions. If existing code relies on the behavior of the 6502/65C02 to undefined opcodes, then the M65C02 core is not a potential replacement. The behavior of the 65C02, with respect to undefined opcodes, can be incorporated into the M65C02 with some simple microprogram ROM changes, which can be inserted into the final configuration bit stream using the Data2MEM utility.\n\nThird, the behavior of the M65C02 to a BRK is consistent with the intent. However, existing 6502/65C02 processors push, as the return address, the address of the second byte after the BRK instruction. This particular characteristic, coupled with the fact that the BRK and IRQ traps share a single service routine, means that debuggers and other such utilities must adjust the return address on the processor stack in order to return instruction processing to the instruction after BRK. In contrast, the M65C02 pushes the address of the BRK instruction. This means that no manipulation of the return address on the stack is required to continue with the instruction following BRK. (Note: if the BRK instruction is inserted by a dubugger, then it may require adjustment of the return address on the stack in order to restore the program to the state before the break point was inserted. If the debugger or monitor requires 6502/65C02 BRK behavior and can't be adjusted, then the M65C02 core is not a viable candidate.\n\nFourth, on the M65C02, BRK, IRQ/NMI, and JSR all push the address of the last byte in the instruction. For BRK this is the address of the BRK opcode itself, for JSR it's the address of the high byte of the target address, and for any interruptable instruction, it's the address of the last byte of the instruction. For two byte instructions, it's the address of the second byte, and for three byte instructions it's the address of the third byte. This allows the implementation of RTS/RTI using a consistent manner: the return address pulled from the stack is always incremented by one regardless of whether an RTS or RTI instruction is being executed. If specific expectations regarding the return address on the stack are not required, then the M65C02's behavior is transparent and should not be an issue.\n\nThe fifth and final limitation is that not all M65C02 instructions are interruptable. Instructions such as CLI and SEI are not interruptable. This implementation was chosen so that these instructions would not have to be implemented as two cycle instructions to account for the pipelined fetch/execute nature of the M65C02. The M65C02 also does not allow the interruption of any program flow control instruction. Thus, all jumps, branches, calls, and returns are not interruptable. Interrupts (NMI or IRQ) will be delayed until after the completion of the first instruction after a jump, branch, call, or return instruction. This means that using a self-referencing loop, e.g. Here: bra here, to wait for an interrupt is not allowed with the M65C02. Any such loop must include at least one interruptable instruction, or use the WAI instruction which is expressly intended for this situation." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelA name: m65c02 status: FPGA proven svn-updated: Dec 14, 2014 updated: Jun 15, 2014 wishbone-compliant: 0 - category: Communication controller created: Mar 9, 2014 description: "===== \n Description =====\n\nEthernet MAC Layer Switch.\nThe switch receive 100 MB/s data rate from 6\nchannels and direct each frame received to its destination port.\nThe switch is designed with :\n1. Simultaneously Read / Write frames memory - to improve latency\n2. Digital serialize / De - Serialize and digital routing core\nThe Simulation include testbench of 6 Network Adapters (NIC Hosts) \ntransmitting 100 MB/s data to the switch.\nNiC hosts are teken from the eth ip core projects as benchmarks( may be modified)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ranm11 name: mac_layer_switch status: Mature svn-updated: Jun 19, 2014 updated: May 25, 2014 wishbone-compliant: 0 - category: Communication controller created: Feb 14, 2009 description: "===== \n Description =====\n\nThis is a receiver for a Multichannel Audio Digital Interface (MADI), also known as AES-10. This type of fibreoptical or electrical connection is used in professional audio where a greater number of digital audio channel has to be transported.\n\nThe link speed of MADI is 125Mbit/s, while the data transfer rate used is 100Mbit/s. The diffrence between the two is explained by the use of a link encoding scheme. The encoding scheme used is known as 4B5B, which turns a 4 bit nibble into a 5 bit symbol. The data is NRZI encoded for a nearly DC-free link.\n\nClocking of this design is synchonous, a 25MHz clock signal has to be provided in order to receive the datastream. For synchronisation, a unique 2-symbol bit pattern is used, that can never occur in the payload of the data. The extra bandwidth between the payload speed and the data speed is filled with this bit pattern: 11000 10001 or symbols \"JK\" in 4B5B.\n\nAll of this seems very similar to a 100Mbit Ethernet connection. Therefore, an Ethernet PHY is used to receive the MADI datastream. The PHY must be able to output codegroups instead of 4 bit nibbles. A good example is the Cirrus Logic CS8952-CQZ. At the first stages of the development of MADI, AMD's TAXIchip transmitters ans receivers were used to establish the link. Nowadays, TAXIchips are outdated and nearly impossible to get, let alone use it in production. Cypress supposedly has some transceivers which also support the TAXIchip protocol.\n\nThe MADI protocol supports 56 or 64 channels of 48/44.1/32KHz digital audio, or half the number in double the sample clock. To achive an even higher sample rate, two or more channels can be combined for consecutive samples.\n\nThe design uses a wordclock output for MADI, and wordclock and bitclock input for ADAT. Thus, the design needs an external PLL block, which has a 48kHz input and is multiplied by 256 to get a bitclock. Take a look at the Cirrus Logic CS2100 for example. A PLL of such must be supplied externally in order for the design to work. If you try the make a clock multiplier in software, the ADAT signal would have too much jitter. The internal PLL in the Cyclone is not designed to use a 48kHz signal for an input (frequency is too low).\n\nThis design is now FPGA proven as I have developed a prototype board for this purpose. Interfacing to an RME HDSPe MADI soundcard, this prototype board accepts 8 ADAT inputs and turns them into a MADI signal, and converts a MADI steam into 8 ADAT outputs.\n\n \n\n\n \n \n \n\n===== \n Pictures =====\n\n\n\nThis is the prototype board\n\n\n\n\n\n\n\nA closeup, always great to manually solder those QFP's\n\n\n\n\n\n\n\n\nThe board in action on the logictap\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Slim design\n- interface to readily available 100Mbit LAN PHY\n- 25MHz clock input required\n- Outputs appoximate wordclock\n- Interfaces to 8x ADAT optical\n- Supports frames of 20,4 us as well as 10,2 us\n- Maximum of 64 digital audio channels\n- Adapts to speed changes\n \n\n\n \n \n \n\n===== \n Status =====\n\n- VHDL design done\n- preliminary testbench created. This does not create a valid MADI signal, because the frame length is not according to specification. For now it will do the job.\n- FPGA proven\n- Minor adjustments may be neccesary" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dweil name: madi_receiver status: FPGA proven svn-updated: May 2, 2010 updated: May 5, 2015 wishbone-compliant: 0 - category: Communication controller created: Nov 22, 2004 description: "===== \n Description =====\n\nBosch control keyboard and Bosch DVR/VCR send bi-phase Manchester signal in their own format to control Bosch speed doom. This converter get the data and change to UART format for the MCU to process it.\n\nThis is the signal converter on data link layer. \nAbout how to convert signal in phyical layer , there have some circuit to do it , if interest please email to me at kenneth@opencores.org to get schematic.\n \n\n\n \n \n \n\n===== \n Features =====\n\nseparate manchester signal \n\n- guard_time\n- preamble\n- sync_start\n- data\n- stop\n\n-- example : Pan Left Manchester signal on philips protocol\n-- 0000001010101010111000101010100101010110100100001111000000 \"87\"\n-- 0000001010101010111000100101010101010101100100001111000000 \"00\"\n-- 0000001010101010111000100101010101010101100100001111000000 \"00\"\n-- 0000001010101010111000100101011001010101010100001111000000 \"08\"\n-- 0000001010101010111000100101010101010101100100001111000000 \"00\"\n-- 0000001010101010111000100101011010101001100100001111000000 \"78\"\n-- 0000001010101010111000100110010101010101010100001111000000 \"02\"\n-- 0000001010101010111000101001011001010101100100001111000000 \"09\"\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe project was finished and working so far so good." language: VHDL license: unknown maintainers: - kenneth name: man2uart status: FPGA proven svn-updated: Mar 10, 2009 updated: Nov 16, 2009 wishbone-compliant: 0 - category: Communication controller created: Aug 14, 2012 description: "===== \n Description =====\n\nManchester encoder decoder" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vivekv name: manchester_encoder_decoder status: Empty updated: Aug 14, 2012 wishbone-compliant: 0 - category: Communication controller created: Aug 10, 2014 description: "===== \n Description =====\n\nThis is a Manchester encoded UART that enables runing small periferals with parasitic power derived from the TXD line, and allowing large clock differences typical of RC oscillators.\n \n\n\n \n \n \n\n===== \n ManchesterUart =====\n\nWhat it is:\nThe Manchester UART replaces a standard UART. Instead of the NRZ coding of byte, it uses a Manchester protocol and encodes a 16 bit data word. The Manchester protocol transitions in the middle of the bit time. A rising transition is considered a one, and a falling transition is considered a zero. In order to get the correct edge in the middle of the bit time, there may be or may not be a transition at the beginning or end of a bit time. The Manchester UART is high when idle. The word is encoded similarly to a normal UART, with a start bit, 16 data bits (LSB first), and a stop bit. Start and stop bits are encoded as ones.\n\nWhat it is not:\nThe Manchester UART is not a Manchester encoder/decoder. Manchester encoder/decoders have continuous transitions and require higher layers of protocol to construct frames and syncs.\n\nWhy you might use it:\nThe Manchester UART is most useful for communicating with devices that use the same lines for communication and power. Such a system is often referred to as parasitic power. Because the Manchester encoding has a maximum low pulse width of 1 bit time, as opposed to 9 bit times for a standard UART, you can use less capacitance to maintain the power during the lows of the communication stream. Another advantage is that the timing for the Manchester UART resyncs on every bit, whereas a standard UART syncs on the first edge of the start bit, and has to maintain the timing from that first edge to the sample of the stop bit, some 9.5 bit times later. This means the Manchester UART is much more tolerant of clock drifts, and can tolerate RC oscillators. The test bench actually simulates the clock differences between the transmitter and receiver, and can tolerate over plus or minus 18% clock rate differences." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - skeptonomicon name: manchesteruart status: Alpha svn-updated: Nov 12, 2014 updated: Nov 12, 2014 wishbone-compliant: 0 - category: Communication controller created: Jun 10, 2009 description: "===== \n Description =====\n\nThis core decodes incoming Manchester encoded data. The core is easily modified for your particular project, in that there are just a few constants that you must change. \n\nThis project is in an alpha stage and is currently too susceptible to other radio noise. In our development environment, there is currently a 25-50% error rate, which comes from the algorithm misidentifying signal for noise and noise for signal.\n\nObtain the most current code with:\nsvn co http://opencores.org/ocsvn/manchesterwireless/manchesterwireless/tags/release-1.0 manchesterwireless --username your_username \n\nOnce the code is checked out, you will find the manual in documentation/design.txt." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - kingmu - thiagu_comp name: manchesterwireless status: FPGA proven svn-updated: Jul 11, 2009 updated: Jun 24, 2009 wishbone-compliant: 0 - category: Processor created: Feb 1, 2007 description: "===== \n Description =====\n\nMcAdam's RISC Computer Architecture (marca) is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and featuring a 4-stage pipeline.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 16 16-bit registers\n- Harvard architecture\n - all memories on-chip\n - 16KB instruction ROM\n - 8KB data RAM\n - 256 byte data ROM\n- load/store instruction set architecture\n - 75 instructions\n- 16 interrupt vectors\n- 4-stage pipeline\n \n\n\n \n \n \n\n===== \n Status =====\n\n- running on an Altera Cyclone FPGA" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - jeunes2 name: marca status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 2, 2007 wishbone-compliant: 0 - category: Arithmetic core created: Jun 15, 2006 description: '' language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - michland - vv_gulyaev name: matrix3x3 status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 26, 2007 wishbone-compliant: 0 - category: Prototype board created: Jun 15, 2005 description: "===== \n Description =====\n\nThe MAXII-Evalboard is a small and simple board for learning VHDL und testing the own VHDL-codes on a real CPLD-hardware.\nFor the first steps the beginner has 4 switches and a 2 digit LED-display to create and test simple functions.\nLater the advancer can realize a small graphical display with 10x7 LED-pixel with a time multiplex control and a communication link via a USB-UART-Connection to a PC.\nTo expand the MAXII-Evalboard with a additionally hardware all pins of the CPLD are routed to pin contact strip.\nThe MAXII-Evalboard based on the Altera EPM570T100 CPLD and includes the JTAG-programming cable to program the CPLD via the LPT-Port.\nThe board is powered by the USB-port of the PC.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n* Altera EPM570T100 CPLD\n* 2-digit LED-matrix display\n* 4 user-switches + reset\n* Data-connection to PC via USB-UART FTDI FT232BM-chip\n* Integrated JTAG-programming cable to LPT-port\n* Wire-wrap connector to expand with additionally own hardware\n* Power-supply via USB\n* 6 MHz quarz clock\n* 1 kHz RC-oscillator\n* 2-layer PCB 83,2 x 61 mm \n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe board is in a final state V1.0 and is mostly tested\n\nFollowing design files are available:\n* Protel-design-files\n* Gerber-files to order PCBs\n* Schematics, PCB-Prints in PDF-format\n* Bill of materials\n\nQuartus II design-samples to test the board are coming sonn\n\n \n\n\n \n \n \n\n===== \n IMAGE: MAXII-Evalboard_V1.0_a.jpg =====\n\nFILE: MAXII-Evalboard_V1.0_a.jpg\nDESCRIPTION: MAXII-Evalboard with cables\n\n \n\n\n \n \n \n\n===== \n IMAGE: MAXII-Evalboard_V1.0_b.jpg =====\n\nFILE: MAXII-Evalboard_V1.0_b.jpg\nDESCRIPTION: MAXII-Evalboard" language: Other license: unknown maintainers: - hkuester name: maxii-evalboard status: Stable svn-updated: Mar 10, 2009 updated: Jun 26, 2005 wishbone-compliant: 0 - category: Video controller created: Jun 12, 2006 description: "===== \n Features =====\n\n- Baseline JPEG encoder\n- Baseline JPEG decoder (Not ready yet)\n \n\n\n \n \n \n\n===== \n Introduction =====\n\nThis is an open source JPEG codec, including both encoder and decoder (decoder is not ready yet), for embedded systems. It can be fully synthesized and implemented on FPGA. There is also a four-processor design based on it http://opencores.org/project,mpdma,mpdma20061023c.tar.bz2\n\nDifferent to a fully hardware implementation, this JPEG codec is designed based on Xilinx Microblaze processor with customized hardware accelerators. It is expected to achieve high flexibility, low complexity at little cost of size and performance. We aim to archive real time motion JPEG codec on a Xilinx Spartan X3S1000 equivalent FPGA (including I/O and memory controller). **\n\nYou can open the project with Xilinx EDK7.1 or higher and synthesize by Xilinx ISE7.1. * The verification hardware platform I use is Xilinx XUP board with a Xilinx XC2V30P on it. It provides necessary peripherals such as CF card for image storage and video output. The board can be obtained at the cost of 300 euro if you are in a university. Simulation is not tested yet.\n\nThe code here includes two parts, a JPEG codec library and a test bench. The library includes both hardware and software. The test bench is to read a BMP file from CF card, drive JPEG code library to compress it and write the JPG file back to CF card. You can also make your own design to play with camera and video output based on it.\n\nThe JPEG codec library can also be used as a library or IP core for image processing and video compression applications, for instance, MPEG codec. The IP cores can be integrated immediately. It is actually part of my master thesis project and I try to write down in detail how I design and how to use it. Enjoy!\n\n* Some intermediate version can only be open and synthesized by Xilinx EDK 8.1 and ISE 8.1, as indicated respectively.\n** X3S1000: 1M Gates, 1920 CLBs, 432Kbits BRAM, Current implementation: 3460 CLBs, 589Kbits BRAM\n\n*** Call for Participation ***\nThe accelerator is not done yet. It would be a nice project for university students or engineers who is interested in FPGA design. Please drop me an email if you like to join.\n\n\n \n\n\n \n \n \n\n===== \n Roadmap =====\n\nFor encoder\n1. Setup the testbench and development environment\n1.1 Simple environment with CF card and without external memory *\n1.2 Full environment with CF card and external memory *\n2. Port reference code to microblaze \n2.1 Port code to XUP2PRO platform and microblaze processor *\n2.2 Elaborate code for memory and platform independance *\n2.3 Elaborate code for multiprocessor support\n2.4 Elaborate code for multitask OS support\n2.5 Elaborate code for speed\n3. Design a simple FSL accelerator to evaluate the FSL design flow \n3.1 Design a FSL accelerator for MAC operation *\n4. Design DCT FSL accelerator\n4.1 Update Fast DCT algorithm ( 4.2 Design Accelerator\n5. Design color conversion accelerator\n6. Design vlc accelerator\n7. Port code into and optimize for different platforms\n7.1 Port to Xilinx Spartan III board\n7.2 Add Subsampling support *\n8. Experiment for Motion JPEG streaming\n9. Start to design MPEG codec... :)\n\nA project to design multiprocessor system on FPGA is based on this design. It can be found at http://opencores.org/project,mpdma,overview\n\nFor decoder, it is roughly the same.\n\n* Done\n\n\n \n\n\n \n \n \n\n===== \n Milestones =====\n\n1. 2006/07/05 Step 1.1 - Setup the testbench and development environment/Simple environment with CF card and without external memory (Sunwei) CVSTag: STEP1_1 (EDK/ISE8.1)\n\n2. 2006/07/18 Step 2.1 - Port reference code (Joris van Emden) to Microblaze and XUP2PRO board (Sunwei) CVSTag: STEP2_1b (EDK/ISE8.1)\n\nYou can download this bitstream to an Xilinx XUP2PRO board with CF card and it can compress image01.bmp on CF card to image01.jpg and write back to CF card. Due to current implementation limit, the BMP file size can not exceed 64KB for this version of bitstream. It is fixed later.\n\n3. 2006/07/20 Step 3.1 - Design a FSL accelerator to do MAC operation (Sunwei) (EDK/ISE8.1)\n\n4. 2006/07/28 Step 2.2 - Elaborate code for memory and platform independance. \nThe code is elaborated and memory usage is reduced. The code can also be compiled and run on PC without any modification. (Sunwei) CVSTag: STEP2_2b (EDK/ISE8.1)\n\nThe code size is reduced 30% and data size 50%. Now with the same capacity to V0.1 code it need only 32KB code and 32 KB data memory for microblaze processor on FPGA, compared to 64KB code plus 64KB data in V0.1 design. The software code is platform independant and can be compiled on PC as well.\n\n5. 2006/09/15 Step 7.2 - 4:2:0 Subsampling support. The compression ratio is doubled. (Marcel) CVSTag: STEP7_2 (EDK/ISE8.1)\n\n1) 4:2:0 Subsampling is supported and the compression efficiency is doubled.\n2) Reduce file system resource usage. For xilfatfs, CONFIG_BUFCACHE_SIZE 2560 (default 10240), CONFIG_MAXFILES 2 (default 5), CONFIG_WRITE true (default false)\n\n6. 2006/11/04 Step 1.2 - Add external memory support (Sunwei) CVSTag: STEP1_2c\n\nThe BMP file buffer is set to external memory and limitation is as large as 256MB if you use 256MB memory module. Code and data except for BMP file buffer is still in on-chip memory.\n\n\n\n \n\n\n \n \n \n\n===== \n BitStream to Download =====\n\nBitstreams are in CVS/bitstreams directory (http://www.opencores.org/cvsweb.shtml/mb-jpeg/bitstreams/). To download a bitstream to Xilinx XUP2PRO board, you can use impact -batch download_XUP2PRO.cmd in EDK shell. Please note that the bit file to download is set in cmd file for the latest version. If you need to download an old version, it is necessary to modify cmd file.\n\nSource files can be downloaded from the 'Downloads' tab (http://www.opencores.org/pdownloads.cgi/list/mb-jpeg).\n\n1. V0.1 2006/07/19 (CVSTag Step2_1b)\n2. V0.11 2006/07/28 (CVSTag Step2_2b)\n3. V0.2 2006/09/15 (CVSTag Step7_2)\n\n\n \n\n\n \n \n \n\n===== \n Document =====\n\nThere is a brief description of the project (http://opencores.org/svnget,mpdma?file=/web_uploads/SoftwareMultiprocessoronFPGA20070608.pdf)\n\nand my master paper\nhttp://opencores.org/usercontent,doc,1297836039" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - quickwayne - sssf - mlauwerijssen name: mb-jpeg status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 16, 2011 wishbone-compliant: 0 - category: Processor created: Jun 19, 2009 description: "===== \n Introduction =====\n\nThe MB-Lite microprocessor is a ligth-weight implementation of the Microblaze Instruction Set Architecture. It is instruction and cycle compatible with the Microblaze EDK 10.1i. It is successfully tested on older and newer Xilinx platforms (EDK 9 and 11). The design has been successfully synthesized for an Altera board as well to show platform independence.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nMB-Lite is a highly modular design and is therefore very simple to understand and modify. Features of the MicroBlaze architecture and MB-Lite implementation are:\n\n\n\n32-bit data- and instruction bus\nHarvard architecture\nFive pipeline stages\nCycle as well as instruction compatible with the MicroBlaze Instruction Set Architecture\nOptional interrupt support\nOptional wishbone bus\nOptional multiplier\nOptional barrel shifter\n\n\n\nThe following instructions are currently not implemented. All of these instructions are not used by the compiler (mb-gcc) or can be replaced by software libraries.\n\n\n\nMULH, MULHU, MULHSU\nIDIV, IDIVU (Integer Division)\nTN* (Fast Simplex Link instructions)\nF* (Floating point instructions)\nPCM* (Pattern Compare)\nWIC, WDC (Cache instructions)\nMTS, MFS, MSR* (Special purpose register instructions)\nRTBD, RTED (Return from break / exception)\n\n \n\n\n \n \n \n\n===== \n Included design examples =====\n\n\n Integer unit directly connected to instruction- and datamemory\n Integer unit with wishbone bus wrapper\n Integer unit with address decoder\n Integer unit with address decoder and wishbone bus adapter\n SOC for synthesis purposes\n\n \n\n\n \n \n \n\n===== \n Methodology =====\n\nThe core is designed using the two-process design methodology of Jiri Gaisler. All modules use inferred components, the design is not targeted specificly to any platform. However, currently it is only tested on a Xilinx Spartan 3 FPGA. All memory blocks and registers will synthesize to BRAM on xilinx devices.\n\n\n \n\n\n \n \n \n\n===== \n Organization =====\n\nThe organization of the hardware corresponds closely to the implementation of the classic RISC pipeline of Hennesy & Patterson (Computer Organization and Design: The Hardware/Software Approach).\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Performance =====\n\nMB-Lite is tested on a Virtex 5 development board (XC5VLX110-3FF 1760). It is able to obtain 229 MHz (c.f. the original implementation obtains 227 MHz). Furthermore, MB-Lite has a lower Cycles Per Instruction (CPI) than MicroBlaze since MicroBlaze has a prefetch buffer which reduces the rate of instructions which can be fed into the processor. The execution time of MB-Lite is therefore approximately 10% lower than MicroBlaze.\n\n\n \n\n\n \n \n \n\n===== \n TODO / Wishlist =====\n\n\n Modify wishbone bus to support single cycle transfers\n Add Fast Simplex Link (FSL)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - takar - renevanleuken name: mblite status: ASIC and FPGA proven svn-updated: May 15, 2011 updated: Jan 27, 2015 wishbone-compliant: 1 - category: Arithmetic core created: Sep 30, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mezzah name: mcip_open status: Alpha updated: Oct 1, 2014 wishbone-compliant: 0 - category: Processor created: Jul 31, 2007 description: "===== \n MCPU - Minimal CPU for a 32 Macrocell CPLD =====\n\nMCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.\n\nPlease let me know if you find a good use for this CPU and put your project/publication/lecture notes on the web. I will try to maintain a list here. I know it already has found good use for many purposes.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe CPU is accumulator based and supports a bare minimum of registers. The accumulator has a width of eight bits and is complemented by a carry flag. The program counter (PC) has a width of six bits which allows addressing of 64 eight bit words of memory. The memory is shared between program code and data.\n \n\n\n \n \n \n\n===== \n Status =====\n\nSee Github for latest updates\n \n\n\n \n \n \n\n===== \n Downloads =====\n\nI moved the project archive over to Github for easier maintenance. \nYou can find the latest version here: Github repository\n\nThe opencore archive will stay a v1.06b" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: mcpu status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 20, 2014 wishbone-compliant: 0 - category: Processor created: Sep 24, 2012 description: "===== \n Description =====\n\nThe Intel 4004 was the first commercially-available single-chip CPU. Developed by Intel in 1969 for the Busicom company for use in the Busicom 141-PF calculator, and made commercially available for other uses in November 1971, the 4004 CPU and the other MCS-4 family chips were used in embedded applications into the mid-1980s.\n\nThis project is a translation of the pMOS, dynamic-logic MCS-4 chip set design into static-logic, functional Verilog that can be synthesized for most any FPGA. The implementation intentionally uses the net naming convention found in the 400x simulator available from the 35th Anniversary website (http://www.4004.com). Plans include support for the 4004 CPU, the 4001 ROM, 4002 RAM, and 4003 Output expander chips.\n\nComponents from this project can be used to synthesize a complete, working, cycle-accurate, MCS-4 system in an FPGA.\n\nA somewhat rambling blog describing this project, and companion project to implement the 4004 CPU using discrete components, can be found here: http://insanity4004.blogspot.com\n\n\n \n\n\n \n \n \n\n===== \n License =====\n\nIntel has licensed the use of the 4004 CPU schematics, chip mask images, and other documentation under a non-commercial license: http://www.intel.com/museum/4004ipnclicense.htm\n\nIntel also provided written confirmation to use other MCS-4 related materials in this work and publish non-commercially the recreated source materials of 4001 ROM, 4002 RAM and 4003 schematics and 4001 layout under a Creative Commons license. It is available now 'By-attribution, Non-Commercial, Share-Alike' (BY-NC-SA) as described here: http://creativecommons.org/licenses/by-nc-sa/3.0/legalcode\n\nSince this project is derived from the schematics and other documentation licensed above, it necessarily carries the same non-commercial license grants and restrictions. \n\n\n \n\n\n \n \n \n\n===== \n Current Status =====\n\nNov 12, 2012:\n\nAt long last, some Verilog source code! I've uploaded the core modules that make up the 4004 CPU. Test bench code and modules that make up the 4001 ROM will be uploaded in the near future.\n\n\nSep 24, 2012:\n\nAlthough I've listed the project as being in the \"planning\" state, the 4004 CPU is fully coded and runs simple test programs in simulation. The ROM portion of the 4001 is mostly coded and sufficiently functional to support the 4004 CPU testing; the I/O portion is partly coded and totally untested.\n\nVerilog source code will be posted after I've done some clean-up to align it more closely with the OpenCores HDL modeling guidelines and include appropriate license info in the file comments." language: Verilog license: multiple maintainers: - rrpollack name: mcs-4 status: Alpha svn-updated: Nov 19, 2012 updated: Nov 13, 2012 wishbone-compliant: 0 - category: Processor created: Jun 18, 2008 description: "===== \n Description =====\n\nThe goal of this project is to create a very well documented, fully synthesizable VHDL model of an 8-bit microcontroller with extended peripheral set. The model should be highly configurable, making it possible to exclude unused peripheral units. These features make it a very good choice for SoC (System-on-a-chip) designs and for purely educational purposes.\nAn assembler and a testbench describing the behavior of both program and data memory are provided.\n\nhttp://www-user.tu-chemnitz.de/~dimo/opencores/cpu8.gif\n \n\n\n \n \n \n\n===== \n Features =====\n\n- assembler \n- testbench describing the behavior of program and data memory\n- Makefile for synthesis with XST (Xilinx) and simulation with Modelsim (Mentor Graphics) \n \n\n\n \n \n \n\n===== \n Status =====\n\n- Implemented Modules\nsrc/control.vhd\nsrc/alu.vhd\nsrc/pc.vhd\nsrc/reg.vhd\nsrc/ram_control.vhd\nsrc/components.vhd\nsrc/cpu_types.vhd\nsrc/ram.vhd\nsrc/rom.vhd\nsrc/processor_E.vhd\nsrc/processor_tb.vhd\n\n- Implemented Instructions\nNOP -- no operation\nNEG -- bitwise nagation\nAND -- bitwise logical AND\nEXOR -- bitwise Exclusive-OR\nOR -- bitwise OR\nSRA -- shift left through carry\nROR -- rotate left through carry\nADD -- add without carry\nADDC -- add with carry\nJMP addr -- unconditional jump \nJMPC addr -- jump if carry set\nJMPZ addr -- jump if zero set\nLDA const -- load Accumulator Immediate\nLDB const -- load Extension Register Immediate\nLDA addr -- load Accumulator Direct\nLDB addr -- load Extension Register Direct\nSTA addr -- store Accumulator \n\n- Implemented Peripheral\n - Memmory mapped LCD Controller\n - PWM Unit\n - WDT\n \n\n\n \n \n \n\n===== \n History =====\n\n10.08.2008\n- testbench coverage improved\n- fixed bug in the ALU\n\n03.07.2008\n- new assembler programs added\n- improved testbench\n- fixed bug in the control unit\n\n02.07.2008\n- fixed bug in the register block\n- scipts for backannotated simulation added\n\n27.06.2008\n- SRAM controller modificated\n- overall performance improved (293 clocks for the reference multiplication program)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dimo name: mcu8 status: Alpha svn-updated: Mar 10, 2009 updated: Aug 10, 2008 wishbone-compliant: 0 - category: Crypto core created: Jul 31, 2014 description: "===== \n Description =====\n\nA high throughput, 64-stage pipelined implementation of MD5 written in Verilog. Completes one hash per cycle." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - JohnLeitch name: md5_pipelined status: FPGA proven svn-updated: Dec 8, 2014 updated: Nov 27, 2014 wishbone-compliant: 0 - category: Communication controller created: Sep 3, 2013 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - navalps name: mdc_mdio status: Empty updated: Sep 4, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Apr 14, 2006 description: "===== \n Description =====\n\nNEW: 12 bit input MDCT version created by Emrah Yuce has been added to project downloads.\n\n\nParallel synthesizable implementation of 2D DCT in VHDL. Currently works on 8 bit input data using 12 bit DCT coefficients (12-bit DCT output). Multiplier-less design, parallel distributed arithmetic with butterfly computation used instead. Implementation done as row-column decomposition, two 1D DCT units and transpose matrix between them (double buffered as ping-pong buffer for performance). Latency (time between first 8 bit input data is sampled and first dct data present on output) is 94 clock cycles. \n\nSelf-veryfing testbench included which takes matlab-converted image as input. Core transforms it to DCT coefficients and behavioral IDCT testbench code reconstructs from it original image. PSNR is computed between original and reconstructed image to find out error introduced by fixed point arithmetic, for sample Lena images PSNR is 48 dB.\n\nMatlab scripts are included for computing floating point DCT/IDCT as reference. Scripts for converting 8 bit bitmap to txt format readable by testbench and vice versa are also available.\n\nCore was tested on Digilent S3 board with Spartan Xc3S1000 FPGA.\n\n\n \n\n\n \n \n \n\n===== \n Performance/Area =====\n\n+ 8 bit input, 11 bit output\n+ Throughput 10 MSamples/s with 10 MHz input clock\n+ Latency 94 clock cycles\n+ Transforms 8x8 block of 64 samples in 64 cycles when pipeline is full\n+ FPGA proven\n \n\n\n \n \n \n\n===== \n IMAGE: block_diagram.jpg =====\n\nFILE: block_diagram.jpg\nDESCRIPTION: MDCT block diagram\n\n \n\n\n \n \n \n\n===== =====" language: VHDL license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - mikel262 - emrahyuce - bergy name: mdct status: FPGA proven svn-updated: Mar 17, 2009 updated: Mar 7, 2009 wishbone-compliant: 0 - category: System controller created: Sep 25, 2001 description: "===== \n Description =====\n\nThis is a advanced Memory Controller intended for embedded applications. Some of the features are: \n\n- SDRAM, SSRAM, FLASH, ROM and many other devices supported \n- 8 Chip selects, each uniquely programmable \n- Flexible timing to accommodate a variety of memory devices \n- Burst transfers and burst termination \n- Performance optimization by leaving active rows open \n- Default boot sequence support \n- Dynamic bus sizing for reading from Async. Devices \n- Byte parity Generation and Checking \n- Multi Master memory bus support \n- Industry standard WISHBONE SoC host interface \n- Up to 8 * 128 Mbyte memory size \n- Supports Power Down Mode \n \n\n\n \n \n \n\n===== \n Status =====\n\n- May 2002, The core has been verified in hardware. This project is now completed.\n- 8/2/2001 I have fixed various bugs and made many small changes and am still trying to improve and debug the memory controller further. \n- New Directory Structure ! We have agreed on a common directory structure at OpenCores. \n- I will post a message to cores@opencores.org each time I have an update \n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: mem_ctrl status: Stable svn-updated: Mar 10, 2009 updated: Jan 11, 2010 wishbone-compliant: 1 - category: Memory core created: Sep 25, 2001 description: "===== \n Description =====\n\nCheck the memory cores site for more documentation at Jamil Khatib site.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- VHDL codes are stable and available on the CVS \n- Some cores need test benchs \n- we need more memory cores with different features \n- we need more people to test the cores on real hardware \n- You can download the memory codes from the CVS using the module name \"memory_cores\" and for new cores use module name \"memory_cores2\". \n- Note: it is recommended to download the whole module because files are dependent on each other" language: VHDL and Verilog license: custom licensetext: "This VHDL design file is an open design; you can redistribute it and/or\nmodify it and/or implement it under the terms of the Openip General Public\nLicense as it is going to be published by the OpenIP Organization and any\ncoming versions of this license.\nYou can check the draft license at\nhttp://www.openip.org/oc/license.html\n" maintainers: - khatib name: memory_cores status: Stable svn-updated: Mar 10, 2009 updated: Oct 14, 2001 wishbone-compliant: 0 - category: Memory core created: Dec 19, 2001 description: "===== \n Description =====\n\nThe memory_sizer project is designed to automatically handle accesses to and from memory. It does not handle refreshing DRAM at all, but it does automatically generate the cycles needed to fulfil a memory request by a processor. For example, it can load 32-bit words from byte wide memory (if you want to boot from a single byte-wide flash chip, for instance). Alternatively, it could load 16-bit words from byte wide memory. It also handles loading and storing bytes from 32-bit wide memory and 16-bit memory, although the memory in this case must support the use of \"byte enables.\" This is done dynamically, so that multiple widths of memory may be shared in the same address space. Moreover, memory_sizer can load and store data using misaligned adresses (as does the power PC architecture!) which is a very difficult proposition, if you need to do misaligned accesses, because it involves splitting an access across the boundaries of the given memory. The memory_sizer handles these misaligned accesses automatically. Also, memory_sizer can do \"little endian\" or \"big_endian\" accesses. A single input to the module determines which mode is used.\n\n\n\nOne particularly nice feature of this block is that it is scalable in size by changing the parameters. This means that if you want to generate accesses which are 64-bits wide, 128-bits wide, or even 256-bits wide, you may do so. Simply change the appropriate parameters, and the memory_sizer module will produce the appropriate access cycles, with address and byte enables being generated automatically, for both loads and stores. Of course, it will then consume more resources, there is no escaping that!\n\n\n\nIf you wish to simplify this module, in order to save resources on your target chip, then simply tie the unused inputs to the desired state to constrain them, and the synthesis tools will \"optimize away\" the unneeded portions of the logic. For instance, if you do not want little_endian/big_endian support, just tie that input to zero or one, and the resulting synthesis will take up less space, and run faster.\n\n\n\nThe code is written in Verilog, and was sythesized into a Xilinx SpartanII XC2S200 chip. Debugging was done in actual hardware, with an HP16500 series logic analyzer, and there is no simulation testbench for these modules.\n\n\n\n\nThe design team of memory_sizer welcomes any kind of help and feedback on these cores. If you are interested in further development of this project, please contact us.\n \n\n\n \n \n \n\n===== \n Features =====\n\nThese cores have been coded completely, synthesized and tested for correct operation (and debugged!) inside a Xilinx XC2S200 chip. The tools used for development were the Xilinx Foundation 3.1i (non-ISE) tools.The original \"memory_sizer.v\" supports bus switching to re-use the same hardware for writes and reads. It was tested at 12.5 MHz, and uses 200 Virtex slices.The second version, \"memory_sizer_dual_path.v\" uses separate paths for writing and for reading. It is faster (tested at 25MHz) and uses 300 Virtex slices...There are no technology-dependent elements used in these cores, except for the block DPRAMs, which can be replaced by their generic equivalents.The cores are parameterized to allow changing timer values to accomodate different clock speeds.The code has good comments.An example interface is given, showing how the \"memory_sizer\" and \"memory_sizer_dual_path\" modules were tested using rs232_syscon commands through Windows hyperterm. (See opencores project \"rs232_syscon\" for further details on this interface.)The wait states needed by the memory are not defined in the \"memory_sizer\" module. A \"memory_ack_i\" line is used to indicate that the memory is ready to proceed with the access cycle, so that wait state logic may be defined as you wish it to be." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jclaytons name: memory_sizer status: Stable svn-updated: Mar 10, 2009 updated: Dec 21, 2001 wishbone-compliant: 1 - category: Arithmetic core created: Jan 2, 2013 description: "===== \n Description =====\n\nThe MESI InterSection Controller (ISC) is a coherence system controller. It supports the MESI coherence protocol for a cache data consistency. It synchronizes the memory requests of the system masters. It enables to keep the consistency of the data in the memory and in the local caches.\nThis project provides the following elements:\n\n A synthesizable controller core with a complete environment of verification, synthesis, and documentation.\n Instructions for integrating MESI_ISC to a system.\n A definition and requirements of the system masters.\n \nFor a detailed description see the\n\n===== MESI_ISC Specification (ver 0.12) =====\n\nProject status:\n\n Documentation: On progress. Main chapters have written.\n RTL: Done.\n Verification: On progress. A basic test plan has done.\n Synthesis: On progress. Initial synthesis has passed successfully.\n \n\n\n A schematic diagram of a coherency system with MESI_ISC:\n \n \n\n \n\n \n\n Project's Environment Structure \n \nThe full environment of the project can be downloaded here. The following drawing describes the directories structure of the environment." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - yaira name: mesi_isc status: Alpha svn-updated: Jan 31, 2013 updated: Mar 17, 2013 wishbone-compliant: 0 - category: Prototype board created: Sep 25, 2001 description: "===== \n Description =====\n\nMicro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip.\n\n\n\nFPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. It is designed for debugging and verification process of small units or cores. See a block diagram for details.\n\n\n\n\n\nPicture 1: Block diagaram\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- board is finished and it is fully functional\n \n\n\n \n \n \n\n===== \n Shematic sources =====\n\n\nSchematic as Adobe PDF document\nSchematic in Protel Binary format\nLibrary in Protel Binary Library format\nSchematic in Orcad format (exported from Protel)\n\n \n\n\n \n \n \n\n===== \n Maintainer =====\n\nAndrej.Trost@fe.uni-lj.si\n\n\nMailing-list:\ncores@opencores.org" language: Other license: unknown maintainers: [] name: mfpga status: Stable svn-updated: Mar 10, 2009 updated: Mar 10, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Jun 22, 2008 description: "===== \n Description =====\n\nDescription of project.." language: VHDL license: GPL3 licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - yacinenet name: microprocessor status: Planning svn-updated: Mar 10, 2009 updated: Jun 23, 2011 wishbone-compliant: 0 - category: Processor created: Mar 20, 2002 description: "===== \n Description =====\n\n32 Bit RISC Processor, 5 Stage Pipeline. Developed for embedded control of devices. Optimized for the Xilinx SpartanII and Virtex line of FPGA's. Later optimizations will be made for Actel ProASIC(+) FPGA's. Uses the Harvard architecture for memory. It contains one interupt vector with a cause register.\n\nThe 5 Stages:\n- Fetch\n- Decode/Register/Uncoditional Branch\n- Execute(ALU/Compare/etc.)\n- Memory/Conditional Branch\n- Write Back\n\nUnique Instructions:\n- Population Count(Ones,Zeros,Bit Changes)\n- Random Number Generator\n \n\n\n \n \n \n\n===== \n Status =====\n\nSVN Contains: AU, LU, Compare Unit, Register File, IF, EX, WB Stages\n\nThe top level file's really the only thing left. I'm expanding and optimizing many modules and I won't upload them until I am more satisfied with how they function. Also, I may add a few features. I am considering makeing an optional 16 bit ISA.\n\nCompleted:\n- AU (Arithmetic Unit) - Missing random number generator\n- LU (Logic Unit)\n- Compare Unit\n- Register File\n- Special Instruction Unit(Interupts, Cause Register,Load Low,High)\n- Instruction Fetch Stage\n- Execution Stage\n- Memory Access Stage\n- Write Back Stage\nAlmost Completed:\n- Decoder\n- Decode/Register Access Stage\nTODO:\n- Top Level File" language: Verilog license: unknown maintainers: - alikat name: microriscii status: Alpha svn-updated: May 6, 2009 updated: Apr 1, 2002 wishbone-compliant: 0 - category: Communication controller created: Nov 2, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - morpheous name: milstd1553bc status: Empty updated: Nov 7, 2012 wishbone-compliant: 0 - category: Crypto core created: Dec 5, 2005 description: "===== \n Mini AES =====\n\nAdvanced Encryption Standard (AES) implementation with small area/resources utilization.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Encryption and Decryption unit in single core.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Currently only AES 128 version.\n- Not small enough.\n- http://www.opencores.org/pstats.cgi/view/mini_aes (Project status)" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - arif_endro name: mini_aes status: Design done svn-updated: Jun 25, 2010 updated: Mar 19, 2010 wishbone-compliant: 0 - category: Communication controller created: Aug 6, 2010 description: "===== \n Description =====\n\nThis core is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\n\nMinimal 10/100 Ethernet MAC.\nOnly full duplex support for now.\nDMA support (Wishbone master)\nPackets are streamed to and from system memory to minimize costly on-chip storage.\nDirectly connects to standard MII PHYs.\nBit-banged MDIO\n\n \n\n\n \n \n \n\n===== \n More information =====\n\n\nCore documentation\nCSR bus specifications" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: minimac status: FPGA proven svn-updated: Aug 24, 2010 updated: Aug 7, 2010 wishbone-compliant: 1 - category: Processor created: Jun 3, 2004 description: "===== \n Main aspects =====\n\n- The miniMIPS is a 32 bits core and has a Von Neumann architecture.\n\n - The miniMIPS is 5-stage pipeline :\n - Instruction extraction\n - Instruction decoding\n - Execution\n - Memory access\n - Update registers\n\n- Only two instructions can access the memory. The others work on registers which are 32 bits large. The processor contains 32 registers.\n\n- Data hazards are resolved thanks to a bypass unit.\n\n- Branch hazards are resolved by predicting the address results.\n\n- Interruptions and exceptions are taken in account thanks to a system coprocessor.\n \n\n\n \n \n \n\n===== \n Assemblee =====\n\nAn assembly gasm is provided with the project to generate the binaries for the miniMIPS cores.\nThis program is developed by Samuel Hangou\xC3\xABt and Louis-Marie Mouton.\n \n\n\n \n \n \n\n===== \n Performance =====\n\nThe miniMIPS was integrated in an FPGA from Xilinx Xc2V1000-5fg456.\n\nThe processor speed is 50MHz. As at each cycle an instruction ends (except when there are stalls), that means 50 million instructions per second.\n\nThe processor is used as a free example in the XSmart-ICE product (a generic emulator for core) from the french society Raisonance based in Grenoble.\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe project miniMIPS is a processor core based on the MIPS I architecture. \n\nThe project is born during a school project at the ENSERG (Ecole Nationale Sup\xC3\xA9rieure d'Electronique et de Radio\xC3\xA9lectricit\xC3\xA9 de Grenoble), France.\n\nThe main contributors are Samuel Hangou\xC3\xABt, S\xC3\xA9bastien Jan, Louis-Marie Mouton and Olivier Schneider." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - poppy - shangouet - louismarie name: minimips status: FPGA proven svn-updated: Jun 18, 2009 updated: Mar 24, 2006 wishbone-compliant: 0 - category: Processor created: Sep 25, 2001 description: "===== \n Description =====\n\nThis is a Mini-RISC CPU/Microcontroller that is compatible with the PIC 16C57 from Microchip. Additional information about the instruction set and capabilities can be found at: www.microchip.com.\n \n\n\n \n \n \n\n===== \n Legal notice =====\n\nPIC, Microchip, etc. are Trademarks of Microchip Technology Inc. I have no idea if implementing this core will or will not violate patents, copyrights or cause any other type of lawsuits. I provide this core AS IS, without any warranties. If you decide to build this core, you are responsible for any legal resolutions, such as patents and copyrights, and perhaps others .... This source files may be used and distributed without restriction provided that all copyright statement are not removed from the files and that any derivative work contains the original copyright notices and the associated disclaimer.\n\n THIS SOURCE FILES ARE PROVIDED \"AS IS\" AND WITHOUT ANY\n EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT\n LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND\n FITNESS FOR A PARTICULAR PURPOSE.\n\n\n \n\n\n \n \n \n\n===== \n Motivation =====\n\n- A PIC compatible Microcontroller that runs a lot faster \n- Synthesisable and technology independent design \n- Separate (External to the core) Program Memory \n- Options to extend the core \n \n\n\n \n \n \n\n===== \n Compatibility =====\n\nThis design should be fully software compatible to the Microchip Implementation of the PIC 16C57, except for the following extensions:\n\n- Port A is full 8 bits wide \n- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded) \n- Executions of instructions that modify the PC has became a lot more expensive due to the pipeline and execution of instructions on every cycle. Any instruction that writes to the PC (PC as destination (f), call, goto, retlw) now takes 4 cycles to execute (instead of 2 in the original implementation).\n- The 4 'skip' instructions, remain as in the original implementation: 1 cycle if not skipped, 2 cycles if skipped. \n- Sampling of IO ports might be off \n- Timer and watchdog might be off a few cycles \n \n\n\n \n \n \n\n===== \n Performance =====\n\n- About 80Mhz, in a Spartan IIe-50, 30% utilization\n- Single cycle instruction execution, except as noted above for PC modifications.\n- I estimate about 22K gates with the xilinx primitives, (excluding Register File and Program Memory). A Xilinx Vertex XCV100 can hold 4 of this cores and program memory, and still have some room left. \n \n\n\n \n \n \n\n===== \n Implementing the Core =====\n\nThe only file you should edit if you really want to implement this core, is the 'primitives.v' file. It contains all parts that can be optimized, depending on the technology used. It includes memories, and arithmetic modules. I added a primitives_xilinx,v file and xilinx_primitives.zip which contain primitives for xilinx.\n \n\n\n \n \n \n\n===== \n Status =====\n\nFirst version of the core is released. Included with the release is also a small test bench and several test programs written in assembly. MPLAB from Microchip, can be used to compile and develop additional code.\n\nThe core can be downloaded from OpenCores CVS (see Downloads)\n \n\n\n \n \n \n\n===== \n Development tools =====\n\nA very nice(and free) development environment with a software simulator is provided by Microchip on their web site. This environment works only on PCs. Various free and chimerical tools are available from third party, just Search the web !\n\nHere is a link to the Microchip Development environment (http://www.microchip.com/10/Tools/PICmicro/DevEnv/)\n \n\n\n \n \n \n\n===== \n To-Do =====\n\nThings that need to be done\n\n1.Write more test/compliance test vectors \n\n- Verify that all instructions after a goto/call/retlw/write to PCL are not executed \n- Verify ALU \n- Timer and Watchdog tests \n- Perhaps some other areas ? \n\n2.Extensions ? \n\n- guess this is on a \"as needed\" basis \n- Would be nice to extend the register file and have a few registers that are shared between two or more of this cores in a MP implementation ! \n\n \n\n\n \n \n \n\n===== \n Change log =====\n\n6/18/200 RU\n - Added this Change Log\n - Added \"Development Tools\" Section|\n - Removed speed claims from the \"Performance\" Section: Need to re-synthsise the core and resolve synthesis tool/backend tool issues.\n - added \"risc_core_top.v\", a top level with tri-state buffers and program memory, to make it look like a real PIC !\n - Updated the primitives_xilinx.v so it will work correctly with Synplify and Synopsys FPGA compiler\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\nTHIS SOURCE FILE IS PROVIDED \"AS IS\" AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT\nLIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND\nFITNESS FOR A PARTICULAR PURPOSE.\n" maintainers: - rudi name: minirisc status: Stable svn-updated: Mar 10, 2009 updated: Feb 6, 2012 wishbone-compliant: 0 - category: Communication controller created: Jan 20, 2002 description: "===== \n Description =====\n\nDesign in VHDL:\nThis UART is able to Transmit/Receive bytes in the configuration:\n1 start bit - no parity - 1 stop bit.\nIt can be commanded by a microcontroller, or by other IP core.\nIt is not suited to interface a modem as there is no control handshaking (CTS/RTS).\nIt does'nt contain FIFO for emit/receive.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\xE2\x80\xA2 WISHBONE interface in 8-bit data bus\n\xE2\x80\xA2 Two clock: one for wishbone interface, one for RS232 bitstream generation\n\xE2\x80\xA2 Baudrate divisor from 1 to 65536 (generic parameter set at integration time)\n \n\n\n \n \n \n\n===== \n Synthesis results =====\n\nXilinx:\n\xE2\x80\xA2 Spartan: XCS10-TQ144-4: 71 flip-flop\n\xE2\x80\xA2 Spartan-II: XC2S15-CS144-6: 153BELs@107MHz\n \n\n\n \n \n \n\n===== \n Status =====\n\nOperational" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - philippe name: miniuart2 status: Mature svn-updated: May 6, 2009 updated: Aug 26, 2010 wishbone-compliant: 1 - category: System on Chip created: Sep 18, 2009 description: "===== \n Description =====\n\nThe Minimal OpenRISC System on Chip is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation consists of a standard project comprehending the standard IP cores necessary for a SoC embedding the OpenRISC implementation OR1200.\n\n\n\n\n\nThis project idea is to offer a synthesizable SoC which can be uploaded to every FPGA and be compatible with every FPGA board without the requirement of changing its code. In order to deliver such a project, the project has been based on a standard memory implementation and the Advanced Debug System, which allows system debug and software upload with the same cables used for FPGA configuration.\n\n\n\n\n\nThe adaptation of the project to a target board is made in 2 steps maximum. First, the \xE2\x80\x9Cminsoc_defines.v\xE2\x80\x9D file has to be adjusted, generally one has to only uncomment his FPGA manufacturer and FPGA model definitions. After that, a constraint file for your specific pinout has to be created. Constraint files for standard boards can be found in the backend directory of the project.\n\n\n\n\n\nFurthermore, the project offers working testbench and firmwares for its SoC. The current testbench can be run out of the box using Icarus Verilog v. 9.1. The firmwares are nearly the same of those of orpsocv2. The differences are for now, that the known UART \"hello world\" example now runs with interrupts and a new Ethernet example has been added to it.\n\n\n\n\n\nTo complete, an on-chip memory instance is provided to embed the CPU's firmware. The size of this memory can be adapted defining its address width inside of the same minsoc_defines.v file, affecting simulation and synthesis equally. This enables the customization of the SoC to the available resources of the target FPGA, for general purposes, or to the memory amount required by the target firmware, for custom implementation, e.g. ASIC.\n\n\n\n\n\nAn overview about the complete SoC and its external connections is on Figure 1.\n\n\n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n System Features =====\n\n-or1200 OpenRISC implementation\n\n-Resizable onchip memory\n\n-System frequency selection\n\n-JTAG debug featuring a multitude of cables\n\n-Start-up option to automatically load your firmware on start-up from an external SPI memory\n\n-UART and Ethernet modules\n\n-FPGA generic and specific code (Xilinx & Altera) for memory, clock adaptation (PLLs and DCMs) and JTAG Tap\n\n-System configuration in a single definition file\n\n-Example firmwares using UART and Ethernet\n\n-Testbench included, for the simulation of exacly your configured system\n \n\n\n \n \n \n\n===== \n Status =====\n\nAll minsoc FPGA generic features have been simulated and proven to work. \n\nThe FPGA generic features have been tested on an FPGA implementation and are working. These comprehend the FPGA generic only modules, start-up, Ethernet, UART and or1200 OpenRISC; and the generic JTAG tap and the generic clock divider. Both, JTAG tap and clock divider, can optionally be FPGA specific. On the other hand, the generic memory cannot be implemented in an FPGA generic way, because the synthesizer does not allocate them to RAMs, consuming then all FPGA flip-flops. \n\nThe FPGA specific features, onchip memory, clock frequency adaptation and JTAG taps have to be tested for different FPGAs. Xilinx implementations differs in both instantiation and implementation for all modules. Altera differs perhaps in implementation, but the modules can be instantiated equally. A specific implementation of a clock frequency adaptation PLL for Altera has been recently added by Javier Almansa.\n\nTest of FPGA specific features requires feedback from users, for now we have positive results from the following configurations:\n-Xilinx, Spartan 3E (Spartan3E Starter Kit) (Thanks to Bakiri Mohammed)\n-Xilinx, Spartan 3A (Spartan3A 1800 DSP Kit)\n-Xilinx, Virtex 4 (ML405 board) (Thanks to Ravi Kumar)\n-Xilinx, Virtex 5 (ML505 board) (Thanks to Evangelos Logaras)\n-Altera, Cyclone II (Thanks to Nathan Yawn)\n-Altera, Cyclone II (DE2-70 board) (Thanks to Alex Parrado)\n-Altera, Cyclone III (Thanks to Davide Catani)\n-Altera, Cyclone IV (Bemicro SDK board) (Thanks to Jean-Christophe Ricard)\n-Altera, Stratix II (Thanks to Alex Parrado)\n\nFor now no configurations have been proven not to work. \n \n\n\n \n \n \n\n===== \n How To =====\n\nInformation regarding the usage of MinSoC can be found in our wiki: http://www.minsoc.com/\n\nThere, you will find guidance to retrieve and install the required tools, simulate and synthesize the design, and to run and debug the first firmware on your FPGA. \n\nIf you can improve the wiki, feel free do so. It is public. Update pages, create new ones and add links to them. This allow for quality as you find errors, correct the language or give hints to users doing the same thing as you. \n \n\n\n \n \n \n\n===== \n Contact =====\n\nIf you have problems implementing the design or information regarding new tested platforms, want to contribute with a ucf file or are interested in implementing something for the project, contact our discussion group.\n\nSend an email to: minsoc@googlegroups.com\n\nThis discussion group together with the wiki are the places for decision and planing of MinSoC's development. You can check latest maintainer's ideas and plans under: http://www.minsoc.com/pm:start" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rfajardo - nyawn - ramkumarj2000 - javieralso - firefalcon name: minsoc status: FPGA proven svn-updated: May 12, 2013 updated: Apr 20, 2013 wishbone-compliant: 1 - category: Processor created: Oct 14, 2012 description: "===== \n Description =====\n\nUPDATE 1-Jan-2014: This project has moved to GitHub. Please visit https://github.com/grantea/mips32r1 for the latest code. No further changes will be committed to this repository.\n\n\nA 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This processor implementation was designed and built by Grant Ayers as part of the eXtensible Utah Multicore (XUM) project at the University of Utah, 2011-2012. Feel free to send questions or feedback to grant DOT ayers AT stanford.edu.\n \n\n\n \n \n \n\n===== \n Details =====\n\n- Single-issue in-order 5-stage pipeline with full forwarding and hazard detection.\n- Harvard architecture with separate instruction and data ports which can be combined if desired.\n- All required MIPS32 instructions are implemented, including hardware multiplication and division, fused multiply/adds, atomic load linked / store conditional, and unaligned loads and stores.\n- Complete Coprocessor 0 allows ISA-compliant interrupts, exceptions, and user/kernel modes.\n- No MMU and no FPU, with toolchain support for software-based floating point.\n- Hardware divider is small, multicycle, and runs asynchronously from the pipeline allowing some masking of latency.\n- Memory interface is separate from the processor for flexibility with connecting various RAMs.\n- Hardware is Big-Endian by default and supports reverse-endian mode for User mode.\n- Parameterized addresses for exception/interrupt vectors and boundary address between user/kernel regions.\n- Extensive documentation in-source and elsewhere.\n- Vendor-independent code.\n- A clean, modular design written from scratch.\n\nThe project includes a standalone MIPS32 processor as well as a full System-on-Chip design targeted for the XUPV5-LX110T board. With minor changes (clock module, BRAM module, and pin constraints) the SoC can run on many hardware platforms.\n\nThe standalone processor utilizes approximately 1,800 slice registers (2%) and 4,000 LUTs (5%) on a Virtex 5 LX110T.\nThe SoC utilizes approximately 2,700 slice registers (3%) and 5,100 LUTs (7%) on a Virtex 5 LX110T.\n\n \n\n\n \n \n \n\n===== \n Future Plans =====\n\n1. Add hardware division. (DONE)\n \n\n\n \n \n \n\n===== \n Other Inclusions =====\n\nThe following MMIO hardware drivers are included as part of the SoC design:\n\n- Basic single-master I2C driver.\n- 16x2 LCD driver for Sitronix ST7066U, Samsung S6A0069X / KS0066U, Hitachi HD44780, SMOS SED1278, or other compatible hardware.\n- LED driver.\n- Piezo transducer driver.\n- Switch input filter.\n- 115200 baud 8-N-1 serial port using only Tx and Rx with configurable baud rate.\n- 592 KB BRAM and clock generation for XUPV5 board.\n\nThe following software is included:\n\n- XUM bootloader which loads programs from a PC to the FPGA. This is written in C# for Windows, however the boot protocol is simple and can be implemented in any operating system or not used at all.\n \n\n\n \n \n \n\n===== \n Software Toolchain =====\n\nThe software toolchain is based on Binutils, GCC, and Newlib. It can be built for almost any platform, including unix-like environments and Windows (Cygwin). Instructions are included with the project.\n\nThe current toolchain uses Binutils 2.21, GCC 4.7.1 (mpfr 3.0.1, mpc 0.9, gmp 5.0.5), and Newlib 1.20.0.\n\nThe toolchain currently supports Big- and Little-Endian code as well as software floating point. Newlib C library stubs are left unchanged." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ayersg name: mips32r1 status: Stable svn-updated: Jan 2, 2014 updated: Apr 12, 2014 wishbone-compliant: 0 - category: Processor created: Aug 24, 2007 description: "===== \n Description =====\n\nThis is a soft processor core written in verilog-2001 with five pipeline stages which supports almost MIPSI instructions. MIPS789 supports gcc-elf-mips tools provided by Steve Rhords, author of plasma.In fact, this core is designed based on this complier. I\xE2\x80\x99ve tested it by using a lot of C programs in a CYCLONE device EP1C6Q240 at 50MHZ frequence and it worked so well. By calculation, its CPI (cycle per instruction) is about 1.1 when run common programs. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Five stage \n - IF&ID: instructions fetch /decode.\n - RF: register fetch /generate next pc (branch included).\n - EXEC: execute instruction.\n - DMEM: read/write data from/to data memory or device.\n - WB: result write back to register bank.\n\n- supporting interrupt by using a special way.\n - dynamic IRQ address, which means you can redefine the IRQ address by point of C programs.\n - using \xE2\x80\x9CMFC0 $RX,$RX\xE2\x80\x9D to save the Saved PC to register $RX.\n - using \xE2\x80\x9CMTC0 $ZERO,$ZERO\xE2\x80\x9Dto return from an interrupt.\n\n- WELL TESTED \n - Tested running all instructions that are implemented generated by assembler.\n - Tested and running correctly at 50MHz in cyclone device EP1C6Q240 -8.\n - Tested running large blocks of compiled C code.\n\n- ATTIONS\n - Only support big endian.\n - DO NOT SUPPORT normal COP0 currently. \n - SWL, SWR, LWL and LWR are not implemented.\n\n\n \n\n\n \n \n \n\n===== \n Legal =====\n\nI have no idea if implementing this core will or will not violate \npatents, copyrights or cause any other type of lawsuits.\n\nI provide this core \"as is\", without any warranties. If you decide to \nbuild this core, you are responsible for any legal resolutions, such \nas patents and copyrights, and perhaps others ....\n\nTHIS SOURCE FILE(S) IS/ARE PROVIDED \"AS IS\" AND WITHOUT ANY \nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT \nLIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND \nFITNESS FOR A PARTICULAR PURPOSE.\n \n\n\n \n \n \n\n===== \n IMAGE: topview.GIF =====\n\nFILE: topview.GIF\nDESCRIPTION: structure of MIPS789\n \n\n\n \n \n \n\n===== \n IMAGE: pi_2200.GIF =====\n\nFILE: pi_2200.GIF\nDESCRIPTION: Calculating PI with 2200 digitals (about 5second @50MHZ)" language: Verilog license: custom licensetext: "This source file may be used and distributed freely without\nrestriction provided that this copyright statement is not\nremoved from the file and any derivative work contains the\noriginal copyright notice and the associated disclaimer.\n\nPlease let the author know if it is used\nfor commercial purpose.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - mcupro name: mips789 status: FPGA proven svn-updated: Nov 12, 2009 updated: Oct 2, 2014 wishbone-compliant: 0 - category: Processor created: Mar 3, 2012 description: "===== \n Description =====\n\nThis project was aimed at providing people a simple, runnable, and easy-to-enhance MIPS CPU main architecture, along with well commented Verilog RTL source code, complete simulation test benches & scripts, and detailed documentation. People can read the source code, make simulations to verify the result, and then make modifications to enhance it. I hope this project can help you learning the MIPS CPU architecture and enjoy constructing your own CPU core.\nThis CPU design is based on Mr. Hu Weiwu\xE2\x80\x99s book \xE2\x80\x9DComputer Achitecture\xE2\x80\x9D, Tsinghua University Press, 2011\n\n \n\n\n \n \n \n\n===== \n Technical brief =====\n\n1.\t16-bit data width\n2.\tclassic 5-stage static pipeline, 1 branch delay slot, theoretical CPI is 1.0\n3.\tpipeline is able to detect and prevent RAW hazards, no forwarding logic\n4.\t8 general purpose register (reg 0 is special, according to mips architecture)\n5.\tup to now supports 13 instructions, see ./doc/instruction_set.txt for details\n6.\tMaximum clk Frequency: 82.688MHz on Xilinx 3s1000fg320-5 device (XST).\n \n\n\n \n \n \n\n===== \n File system description =====\n\nDirectory tree:\nmips_16\t\n+-backend => Backend tool dir\n| +-Xilinx => Xilinx ISE work dir\n+-bench => Test benches & modelsim scripts for each module\n| +-mips_16_core_top => benches & scripts for top module\n| +-module_1 => benches & scripts for module_1\n| +-module_2 => benches & scripts for module_2\n| +-... => ...\n| +-module_n => benches & scripts for module_n\n+-doc => documentations\n+-rtl => RTL source code of this project\n+-sim => Modelsim work dir\n+-sw => Tool chains\n\nFile types:\n*.asm : => MIPS_16 assembly language source file\n*.prog: => MIPS machine language file,\ngenerated from .asm files,\nin ASCII format, for simulation only." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Doyya name: mips_16 status: Stable svn-updated: Mar 4, 2012 updated: Aug 18, 2013 wishbone-compliant: 0 - category: Processor created: Jun 11, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mkarimim name: mips_32bit-single_cycle status: Empty updated: Jun 11, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Jun 11, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mkarimim name: mips_32bit_single_cycle status: Empty updated: Jun 11, 2013 wishbone-compliant: 0 - category: Processor created: Nov 27, 2010 description: "===== \n Description =====\n\nThis project is based on MIPS789 opencores project.We used MIPS789 core and added the cache infrastracture and AMBA bus from LEON3.The final core executes MIPS I instructions.It is downloaded on a Spartan3 fpga(gr-xc3s-1500).In order to test it we used the Leon3 Testbench." language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dimamali - walker name: mips_enhanced status: Stable svn-updated: Apr 9, 2011 updated: Apr 10, 2011 wishbone-compliant: 0 - category: Processor created: Jan 22, 2013 description: "===== \n Description =====\n\nA fault tolerant for processor \nThe mips \xE2\x80\x93 fault tolerant is mips 32 bits processor with error detection ( Fault Tolerant ). The processor implementation was designed by Lazaridis Dimitris.\nMain aspects\nThe core is in 5 stages:\n- Instruction extraction\n- Instruction decoding\n- Execution\n- Memory access\n- Update registers\nIt supports almost all instructions of mips technology, R type, I type, Branch, Jump and multiply packet instructions.\nThe multiply result is stored until is needed regardless if others instructions follows.\nThere is an error detection circuits for fault tolerant. It is implementing in hardware 100% which provides error detection at reset start-up.\nThere is a separate memory for instructions and another for data read \xE2\x80\x93 write which can be changed.\nAt each stage one clock cycle is used. Both memories function in descending pulse and the remaining pulse is used for developing the necessary functions (e.g. pipeline), which makes the core faster and more flexible.\nAll I types instructions are part decoded in first stage and all R types also part decoded in Alu control reducing the complexity in main Control unit (FSM).\nAll instructions are tested for correct execution. A test benchs from separate circuit implementation is also included (to verify the program which exists in Instruction memory).\nThe mips - fault tolerant was integrated in an FPGA from Xilinx version 13.1 in Spartan 3 xc3s400-5tq144 target device but can be fit in another similar target device.\nThe processor is implemented all in VHDL. \nError detection\nWith continuous scaling in CMOS technology the number of transistors grows more and more in a single chip. Chip multiprocessors (CMPs) are an efficient way for using this very large number of transistors integrated in a chip. Several researches show that high density integration makes modern processors prone to the risk of transient or permanent fault. However, the increase of temperature and decrease of the voltage in the chip lead to a higher susceptibility to faults. As the feature size shrinks the probability of a single transistor to become faulty, it increases due to the low threshold voltages.\nIt is projected that the rate at which the transient errors occur will grow exponentially and will soon represent one of the most significant issues in the design of future generation high-performance microprocessors.\nThis work proposes a fault tolerant architecture that tolerates the high fault rates that are expected in future technologies. In this work the multiplication block circuit is tested. \nAnalyze\nIn this method a multiplication is executed and the result is stored following by a comparison. It is start with initial value of 00001111\xE2\x80\xA6. which this value executes a multiplication in multiplication circuit and the result is stored. It needs 64 machine cycles to complete this error detection. After the initial multiplication the numbers which are executed are subjected a shift one digit, following by a multiplication again and the result are stored in previous result. This is continuous for 64 machine cycle, where the final result is stored, including the previous results. In final stage of error detection the calculated result is compared with a correct stored result and if any error exists in multiplication array circuit this can be found. In this method the fault coverage is approximately 75% and 64 machine cycles are demanded. The error detection begins at start up before any execution. It has a high fault coverage and nearly fast execution due to hardware implementation, which will be more popular method for errors detection in future for the time saving (there is not time penalty), reliability, low cost and high presentence to fault coverage, low power consumption. \nA slide different circuit implementation but much more powerful: \nThe multiplier circuit device made with and/h/f/adders.\nC\\AB 00 01 11 10\n0\t0 1\t 0 1\n1\t1 1c 0 1c\nI treat both exits as one because the point is to detect errors, from the karnaugh map we have:\nA\xE2\x80\x99B + AB\xE2\x80\x99 + CB\xE2\x80\x99 If combine the first two we have CB\xE2\x80\x99.\nThere is the term +AB (from 111, 110) but I subtract it temporally to simplify the procedure.\nTo implement it we need to include only one 0 in test vectors.\nIf we will check a 4X4 bits multiplier with a shift in each clock as:\n1110, 1101, 1011, 0111 in y axes and the same in x axes, we will cover the 90% error detection in 8 machines cycles. I left one stage of variables out, for isolate detection to simplify the procedure, which is the value all -> 1s, which needs one machines cycle and cover the remaining 10% of error detection. The total procedure needs 10 machines cycles with an addition all -> 0s. The total coverage is 98-99%. In multiplier 32X32 bits it needs 66 machines cycles for total coverage. This method is fast enough and support total error detection with hardware implementation.\n\nAnother alternate method: This method is hardware implemented 100% also and it is very simple. In first machine cycle a 0000\xE2\x80\xA6 is executed in multiplication circuit and the result is compared with 0, if a 1 stack exists can be found here. (This covers the 50% error detection)\nIn second cycle a number 1111111111111111111111111111111 is multiplied with the 10101010101010101010101010101010 and comparison is done with a correct stored value at the end of this cycle. The third and final stage a multiplication is done with reversed numbers to cover as much as possible of the multiplication array circuit and if any error detection exist is also found here. (In a sample multiplier 4X4 bits error detection coverage is about 2%) This method has smaller fault coverage about 54% but it is very fast, it is only need 3 machines cycles to complete the fault tolerance.\n \nFurther research \nMost error detect methods for fault tolerance check the mips or a circuit at start up or at once or periodically to find any errors for fault coverage, but what if an error occurs during the tests? A fault data will process as correct. To work around with this, a non stop searching method is presented to test the mips continuously, it can be implement and find any error as it appears in born, further more if the fpga has enough space to relocate the damaged place it can be done in another undamaged. \nTo implement this error detect method, we can inject in fsm and detect the errors for fault tolerance. Knowing the next stage (instruction) through fsm, it is easy to start the test for \xE2\x80\x9Cmultiply\xE2\x80\x9D block circuits, which error detection circuit could test the multiply circuits as long as the next instruction it is not concern this circuits, if a multiply instruction is coming up we can stop the process and continue when it is free again, thus we can find if an error occurs in this part of cpu and cover the fault tolerance. The same process it is possible to test and other critical part of mips or central unit and find if an error exist. The advantage in this method is that the error detect circuit works continuously. This method does not require double cores, but only some additional parts (low cost) and which can work in conjunction with fsm without consume the microprocessor\xE2\x80\x99s working time but it can work simultaneously." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jimi39 name: mips_fault_tolerant status: FPGA proven svn-updated: May 14, 2013 updated: May 14, 2013 wishbone-compliant: 0 - category: Processor created: Oct 12, 2012 description: "===== \n Description =====\n\nThe mipsr2000 is mips 32 bits processor. The processor implementation was designed by Lazaridis Dimitris.\nMain aspects\nThe core is in 5 stages:\n\t- Instruction extraction \n\t- Instruction decoding \n\t- Execution \n\t- Memory access \n\t- Update registers\nIt supports almost all instructions of mips technology, R type, I type, Branch, Jump and multiply packet instructions.\nThe multiply result is stored until is needed regardless if others instructions follows.\nThere is a separate memory for instructions and another for data read \xE2\x80\x93 write which can be changed.\nEach stage use one clock cycle. Both memories function in descending pulse and the remaining pulse is used for developing the necessery functions (e.g. pipeline), which makes the core faster and more flexible.\nAll I types instructions are part decoded in first stage and all R types also part decoded in Alu control reducing the complexity in main Control unit (FSM). \nAll instructions are tested for correct execution. A test benchs from separate circuit implementation is also included (to verify the program which exists in Instruction memory).\nThe mipsr2000 was integrated in an FPGA from Xilinx version 13.1 in Spartan 3 xc3s400-5fg456 target device but can be fit in another similar target device.\nThe processor is implemented all in VHDL." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jimi39 name: mipsr2000 status: FPGA proven svn-updated: Jan 9, 2013 updated: Feb 6, 2013 wishbone-compliant: 0 - category: Video controller created: Oct 30, 2008 description: "===== \n Description =====\n\nA hardware based system to decode JPEG baseline compressed image data. The different stages of the decoding process are implemented in a pipelined design described in VHDL. Running on a Virtex-II Pro FPGA at 100 MHz operation frequency. The pipelined structure allows for the processing of multiple image blocks simultanously. Thus, the decoder is prepared to decode MotionJPEG movies. Functionality of the system is demonstrated with a proof-of-concept hardware MotionJPEG video player application.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- jpeg baseline decoding\n- mjpeg\n- display decoded data on a VGA monitor\n \n\n\n \n \n \n\n===== \n Status =====\n\n- closed" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - smanz name: mjpeg-decoder status: Beta svn-updated: Nov 16, 2009 updated: May 30, 2010 wishbone-compliant: 0 - category: Video controller created: Mar 7, 2009 description: "===== \n NEWS =====\n\n21 AUG 2011\nNew revision 70. contains new BUF_FIFO contributed Ahmet Tekyildiz which needs circa 9.5 line buffer but achieves performance very close to old design with ~16 lines (8 extra lines). So it heavily reduces on-chip RAM utilization without performance sacrifice.\nAlso this version contains nearest integer rounding in DCT-2D instead of truncation when bit growth/precision is reduced. Truncation caused 8x8 block artifacts easily visible in very high quality modes (>95% quantization tables). Rounding alleviates this problem.\n \n\n\n \n \n \n\n===== \n EV_JPEG_ENC JPEG Compressor =====\n\nWarning! WebSVN does not work correctly for project, use link below to download latest rev:\n\n\xE2\x80\xA2 DOWNLOAD LATEST REVISION 61\n\n\n\n\xE2\x80\xA2\tEV_JPEG_ENC core is intended to encode raw bitmap images into JPEG compliant coded bit stream. JPEG baseline encoding method is used.\n\n\n\xE2\x80\xA2\tLICENSE: GNU LGPL v3.0\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n\xE2\x80\xA2\tJPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1\n\xE2\x80\xA2\tStandard JFIF header v 1.01 automatic generation\n\xE2\x80\xA2\tColor images only (3 components, RGB 24 or 16 bit, YUV input)\n\xE2\x80\xA2\tTwo programmable Quantization tables\n\xE2\x80\xA2\tHardcoded Huffman tables (luminance and chrominance)\n\xE2\x80\xA2\t2.3 to 2.7 clock cycles per one input 24 bit pixel @ 50% Quality\n\xE2\x80\xA2\tOPB programming and data Host interface\n\xE2\x80\xA2\t4:2:2 subsampling\n\xE2\x80\xA2\tSource code target independent, synthesizable RTL VHDL code\n\xE2\x80\xA2\tDetailed documentation\n \n\n\n \n \n \n\n===== \n Throughput =====\n\nExample throughput\n\nMeasured from JPEG encoding start till encoding done:\n\n\xE2\x80\xA2\tInput image 640x480 24 bit RGB color. New sample loaded every cycle until FIFO full.\n\xE2\x80\xA2\tQuantization tables at 50% quality setting\n\xE2\x80\xA2\t7.3 ms processing time @ 100 MHz clock\n\xE2\x80\xA2\t1000/7.3=136 frames per second @ 100 MHz\n\xE2\x80\xA2\tInput file size = 921 kB. Output file size = 44 kB (depends on image)\n\nCompression stats (from JPEGSnoop software):\n\xE2\x80\xA2\tCompression Ratio: 21.31:1\n\xE2\x80\xA2\tBits per pixel: 1.13:1\n\n\n100 MHz is achievable under Stratix II S90 for example. Optimization set to performance.\n \n\n\n \n \n \n\n===== \n TODO =====\n\n\xE2\x80\xA2\treplace OPB interface used for programming with PLB or WishBone\n\n \n\n\n \n \n \n\n===== \n Architecture =====\n\n\n \n\n\n \n \n \n\n===== \n Low Level Design =====\n\nHere is a quite detailed low level design document for the Core:\nLow Level Design Document\n\n \n\n\n \n \n \n\n===== \n LICENSING =====\n\nEV_JPEG_ENC is software released under Lesser GPL license and can be used freely for commercial and noncommercial purposes under NO WARRANTY. \n\n\n \n\n\n \n \n \n\n===== \n AREA/PERFORMANCE =====\n\nDevice Utilization Summary for Stratix II S90 (mkjpeg revision 57)\n\n6135 ALUTs\n3095 registers\n3858 ALMs\n4 DSP9\n55 M4K\n1 MRAM\n \nPerformance: above 100 MHz\n\nBuild configured for maximum image width 640 pixels and highest performance and memory usage (settable in JPEG_PKG.VHD)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mikel262 - ClementACTRIS name: mkjpeg status: FPGA proven svn-updated: Oct 3, 2012 updated: Sep 25, 2014 wishbone-compliant: 0 - category: ECC core created: Aug 2, 2014 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Lalit_Prasad name: mlc_nand_bch_eccw status: Empty updated: Nov 11, 2014 wishbone-compliant: 0 - category: DSP core created: Feb 15, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - juliob name: mlp status: Empty updated: Feb 15, 2012 wishbone-compliant: 0 - category: Prototype board created: Jul 1, 2010 description: "===== \n Description =====\n\nMilkymist One features the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\n\n\nThe Milkymist One will be a packaged, ready to use interactive VJ (live video performance) station. It is currently in active development and not generally available yet, however, some prototyping boards are available to developers.\nFeatures:\n- XC6SLX45 Spartan-6 FPGA\n- 128MB 32-bit DDR400 SDRAM\n- 32MB parallel flash\n- VGA output, 24bpp, up to 140MHz pixel clock\n- Multi-standard video input (PAL/SECAM/NTSC)\n- AC'97 audio\n- 10/100 Ethernet\n- Memory card\n- Two connectors that accept USB peripherals\n- Two DMX512 ports\n- MIDI IN and MIDI OUT ports\n- RC5-compatible infrared receiver\n- RS232 debug port\n\nMore information: http://www.milkymist.org/" homepage: http://www.milkymist.org/ language: Other license: unknown maintainers: - lekernel name: mm1 status: Empty updated: Aug 5, 2010 wishbone-compliant: 0 - category: Other created: Aug 6, 2010 description: "===== \n Description =====\n\nThis core is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\n\n16-bit 48kHz stereo only\nFull duplex support\nDMA support (Wishbone master)\nCodec register access support.\nUltra small size.\n\n \n\n\n \n \n \n\n===== \n More information =====\n\n\nCore documentation\nCSR bus specifications" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: mmac97 status: FPGA proven svn-updated: Aug 24, 2010 updated: Aug 7, 2010 wishbone-compliant: 1 - category: Other created: Dec 27, 2004 description: "===== \n Description =====\n\nIP Core for FPGA Configuration Controller from MMC Card. Can configure an FPGA in serial mode from continous blocks stored on MMC Card. Smallest version of the IP Core only needs 21 PLD Macrocells.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- FPGA Configuration modes supported\n - Master Serial (Xilinx) > FPGA tested\n - Slave Serial\n- Small Size\n - Minimal Core is 20 CoolRunner PLD-Macrocells\n- Removable Media for Bitstream Storage\n - MMC Cards are supported (no SD-Cards!)\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Xilinx Master Serial mode support tested with real HW (XC9536XL as config controller configuring VP20)\n-" language: Verilog license: unknown maintainers: - openchip name: mmcfpgaconfig status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 9, 2005 wishbone-compliant: 0 - category: System on Chip created: Feb 1, 2013 description: "===== \n Description =====\n\nISO/IEC14443 A is an important to the finance identification smartcard and NFC ASIC. And the modified Miller decoder is the key module for the wireless / dual-interface smartcard ASIC implementation. There are four data speed for ISO14443 A (2005 version), ie:\n* fc/128, or 106kbps, the default downlink data speed;\n* fc/64 (212kbps), fc/32 (424kbps) and fc/16 (847kbps), high speed for data exchange between PCD and PICC;\nThe mmiller_decod106t847kbps project gave a mature design of the mentioned decoder. Key features include;\n* low power consumption, 17uA@1.8VDC (UMC 0.18um CMOS, can be further reduced per request)\n* 50% duty of ETU clock output\n* better PAUSE duration, typ. +/-25%@106kbps\n* non-return zero decoder output with 1/8 ETU clock period shift from PAUSE signal\n* FDT0 and FTD1 available\nFPGA codes including PCD stimulus are available. Die samples are also available with 0.18um CMOS (UMC).\nDesign waves (bmp format, can be displayed by web browser with \"open with Firefox or IE, etc\", die and die test images also are available in the download section.\n\nluxiaodong@ime.ac.cn\nBeijing\n2013/2/2" language: Verilog license: unknown maintainers: - luxiaodong name: mmiller_decod106t847kbps status: Empty updated: Feb 28, 2013 wishbone-compliant: 0 - category: Processor created: Oct 5, 2013 description: "===== \n Description =====\n\nmmu180 is a MMU (memory mananagement unit) designed per original specifications of Zilog's Z180 family of processors (including Hitachi HD64180), which can be used to enhance any Z80-compatible core or physical processor to address up to 1 MiB of memory, per the original MMU specification. It allows most software written for Z180 devices to run on either a Z80-compatible core with mmu180, or on an actual Z80 or eZ80-family processor interfaced to mmu180 (e.g. in CPLD).\n \n\n\n \n \n \n\n===== \n Status =====\n\nAt present, has been simulated with Icarus Verilog and also from within Xilinx ISE WebPACK, and was successfully fitted into a Xilinx XC95144XL CPLD.\n\nActual validation of the MMU180 design is slated to proceed on a Zilog eZ80L92-based prototype. However, the challenge remains to obtain known working source code which can both reliably detect the presence of a Z180 MMU, and then run a comprehensive memory test suite to validate that the MMU functions properly \"in situ\". Beyond this, the design could be further and fully validated with confidence by running an operating system such as a version of CP/M Plus or Z-System which utilizes a Z180-compatible BIOS." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - beattidp name: mmu180 status: Alpha svn-updated: Oct 5, 2013 updated: Oct 5, 2013 wishbone-compliant: 0 - category: Communication controller created: Aug 6, 2010 description: "===== \n Description =====\n\nThis core is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\n\nMinimal UART core\nNo hardware FIFO\nNo modem control signals (just TX and RX)\nFully synchronous design\nConfigurable baud rate\nMeant to interface with Milkymist CSR bus and an edge sensitive interrupt controller (like that of LatticeMico32)\n\n \n\n\n \n \n \n\n===== \n More information =====\n\n\nCore documentation\nCSR bus specifications" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: mmuart status: FPGA proven svn-updated: Aug 24, 2010 updated: Aug 7, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Oct 9, 2010 description: "===== \n Description =====\n\nA quick & simple mod 3 calculator(only just combinational logic). the input 8-bit data is divided by 3. and the output is only 0, 1, or 2.\nI use XilinxISE10.1 Synthesis the file, the speed can reach 113MHz.\nIf anyone want make it more faster, you can insert some registers and make it pipeline." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - yanzixuan name: mod3_calc status: Alpha svn-updated: Oct 11, 2010 updated: Oct 11, 2010 wishbone-compliant: 0 - category: Crypto core created: Dec 23, 2014 description: "===== \n Description =====\n\nModular multiplication and modular exponentiation play an important role in the most\nof existing cryptographic systems. In fact these are time and hardware consuming\noperations. \nUp to now there were proposed modular multiplication and modular exponentiation \nimplementations. One of them, Montgomery method, is very efficient especially if\nmodulus is coprime integer with the word length in which it is operated, what is\nalways true in binary systems\nIn this project Montgomery multiplier and Montgomery exponentiation blocks was \ndeveloped. They were prepared for Spartan 3ES500 FPGA in Spartan 3E Starter Board \ndeveloped by DIGILENT, but can be easily suited in another cores. In its basic \nthey were prepared for 64 bit and 512 bit word length (due to the FPGA capacity), \nand the way of the cores expanding was presented. \n\n\n\n\n\n\nTask done:\n\n Uploaded working Montgomery multiplier\n Uploaded working Montgomery exponentiator (with one variable input)\n\nTODO:\n\n Upload working example for multiplying\n Upload working example for exponentiation\n Write documentation\n\n\n\n\n\n\nIf You have any questions write me an email gajos@opencores.org." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gajos name: mod_mult_exp status: Alpha svn-updated: Feb 1, 2015 updated: Feb 1, 2015 wishbone-compliant: 0 - category: Crypto core created: Oct 16, 2012 description: "===== \n Project information =====\n\nThe Modular Simultaneous Exponentiation core is a flexible hardware design to support modular simultaneous exponentiations in embedded systems. It is able to compute a double exponentiation as given by\n\ng0e0\xE2\x8B\x85 g1e1 mod m\n\nWhere g0, g1 and m are n-bit numbers and the exponents e0 and e1 are t-bit numbers. This operation is commonly used in anonymous credential and authentication cryptosystems like DSA, Idemix, etc.. For this reason the core is designed with the use of large base operands in mind (n=512, 1024, 1536 bit and more..). The hardware is optimized for these simultaneous exponentiations, but also supports single base exponentiations and single Montgomery multiplications. Flexibility is offered to the user by providing the possibility to split the multiplier pipeline into 2 smaller parts, so that in total 3 different base operand lengths can be supported. The length of the exponents can be chosen freely by the controlling software. \n\nThe goal of this project is to develop a general core that works on different systems (Xilinx, Altera, ...) and supports various bus interfaces like AXI, PLB and wishbone.\n\nThe driver source can be found at: https://code.google.com/p/libmme/\n\n \n\n\n \n \n \n\n===== \n Architecture =====\n\nThe architecture for the full IP core is shown in the figure below. It consists of 2 major parts, the actual\nexponentiation core (mod_sim_exp_core entity) and a bus interface wrapped around it.\n \n\n\nThe mod_sim_exp_core entity is the top level of the modular simultaneous exponentiation\ncore. It is made up by 4 main blocks:\n\na pipelined Montgomery multiplier as the main processing unit\nRAM to store the operands and the modulus\na FIFO to store the exponents\na control unit which controls the multiplier for the exponentiation and multiplication operations\n\nFor further information about the architecture and internal workings, see the documentation on SVN.\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe design is working on both PLB and AXI with a generic operand RAM.\nCurrently the possibility to run the multiplier on a higher clock than the bus clock is being implemented." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - JonasDC - GEOFFREY_OTTOY name: mod_sim_exp status: FPGA proven svn-updated: Aug 21, 2013 updated: Jul 6, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Feb 24, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - guanucoluis name: modbus status: Beta svn-updated: May 9, 2011 updated: Feb 24, 2011 wishbone-compliant: 0 - category: Communication controller created: Aug 1, 2011 description: "===== \n Description =====\n\nThis controller is targetting fpga based applications were a microcontroller is not needed or wanted.\nBy design everything will be based on state machines.\nNo consideration will be done on power efficiency at the initial stage.\nCurrently on the drawing board for implementation.\nFunctions available are to be defined by use of generics as most of the people only use a narrow subset of all functions." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mana name: modbuscontroller status: Empty updated: Aug 3, 2011 wishbone-compliant: 0 - category: Other created: Nov 5, 2008 description: "===== \n [EN] Description =====\n\nThe aim of the project is to develop oscilloscope functions (conversion control, trigger, FFT, ...) in several cores and implement a usefull oscilloscope in a development board. The results are shown in a computer with a simple software.\nThe software will be developed using LGPL tools and distributed under such license, like the cores.\nThe beginig of this project is part of a universitary work in National University of San Luis, Argentina. For now, it is only a unipersonal project, but in some months it will have more maintainers.\n\n\n \n\n\n \n \n \n\n===== \n [EN] Features =====\n\n- PC interconnection\n\xC2\xB7 EPP\n- Configurable acquisition\n- Multiple inputs\n- Several trigger options\n- Software\n\xC2\xB7 GUI for windows and linux\n\xC2\xB7 Qt library\n\n\n\n \n\n\n \n \n \n\n===== \n [EN] Status =====\n\nLogic (alfa) and software (alfa) available.\n\nDone:\n- EPP-Wishbone bridge development.\n- Acquisition development.\n- Control development.\n- Software development.\n\nTo Do:\n- Test and improvement.\n- Full documentation still in progress. \n- Looking for new maintainers.\n\n \n\n\n \n \n \n\n===== \n [ES] Descripci\xC3\xB3n =====\n\nLa primera parte de este proyecto forma parte de un trabajo universitario en la Universidad Nacional de San Luis de Argentina. Por esta raz\xC3\xB3n, por ahora, solo se mantendr\xC3\xA1 en forma unipersonal. \nEl objetivo del proyecto es desarrollar funciones de osciloscopios (control de conversi\xC3\xB3n, trigger, FFT, ...) en varios m\xC3\xB3dulos e implementar un osciloscopio funcional en una placa de desarrollo. Los resultados se mostrar\xC3\xA1n en un programa sencillo de computadora.\nEl programa y los IP Cores ser\xC3\xA1n desarrollados bajo licencia LGPL.\n \n\n\n \n \n \n\n===== \n [ES] Caracter\xC3\xADsticas =====\n\n- Conexi\xC3\xB3n con PC\n\xC2\xB7 EPP\n- Adquisici\xC3\xB3n configurable\n- Entradas m\xC3\xBAltiples\n- Varias opciones de disparo\n- Software\n\xC2\xB7 Interfaz gr\xC3\xA1fica para windows y linux GPL\n\xC2\xB7 Qt\n(M\xC3\xA1s caracter\xC3\xADsticas pronto...)\n \n\n\n \n \n \n\n===== \n [ES] Estado =====\n\n- Desarrollo de m\xC3\xB3dulo EPP\n- Desarrollo del m\xC3\xB3odulo de adquisici\xC3\xB3n\n- Desarrollo del m\xC3\xB3dulo de control\n- Desarrollo del software\n- Testeos y mejoras...\n \n\n\n \n \n \n\n===== \n IMAGE: thumb_diagrama.jpg =====\n\nFILE: thumb_diagrama.jpg\nDESCRIPTION: General diagram of full project." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - budinero - maxpelaez - emanuelt name: modular_oscilloscope status: FPGA proven svn-updated: Nov 18, 2009 updated: Oct 15, 2011 wishbone-compliant: 1 - category: Communication controller created: Dec 15, 2005 description: "===== \n Description =====\n\nDescription of project..\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\n-Planning" language: Verilog license: unknown maintainers: - aanjhan name: most status: Planning svn-updated: Mar 10, 2009 updated: Dec 25, 2005 wishbone-compliant: 0 - category: Communication controller created: Jul 2, 2004 description: "===== \n Description =====\n\nWith the M2G protocol a high performance, very scalable and easy to implement multi media transport system for in car use shall be defined. Inspired by the MOST protocol (Media Oriented Systems Transport) (http://www.mostcooperation.com) but with many innovative improvements it shall be proved that with already existing technologies a far higher bandwidth for in car communication is possible. \n\nAny OEM (car manufacturer) and Tier1 are welcome to participate in this project and to support my work. If you find mistakes in my documentation inform me, please.\n \n\n\n \n \n \n\n===== \n Goals =====\n\nMOST currently specifies three different speed grades: 25, 50 and 150 Mbps (INIC25..INIC150 chips). By adoption of existing high speed data transmission technologies like PCIe, SATAII, USB3 and RapidIO it is expected to boost this bandwidth beyond 2 Gbps independent whether fiber optics or copper transmission lines are used.\n \nAdditionally the following demands must be kept in mind:\n* open protocol spec\n* scalable from 150 Mbps up to above 3 Gbps\n* support for 44.1, 48 or 96kHz frame rate\n* tunnelling of other bus systems like Ethernet or DTCP\n* independent from transmission media (optical or copper; DC free)\n* reuse of existing M messaging software\n* CDR (clock data recovery), source synchronous or oversampling possible\n* for FPGA and ASIC\n* dynamic bandwidth usage\n* save and deterministic arbitration mechanisms\n* protecting the ECU controller from high bandwidths streams and high event rates\n* EMI reduction (e.g. data scrambling and error detection/recovery)\n\n \n\n\n \n \n \n\n===== \n The steps =====\n\nThe following steps will be required:\n\n 1. Requirements analysis, analysis of available technologies [in progress; 85%]\n 2. Protocol specification [todo]\n 3. Proof of some physical principles [todo]\n 4. Simulation of node behavior [todo]\n 5. Protocol review [todo]\n 6. IP core specification [todo]\n 7. Simulation and real life test specification [todo]\n 8. Programming and simulation [todo]\n 9. Synthesis for FPGA [todo]\n10. Real life test and validation [todo]\n11. Bug fixing [todo]\n12. Documentation [todo]\n13. Promotion [todo]" language: VHDL license: custom licensetext: "All files and information provided by and around the M2G project are copyright protected to\n\nPeter Green.\n\nThey can be used for private or educational purposes with unmodified file headers and by mentioning\nme as the inventor and devleloper of M2G in your project documentation or web site if existing.\n\nCommercial users are required get in contact with me for definition of the conditions for IP reuse.\n" maintainers: - sinx name: most_core status: Planning svn-updated: Mar 11, 2009 updated: Mar 28, 2010 wishbone-compliant: 1 - category: Arithmetic core created: Dec 10, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - FMM name: motion_control_library status: Empty updated: Dec 10, 2011 wishbone-compliant: 0 - category: Video controller created: Aug 27, 2009 description: "===== \n Description =====\n\nHigh-definition programmable and configurable motion estimation processor for H.264, VC-1 and AVS video codecs. \n \n\n\n \n \n \n\n===== \n Summary =====\n\nThe LiquidMotion LMx1 processor is a reconfigurable ASIP (Application Specific Instruction Set Processor) designed to execute user-defined block-matching motion estimation algorithms optimized for hybrid video codecs such as MPEG-2, MPEG-4, H.264 AVC and Microsoft VC-1. The core offers scalable performance dependent on the features of the chosen algorithm and the number and type of execution units implemented. The ability to program the search algorithm to be used, and to reconfigure the underlying hardware that it will execute on, combines to give an extremely flexible motion estimation processing platform. \nA base configuration consisting of a single 64-bit integer pipeline, capable of processing 1080p HD video at 30 frames per second using a hexagonal motion estimation search followed by a square refine (as used in the opens-source h.264 encoder x264) with 1 reference frame and 16x16 block size can be implemented in 2,300 FPGA logic cells. In contrast, a complex configuration including support for motion vector candidates, sub-blocks, motion vector costing using Lagrangian optimization, four integer-pel execution units and one fractional-pel execution unit plus interpolation will need around 14,000 logic cells. At least one integer-pel execution unit must always be present to generate a valid processor configuration but the others units are optional, and are configured at synthesis time.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n\xE2\x80\xA2\tIntuitive and easy programming using a c-like syntax of user-defined block matching motion estimation algorithms.\n\xE2\x80\xA2\tHighly configurable architecture enables the designer to optimize the hardware for the selected algorithm.\n\xE2\x80\xA2\tBinary compatibility so that once an algorithm has been compiled it can be executed by any hardware configuration.\n\xE2\x80\xA2\tSupport of advance features such as rate distortion optimization using Lagrangian techniques, sub-partitions and fractional pel searches\naccording to the codec standard. \n\xE2\x80\xA2\tEfficient evaluation of multiple user-defined motion vector candidates transparently to the rest of the algorithm. \n\xE2\x80\xA2\tToolset available to enable the efficient exploration of the large design space and the generation of the RTL configuration file for the hardware processor library.\n\n \n\n\n \n \n \n\n===== \n Applications =====\n\n\xE2\x80\xA2\tVideo coding (H.264, MPEG-4, MPEG-2, VC-1, AVS)\n\xE2\x80\xA2\tVideo enhancement applications such as frame rate conversion, de-interlacing, super-resolution and video \n stabilization.\n\n \n\n\n \n \n \n\n===== \n Tools =====\n\nA toolset has been developed that enables the algorithm designer access to the hardware features without any knowledge of the processor microarchitecture. The toolset IDE is a fully integrated environment composed of a compiler, assembler, cycle accurate model and RTL export. The Cycle Accurate Model includes a full implementation of the x264 encoder (open-source h.264) so the designer can quickly evaluate the effects of different motion estimation algorithms in terms of PSNR and bit rate. The algorithm designer can create a new algorithm for the required application using typical C constructs such as for, while loops and if-else constructs. The compiler automatically recognises the search points that correspond to fractional-pel searches and generates the correct instructions.\nParallelism is extracted by the compiler by coding search patterns composed of a variable number of search points in a single instruction. The hardware analyses the instruction and distributes the load to the available execution units. Using the cycle accurate model the designer can quickly explore the performance of many configurations in terms of frame per second throughput, compressed video bit-rate and PSNR, hardware complexity and power/energy consumption.\nThe impact of changes in the original search algorithm can be evaluated before exporting the selected configuration hardware file and program binary. The final implementation can then be generated by processing the configuration file and the rest of the RTL processor description with standard tools such as Synplicity and/or Xilinx ISE. \n\n \n\n\n \n \n \n\n===== \n Deliverables =====\n\nToolset (compiler, cycle accurate model and analysis tools) available at http://seis.bris.ac.uk/~eejlny/binaries/lmcompiler.zip VHDL configurable processor description, VHDL testbench, FPGA prototype implementation using the PCI bus also available together with the original design team. The cycle accurate simulator supports all the features. The open-source RTL version is free for academic and research purposes and currently supports a single integer pipeline with 16x16 macroblocks. See it working at http://www.youtube.com/watch?v=TkRnm8qvdDA . The commercial version RTL supports all the features" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - eejlny name: motion_estimation_processor status: Stable svn-updated: Oct 11, 2009 updated: Jan 6, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Aug 27, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Xinthose name: mouse_led status: Empty updated: Aug 27, 2012 wishbone-compliant: 0 - category: System on Chip created: Aug 28, 2006 description: "===== \n Description =====\n\nSoft Multiprocessor on FPGA is becoming more attractive as the design cost and NRE soaring up in deep-submicron age, especially for high performance computing applications. However, it becomes time consuming and error prone to design multiprocessor as the number of processors grows quickly. To make it easier, I am going to design a tool (BlazeCluster) to generate multiprocessor architecture on FPGA consisting of Xilinx microblaze, PowerPC and open source processor cores from a simple, top-level script. \n\nThe tool is written in Perl. On most of Linux installations, the Perl interpreter is already there. For Windows XP you can install activePerl. The generated EDK project consists of XMP, MHS, MSS and UCF file which can be synthesized by Xilinx EDK7.1 and ISE7.1. The simulator is ModelSim 6.1 starter version. \n\nIt can also be used as a fast prototype tool for high performance computing (HPC) applications on FPGA.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- flexible Soft Multiprocessor on FPGA\n- various interconnections, including DPRAM, FIFO, bus, DMA\n- on-chip communication monitoring and profiling\n- real application (for example, JPEG Codec, Mandelbrot set) verified\n\n \n\n\n \n \n \n\n===== \n Documents =====\n\nA brief tutorial and case study is available at download page, http://opencores.org/project,mpdma,SoftwareMultiprocessoronFPGA20070608.pdf and my master paper http://opencores.org/cvsweb.cgi/~checkout~/mb-jpeg/doc/Master%20Paper.pdf?rev=1.1;content-type=application%2Fpdf\n\n\n \n\n\n \n \n \n\n===== \n Roadmap =====\n\n1. Multiprocessor Testbench\n1) single processor testbench *\n2) four-processor testbench (not-optimized) *\n\n2. Automatic multiprocessor template generator (BlazeCluster)\n1) simple generator for Microblaze only *\n2) support PowerPC *\n3) add area estimation *\n4) generator for other boards\n5) generate software libraries for communication\n\n3. Additional component\n1) Performance counter for Microblaze *\n2) DMA controller\n3) message interface\n\n4. Verification\n1) JPEG encoder*\n2) Mandelbroth set on FPGA*\n\n\n* DONE\n \n\n\n \n \n \n\n===== \n Milestone =====\n\n1. 2006/10/23 STEP1-2 Design a testbench to do JPEG encoder on four microblaze processors. Four processors are communicated to each other via FSL links. The design is not optimized thus there is not much performance improvement.\n\n2. 2007/05/05 STEP2-1 BlazeCluster v0.1. It can generate microblaze multiprocessor architecture on Virtex2vp30 FPGA on XUPV2P board from a single script. \n\nUsage: just run jena.pl. It then generate MHS, MSS, UCF file from system.js in the same directory. The script is designed similar to human language so you can easily understand it from several examples attached.\n\n3. 2007/06/08 STEP2-2 BlazeCluster v0.14. It supports PowerPC now. Meanwhile most of Perl code is rewritten to migrate to object-oriented model.\n\n4. 2007/07/14 STEP2-3 BlazeCluster v0.15. Support area estimation. It's helpful to design large system because you can know if your design fits the chip before time-consuming implementation. The result is in a log file. On the other hand, the LUT packing is not taken into consideration so the estimation of slice can be 10%-25% larger. The BRAM and Multiplier estimation is quite accurate.\n\n5. 2007/09/06 STEP3-1 BlazeCluster v0.17 Add performance counter for Microblaze to facilitate profiling on multiprocessor. An example of usage can be found in Mandelbrot set on FPGA testbench. The accuracy can be up to two cycles for every timer operation. More on http://opencores.org/project,performance_counter,overview \n\n6. 2007/09/06 STEP4-2 Mandelbrot set on soft multiprocessor on FPGA. It consists of one powerPC and eight microblaze processors with FPU running on XUPV2P. The profiling result shows that the load is fairly distributed on eight microblaze processors. The overall performance result is not so impressive, however. It's 4 times slower than a 2.0GHz PC. Any feedback to improve performance is welcome.\n\nNote you need copy Xilinx plb-vga-controller pcores and drivers into project directory in order to implement it. It can be extracted from http://www.digilentinc.com/Data/Products/XUPV2P/slideshow_256mb.zip" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - quickwayne name: mpdma status: Beta svn-updated: Mar 10, 2009 updated: Mar 12, 2008 wishbone-compliant: 0 - category: Arithmetic core created: Feb 28, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dinesha name: mpsc status: Empty updated: Dec 29, 2014 wishbone-compliant: 0 - category: Processor created: Mar 11, 2012 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ultra_embedded name: mpx status: Stable svn-updated: Sep 22, 2013 updated: Sep 22, 2013 wishbone-compliant: 0 - category: Processor created: Apr 24, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - petersz name: msp430_vhdl status: Empty updated: Apr 24, 2014 wishbone-compliant: 0 - category: Communication controller created: Mar 7, 2009 description: "===== \n Description =====\n\nThis is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD.\n\nThe purpose of this core is only to implement a very basic UART, without handshaking or FIFO's.\n\nIt was developed to be syntezizable on a large number of syntesis tools, so it can be adapted to your device easily.\n\nOn the first implementation was used a Xilinx Spartan 3E, with 64 occupied slices.\n\nPlease read the documentation, it have useful implementation examples.\n\nFor the testing was used the Modelsim simulator and a Enterpoint Drigmorn board, connected with some hardware, as described on the documentation.\n\nIf this core was useful I will be very pleased if you send me some information of your project.\n\nFor bugs send me an email, as soon as possible the corrections will be done. \n \n\n\n \n \n \n\n===== \n Features =====\n\nCan work on a small CPLD.\n Works with CPU's using interruptions.\n Can be even smaller changing constants and generics\n \n \n\n\n \n \n \n\n===== \n Status =====\n\n- Post rout tested on modelsim simulator \n- Tested on xilinx ISE simulator\n- Implemented on seven segment display\n- Implemented on KS0070B display, see documentation for details" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: muart status: Planning svn-updated: Mar 10, 2009 updated: May 7, 2011 wishbone-compliant: 0 - category: Communication controller created: Jul 18, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - kaarthika name: multichanneluart status: Empty updated: Jul 18, 2011 wishbone-compliant: 0 - category: Library created: Jun 10, 2009 description: '' language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - activedaily name: mvp_starter_kit status: FPGA proven svn-updated: Jun 10, 2009 updated: Jun 10, 2009 wishbone-compliant: 0 - category: Communication controller created: Dec 29, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Alex_via name: my_first_ethernet status: Empty updated: Dec 29, 2010 wishbone-compliant: 0 - category: Processor created: Nov 16, 2010 description: "===== \n Description =====\n\nmyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in myHDL ( http://www.myhdl.org ). It started as a translation of MB-Lite from VHDL to myHDL, along with a simple emulator. Its minimal configuration was tested on the Spartan-3E Starter Kit.\n\nTodos:\n 1. Wishbone compliant\n 2. Interrupt Controller\n 3. Porting U-Boot" language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rockee name: myblaze status: Mature svn-updated: Nov 22, 2010 updated: Nov 21, 2010 wishbone-compliant: 0 - category: Processor created: Oct 30, 2012 description: "===== \n Description =====\n\nA 32-bit FORTH processor conforming to the DPANS'94. This processor was developed as diploma thesis to obtain the academic degree Diplomingenieur (Master of Computer Science) at Johannes Kepler University in Linz, Austria.\n\nDetails\n\n- Pipelined (6-stage) instruction execution.\n- 2 stacks instead of register array.\n- memory common to data and instructions.\n- optional 64-bit multiplier and divider.\n- optional multicore possible\n- ANSI 754 floating point arithmetic.\n- Hardware is Little-Endian.\n- an Interruptcontroller.\n- an UART.\n- board specific DDR2 memory controller\n- a ROM containig the BIOS, sources included\n- Vendor-independent code. \n- A clean, modular design.\n\nThe projects are realized on Xilinx Spartan 3A Starter board, but can be moved to other Xilinx boards.\n\nThe following software is included:\nA Java-client for communication between board and user. The client includes a FORTH-Assembler and a Java compiler. The sources are included." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gerhardhohner name: myforthprocessor status: FPGA proven svn-updated: Nov 24, 2012 updated: Oct 31, 2012 wishbone-compliant: 0 - category: Library created: Feb 9, 2015 description: "===== \n Description =====\n\nMyGPU is a library of large-scale components like FPU units, a processor and auxillary units which can be used to build SoCs, processors, etc.\nWe do not only write verilog code, but also design layouts of our units, and develop tools to scale the layouts to appropriate tech process." language: Verilog license: unknown maintainers: - ckotinko name: mygpu status: Empty svn-updated: Feb 12, 2015 updated: Feb 12, 2015 wishbone-compliant: 0 - category: Processor created: Jun 2, 2011 description: "===== \n Description =====\n\nName: myRISC1\nSpecification:\n1.\t8-bit program counter\n2.\t256x8 instruction memory\n3.\t256x8 data memory\n4.\t8-bit instruction register\n5.\t4x8 register file\n6.\t8-bit ALU\n7.\t8-bit data bus\n8.\t8-bit address bus\n9.\t1-bit status register\n10.\t16 8-bit instructions\n10.1.\tOne miscellaneous type instruction (NOP)\n10.2.\tEight register type instructions (ADD,SUB,OR,AND,XOR,MOV,LD,ST)\n10.3.\tFour immediate type instructions (ADDI,SUBI,RLI,RHI)\n10.4.\tThree jump type instructions (BZ,BNZ,BRA) \xE2\x80\x93 range of jump is from -8 to +7" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - muzabyte name: myrisc1 status: Empty updated: Jun 2, 2011 wishbone-compliant: 0 - category: Memory core created: Oct 26, 2012 description: "===== \n Overview =====\n\nI implemented 2Q cache strategy from paper \"2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm\" written by Theodore Johnson and Dennis Shasha. It is written in VHDL and supports my FORTH-processor, which runs on a Spartan 3A DSP board from Xilinx. I think it can be adapted for other processors easily.\n\nparameters, user defineable:\n- blocksizeld ld of size of tagram\n- ldways ld of number of tagrams (n-way associative)\n- ldcachedwords ld of number of 32-bit words in one cacheline\n\ndefineable too:\n- ldram ld of depth of cacheram\n- ldqueuelength ld of depth of fifo (2Q strategy)\n\nYOU have to redefine subtype RAMrange in global.vhd:\nAs example, Your RAM is 128 MB then\n subtype RAMrange is natural range 26 downto 0;" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gerhardhohner name: mytwoqcache status: FPGA proven svn-updated: Nov 26, 2012 updated: Nov 26, 2012 wishbone-compliant: 0 - category: Processor created: Jun 1, 2012 description: "===== \n Description =====\n\nNatalius is a compact, capable and fully embedded 8 bit RISC processor core described 100% in Verilog. It occupies about 268 Slices, 124 FFs, 503 LUTs (4 input) in Xilinx Spartan3E1600 (around 1.67% slices). Natalius offers an assembler that can run on any python console.\n\nThe instruction memory is implemented in two Xilinx BlockRAM Memories, it stores 2048 instructions, each instruction has a width of 16 bits (2048x16). Each instruction takes 3 clock cycles to be executed.\n\n \n\n\n \n \n \n\n===== \n Documentation =====\n\nClick here to read the documentation:\nDoc\n \n\n\n \n \n \n\n===== \n Features =====\n\n1.\t8 Bit ALU\n2.\t8x8 Register File\n3.\t2048x16 Instruction Memory\n4.\t32x8 Ram Memory\n5.\t16x11 Stack Memory\n6.\tThree CLK/Instruction\n7.\tCarry and Zero flags\n8.\tNo operation Instruction (nop)\n9.\t8 bit Address Port (until 256 Peripherals)\n10.\tLDI, LDM, STM (Memory Access Instructions)\n11.\tCMP, ADD, ADI, SUB (Arithmetic Instructions)\n12.\tAND, OOR, XOR, NOP, SL0, SL1, SR0, SR1, RRL, RRR (Logical Instructions)\n13.\tJMP, JPZ, JNZ, JPC, JNC, CSR, RET, CSZ, CNZ, CSC, CNC (Flow Control Instructions)\n\n \n\n\n \n \n \n\n===== \n Instructions =====" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: natalius_8bit_risc status: FPGA proven svn-updated: Jun 5, 2012 updated: Jun 8, 2012 wishbone-compliant: 0 - category: Processor created: Aug 5, 2010 description: "===== \n Description =====\n\nNavr\xC3\xA9 is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\n\nAtmel AVR compatible\nAll Classic Core instructions implemented, except conditional branches on I/O registers\nNo interrupt support\nInterrupt related instructions behave as if the I (interrupt enable) bit is hardwired to 0\nVerilog-2001\nUsed to control the SoftUSB OHCI USB host\nFully synchronous\n2-stage pipeline\nAlmost cycle accurate with the original AVR. Most instructions execute in 1 cycle.\nSynthesis results (ISE 12.2 default, post performance evaluation P&R, XC6SLX45-2): 1K LUTs, 11.7ns (85MHz) clock period\n\n\nFor downloading the core, check the SoftUSB project.\n \n\n\n \n \n \n\n===== \n Testing wanted! =====\n\nEven though simple C programs can be run, the Navr\xC3\xA9 softcore still contains several bugs and testers are most welcome.\n\nThe idea is to use Verilog simulations to run and verify every instruction just like the simulavr test suite (which can be used for inspiration). Simple and incomplete test benches can be found with the SoftUSB core.\n\nIf you are interested in carrying out this work because you need an AVR compatible softcore in your design or just as a contribution to the Milkymist project, please contact the Milkymist-devel mailing list or drop by the #milkymist channel on the FreeNode IRC network.\n\nI will happily fix any bug you may find!" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: navre status: FPGA proven svn-updated: Aug 24, 2010 updated: Apr 19, 2013 wishbone-compliant: 0 - category: Processor created: Oct 27, 2006 description: "===== \n Description =====\n\nThis is a little-little processor core. It has 16 instructions. It is under developement again, since the latest version is deleted... It is not yet verified, tested, etc.\nIt's written in Verilog, generaly for Spartan.\n \n\n\n \n \n \n\n===== \n Features =====\n\n-It's very little.\n-Easy to understand.\n-Easy to convert.\n-Easy to compile the RISC or CISC instructions into this small set of commands.\n \n\n\n \n \n \n\n===== \n Status =====\n\nVer 0.1\n \"post-alfa\"\n\nVer 0.2\n There was many errors of syntax...\n So now there are corrected, it's ready to synthesize.\n Not yet wholly tested.\n\nNew in downloads:\n asm compiler C and Yacc/Lex versions (Alpha)\n simple simulator to verify the compiled code\n nCore 2: more procedure-capability\n nCore 3: safe multi-tasking-capability\n\n\nUnder developement:\n C, asm compilers, emulator, BIOS\nUnder planning:\n OS with cooperativ/hybrid multitasking, handling the configuration of the multicore system.\n Wishbone" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - stef name: ncore status: Alpha svn-updated: Mar 10, 2009 updated: Oct 28, 2007 wishbone-compliant: 0 - category: Processor created: Dec 12, 2003 description: "===== \n The Neptune core =====\n\nNeptune is an attempt to create a new, next-generation processor architecture.\n \n\n\n \n \n \n\n===== \n IMAGE: triton-block.png =====\n\nFILE: triton-block.png\nDESCRIPTION: This 8008 block diagram is filler until a new one is designed." language: '' license: unknown maintainers: - llama name: neptune-core status: Empty svn-updated: Mar 10, 2009 updated: Feb 19, 2006 wishbone-compliant: 0 - category: Arithmetic core created: Dec 6, 2012 description: '' language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - md_ayub4 name: network_on_chip status: Empty updated: May 10, 2013 wishbone-compliant: 0 - category: Processor created: Mar 12, 2012 description: "===== \n Description =====\n\n80186 instruction compatible, high performance processor, able to execute up to 40MIPS on a Spartan3AN FPGA. It requires ~1500 slices (25%) on a Spartan3AN. The speed performance is comparable with a 486 in 16bit real mode.\n \n\n\n \n \n \n\n===== \n Features =====\n\nNext186 CPU features:\n - All 80186 intstructions are implemented according with the 80186 specifications (excepting ENTER instruction, which uses always 0 as the second parameter - level).\n - all 80186 exceptions implemented (divide error - INT0, Trace - INT1, Overflow - INT4, Bounds - INT5, Invalid opcode - INT6, Coprocesor exception - INT7)\n - Mascable and non mascable interrupts implemented. If a repeat block instruction is interrupted, the return address is the repeated instruction including all prefixes. This allows fully resume of repeated instruction after interrupt, with no other precautions.\n - Designed with 2 buses: 16bit data / 20bit data_address and 48bit instruction / 20bit instruction_address. This allows most instructions to be executed in one clock cycle.\n - In order to link the CPU unit on a single memory bus, these sepparate data/instruction buses must be multiplexed by a dedicated bus interface unit (BIU).\n - It is able to execute up to 40 MIPS on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU (real mode, 16bit only).\n - Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN\n \n\nNext186 BIU (Bus Interface Unit) features:\n - Links the CPU with a 32bit static synchronous RAM (or cache)\n - Able to address up to 1MB \n - 16byte instruction prefetch queue\n - Works at 2 X CPU frequency (80Mhz on Spartan3AN), requiring minimum 2T for an instruction.\n - The 32bit data bus and the double CPU clock allows the instruction queue to be almost always full, avoiding the CPU starving. The data un-alignement penalties are required only when data words crosses the 4byte boundaries.\n\n\n\n \n\n\n \n \n \n\n===== \n Instruction timing =====\n\nHow to compute each instruction duration, in BIU clock cycles:\n\n1 - From the Next186_features.doc see for each instruction how many CPU T states are required (you will notice they are always\n less or equal than 486 and much less than the original 80186)\n\n2 - Multiply this number by 2 - the BIU works at double CPU frequency because it needs to multiplex the data and instructions,\n in order to keep the CPU permanently fed with instructions.\n\n3 - Add penalties, as follows:\n\n +1T for each memory read - because of the synchronous SRAM which need this extra cycle to deliver the data\n +2T for each jump - required to flush and re-fill the instruction queue\n +1T for each 16bit(word) read/write which overlaps the 4byte boundary - specific to 32bit bus width\n +1T if the jump is made at an address with the latest 2bits 11 - specific to 32bit bus width\n +1T when the instruction queue empties - this case appears very rare, when a lot of 5-6 bytes memory write instructions are executed in direct sequence\n\nSome examples:\n\n - \"lea ax,[bx+si+1234]\" requires 2T\n - \"mov word ptr [bx+si+1234],5678\" requires 2T\n - \"add ax, 2345\" requires 2T\n - \"xchg al, [bx]\" requires 4T\n - \"inc word ptr [1]\" requires 5T (2x2T inc M + 1T read)\n - \"inc word ptr [3]\" requires 7T (2x2T inc M + 1T read + 1T unaligned read + 1T unaligned write)\n - \"imul ax,bx,234\" requires 4T (2x2T imul)\n - \"loop address != 3(mod 4)\" requires 4T/2T (2x1T loop + 2T flush if jump)\n - \"loop address == 3(mod 4)\" requires 5T/2T (2x1T loop + 2T flush if jump + 1T unaligned jump)\n - \"call address 0\" requires 4T (2x1T call near + 2T flush\n - \"ret address 0\" requires 7T (2x2T ret + 1T read penalty + 2T flush)\n\n\n \n\n\n \n \n \n\n===== \n Testbench =====\n\nThe package contains a minimal demonstration system containing:\n\t- Next80186 CPU\n\t- Next80186 BIU - 32bit bus, 80Mhz (the clock can be easily modified by tuning the DCM - but you also need to adjust the bootstrap RS232 receiver code which uses delays made with loop).\n\t- 4KB SRAM (2KB at address 00000h - interrupt vector zone, 2KB at address FF800h - ROM zone)\n\t- 1DCM with 50Mhz input and 80Mhz output\nThe system is connected to RS232, to 9 LEDs on board and to a RESET button. \nThe SRAM is preloaded with a RS232 (115200bps) bootstrap able to load and run an executable at address FF80:0100.\nA sample .ASM application is provided (a simple RS232 feedback loop, with a mini memory dump feature).\n \n\n\n \n \n \n\n===== \n PC AT SoC - Running MS DOS 6.22 =====\n\nBooting DOS 6.22 on a Next186 PC AT SoC Xilinx Spartan 3AN used at ~50% (64MB DDR2, simplified VGA, PS2 KB and mouse, SDCard 4GB, 33MIPS, speaker sound)\n\nNC V5.0\n\nRunning BC++ v2.0\n\nRunning Turbo Pascal 7\n\nIndy MCGA\n\nPrince of Persia 2 MCGA\n\nWordPerfect 6.0 in 640x480x256\n'\nBattleChess4000 in 640x480x256, using EMM" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ndumitrache name: next186 status: FPGA proven svn-updated: May 13, 2014 updated: May 31, 2013 wishbone-compliant: 0 - category: System on Chip created: Jun 10, 2013 description: "===== \n Description =====\n\nPC AT SoC based on Next186 core. CPU runs at 33 MHz (up to 33 MIPS), 64MB of dynamic RAM, DOS6.22. \nAble to run DOS 8086, 80186 applications (most of 80286 applications/games are running ok). May run real mode 32bit 386 applications with a 32bit software extender (see EMU386).\nImplementation done and tested on Xilinx Spartan3AN evaluation board (with Xilinx ISE 14.5), occupying ~50% FPGA resources. \nVideo modes available: 80x25x256 text, 320x200x256 MCGA graphic, 640x480x256 VESA VBE mode 101h.\nPS2 8042 controller for keyboard and mouse.\nSimplified 8259 PIC, 8253 timer.\nBootstrap and BIOS ASM code provided.\nBesides the FPGA board, a SD HC card is required for the hard disk implementation.\nTheoretically, the system is able to run Windows3.0 in real mode if a VESA VBE 640x480x256 driver is provided (I was not able to find one available, or at least Windows3.0 DDK to write one).\n \n\n\n \n \n \n\n===== \n Contents =====\n\nAll building blocks of this system are either developed by me, or are IP cores provided by Xilinx ISE.\n\nCPU: Next186 core, (C) Nicolae Dumitrache, available on OpenCores.\nVGA: A custom VGA core which implements the text mode 3h 80x25x256, the MCGA graphic mode 13h 320x200x256 and the VESA graphic mode 101h 640x480x256. The other CGA/EGA/VGA planar modes were of no interest for me, as the CPU and RAM are fast enough to support a decent linear 256 colors palette graphic mode. Unlike the standard VGA, the mode 13h can support 8 hardware pages.\nTIMER: a simplified 8253\nPIC: a simplified 8259 programmable interrupt controller\nKb, Mouse: a simplified 8042 PS2 controller\nHard Disk - a SD HC 4GB external memory card is used as HD. For simplicity, I access it in SPI mode, being able to get a transfer rate up to 2 MB/s. All the transfer work is done by the CPU, with a minimal hardware interface.\nRS232: software driven interface, 1bit in and 1 bit out\nSpeaker sound\nReset button\nNMI button (useful for debugging, see Turbo Debugger)\nHALT LED\nNo DMA is necessary, as Next186 CPU is able to transfer up to 33MB/s with REP MOVSW.\n\nMore details are commented in the Verilog sources and in the BIOS code.\n\nAs for the IP cores, I used:\n2KB FIFO (32bit in, 16bit out, independent clocks) for VGA\nMIG DDRAM2 memory interface (slightly modified on some timings, as the original implementation was not working ok).\n4KB true dual port 8bit SRAM for text mode font\n2KB true dual port 8/32bit SRAM for 256bit VGA DAC color palette\n2KB true dual port 32bit SRAM for CPU cache\none DCM for DDRAM and VGA\none DCM for CPU\n\nThe CPU clock is independent from DDRAM clock (133MHz), and it can be adjusted from the CPU DCM. I managed to make it work stable at 33.3333Mhz on Spartan3AN FPGA (up to 33MIPS). The bus interface between CPU and the cache memory is 32bit width and it is working at double the CPU frequency (66.6666MHz). All 8/16bit I/O CPU operations are done at 33.33333 MOP/s.\n \n\n\n \n \n \n\n===== \n Booting =====\n\nThe system have no ROM, only 64MB of dynamic RAM and 4KB of code/data cache (8 lines of 256 bytes). In order to be able to boot, the cache is preloaded with the bootstrap code and marked as \"dirty\". At the first flush, the cache content will be transferred to RAM.\nThe bootstrap code tries to load the BIOS (8KB) from the latest 16 sectors of the SD card, at 0F000h:0E000h. If the SD card is not present, or BIOS is unavailable, the bootstrap code waits on RS232 (115200bps) an executable, loads it at 0f000h:100h and executes it.\n\n'\n \n\n\n \n \n \n\n===== \n Memory =====\n\nThe system uses all the dynamic RAM available on the Spartan3AN FPGA board (64MB at 133MHz). The memory is split as follows:\n640KB low DOS memory\n512KB video memory (which can be mapped over segments 0a000h and 0b000h) \n224KB upper memory, available to DOS through the XMM manager\n32KB ROM area, from which only the latest 8KB are actually used by the BIOS code.\n2MB available for the old INT15h extended memory mechanism\n\nThe rest ~61MB is available as extended memory (XMM), and in my DOS configuration, is used as follows:\n2MB for smartdrv (increases a lot the disk access)\n28MB RAM disk (not really necessary, as the SD hard disk + smartdrv is fast enough, but 64MB RAM is too much for DOS) \n16MB EMM (I use a LIMulator for 286)\n15MB XMM\n\nThe RAM is accessed in parallel by the CPU and the VGA. VGA uses a 2KB FIFO and have priority over CPU when the FIFO is empty. When the FIFO is not empty, the CPU have priority.\nThe VGA bandwidth occupy max ~7% of DRAM transfer capacity (in 640*480 resolution), allowing the CPU to access the RAM (including video RAM) with almost no penalty. The effective RAM (including video) CPU transfer rate is 20-30MB/s (and 40-60MB/s fill rate).\nThe RAM is divided in 64Kb pages. Each page can be mapped over each of the first 16 64Kb segment addresses. This mechanism is used for accessing the video memory in mode 13h (8 pages) and mode 101h VESA, and also for the extended/expanded memory access. \n\n\n\n \n\n\n \n \n \n\n===== \n Software =====\n\nI provided in the package the assembler source code for the boot loader and for the BIOS.\nThe BIOS code is quite small, taking only 8KB beginning with 0f000h:0e000h. All the rest of the RAM upper memory is available for DOS.\nThe VESA VBE interface and all required paged memory access code for XMM is contained inside the BIOS.\nA RS232 communication application executable is also provided (SerialComm.exe). It can be used to transfer applications or files from a PC to the Next186 SoC through a serial link.\n\nLately I installed GEOS (Geoworks Ensemble v2.0 and Breadbox Ensemble v4.1.2). With 16MB XMS swap space, almost 900KB global heap (in the first megabyte), and a CPU ~80 times faster than standard XT, it's working like a charm in VESA 640x480x256 colors.\n \n\n\n \n \n \n\n===== \n Screenshots =====\n\nBorland C++ v2.0, Turbo Pascal v7.0\n\n\nIndy MCGA, Prince of Persia 2 MCGA\n\n\nWordPerfect 6.0 VESA 640x480x256, BattleChess4000 VESA 640x480x256\n\n\nGeoWorks Ensemble 2.0 VESA 640x480x256, Breadbox Ensemble v4.1.2 VESA 640x480x256\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n LATTICE MachXO2 -7000HE port =====\n\nI uploaded the latest port of Next186 SoC, on the Valentin Angelovski's tiny but great FleaFPGA board (Lattice MachXO2-7000H, 32MB SDRAM, http://www.fleasystems.com/fleaFPGA.html )\nIt is working at 100Mhz SDRAM, 50Mhz bus, 25Mips) ~11000 Dhrystone 2.1\nIt takes ~78% FPGA area.\n\nThe SoC was extended with the following features:\n- A20 address line, HMA area available\n- added VGA mode 12h (640x480x16 - planar), allowing Windows3.0 to run (and also GEOS and Arachne web browser)\n- added EGA mode 0dH (320x200x16 - planar), allowing a lot of old EGA DOS games to run\n- ModeX support - more great DOS games are running (like Ultima Underworld, and Wolfenstein 3D - playable even in max screen mode).\n- USB flash drive transfer" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ndumitrache name: next186_soc_pc status: FPGA proven svn-updated: May 14, 2014 updated: Jan 7, 2015 wishbone-compliant: 0 - category: System on Chip created: Feb 27, 2015 description: "===== \n Description =====\n\nThis is an evolution of my previous project, Next186SoC PC, able to play MP3 files in real time (any bitrate).\nIt is written in Verilog, and it contains all the features of Next186SoC PC, plus a few more.\n \n\n\n \n \n \n\n===== \n Contents =====\n\nThis is a PC SoC able to run 16bit DOS. It features the following elements:\n- a 80186 compatible CPU, running at 40MIPS (Netx186)\n- 16KB of cache: 4-way set associative\n- SDRAM interface (up to 64MB of SDRAM supported, through EMM and XMM)\n- High Memory Area (HMA) useable in DOS\n- Text mode, EGA(320x200x16), VGA(640x480x16, 320x200x256, ModeX), VESA(640x480x256)\n- a sound queue (16KB), able to deliver CD quality stereo sound (44100Hz) at 2 digital pins (pulse density modulation over a RC integrator: 1Kohm + 10nF). For the best sound quality I recommend a high impedance (>10Kohm) low pass filter (I use a 4th order low pass active Butterworth filter). The sound interface is also compatible with Disney Sound source and with Covox Speech thing, which provides improved sound for some DOS games.\n- a 32bit DSP coprocessor, able to assist the main CPU at MP3 decoding (and not only) - it takes only 5-7% LUTs of the SoC, plus 4x18bit multipliers\n- SD card interface (in SPI mode). FAT16 formatted disks are limited at 2GB. In order to use SD cards of up to 32GB, I used FreeDos 16bit, which supports FAT32.\n\nMy current implementation is done on a Spartan6XC6SLX9 (Papilio Pro), it is running at 80Mhz (40Mips), have 8MB of SDRAM running at 140Mhz.\nThe DSP is running at the bus speed of 80Mhz.\nIt uses ~4200xLUT6 (from 5700 available) and 5x18bit multipliers (from 16 available).\nFor the interface, I extended Arcade Mega Wing to 18bit VGA DAC, and I added a SD card interface.\n\nWithout the DSP, the Next186 CPU is able to provide 50% of the required power for decoding a MP3 file. With the DSP coprocessor, it provides ~150%.\n\n \n\n\n \n \n \n\n===== \n DSP =====\n\nThe DSP have 2K instructions of 16bits, and 256x32bit registers.\nEach instruction can address 2 registers from a 64 registers page. The 64reg pages can be mapped over the 256 registers.\nThe DSP is based on a two stage exposed pipeline, executes one instruction/clock and it is able to execute code in parallel with the main CPU. More than that, the main CPU is able to transfer data to/from DSP registers while the DSP is running, allowing more parallelization.\nThe DSP can do 32bit operations (additions, subtractions, multiplications, shift right, 16bit packing, logical operations). It have no jump, looping, subroutine call capabilities. \nThe instruction set is detailed in the Verilog DSP32.v file.\n\nThe MP3 decoding code occupies under 1K instructions." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ndumitrache name: next186mp3 status: Stable svn-updated: Mar 10, 2015 updated: Mar 10, 2015 wishbone-compliant: 0 - category: Processor created: Mar 18, 2011 description: "===== \n Description =====\n\n- Z80 compatible processor.\n- All documented / un-documented intstructions are implemented. \n- All documented / un-documented flags are implemented.\n- All (doc / un-doc) flags are changed accordingly by all (doc / un-doc)instructions. The block instructions (LDx, CPx, INx, OUTx) have only the documented effects on flags. The Bit n,(IX/IY+d) and BIT n,(HL) un-documented flags XF and YF are implemented like the BIT n,r XF and YF, not actually like on the real Z80 CPU.\n- All interrupt modes implemented: NMI, IM0, IM1, IM2.\n- R register available. \n- Fast conditional jump/call/ret takes only 1 T state if not executed. \n- Fast block instructions: LDxR - 3 T states/byte, INxR/OTxR - 2 T states/byte, CPxR - 4 T states / byte \n- Each CPU machine cycle takes (mainly) one clock T state. This makes this processor over 4 times faster than a Z80 at the same clock frequency (some instructions are up to 10 times faster). \n- Works at up to 40MHZ on Spartan XC3S700AN speed grade -4) - performances similar or better than a real Z80 running at 160Mhz. \n- Small size (~12%, ~700 slices - on Spartan XC3S700AN). \n- Tested with ZEXDOC (fully compliant) and with ZEXALL (all OK except CPx(R), LDx(R), BIT n, (IX/IY+d), BIT n, (HL) - fail because of the un-documented XF and YF flags). \n \n\n\n \n \n \n\n===== \n Testbench =====\n\nThe test bench is a micro computer based on NextZ80 processor (tested on Xilinx Spartan 3AN).\nMain features:\n- NextZ80 CPU running at 40 MHZ\n- the CPU receives maskable interrupt at the end of each scan line. The interrupt vector is 0x00, allowing all IM modes (IM0 = NOP, IM1 = RST38, IM2 = jump at mem[I:0]). It can be used for border effects or for ink - paper - video memory effects.\n- 32 KB static RAM\n- VGA (640*480) screen, with 128 lines upper border, 80x24 characters (8x8 pixels each), and 160 lines lower border.\n- screen buffer (1920 bytes) at address 0x7800\n- character map (2048 bytes) at address 0x7000\n- output port 1 - border color (R3G3B2)\n- output port 2 - ink color (R3G3B2)\n- output port 4 - paper color (R3G3B2)\n- output port 8 - {bit0 = PS/2 clk, bit1 = PS/2 data, bit2 = RS232 TxD}\n- input port 0 - scan line lower 8 bits\n- input port 1 - { bit1:0 = scan line upper 2 bits, bit2 = PS/2 clk, bit3 = PS/2 data, bit4 = RS232 RxD}\n- 1 DCM (supplied with 50 MHZ), providing the 25MHZ VGA clock and 120MHZ system clock.\n- 1 reset button\n- 1 HALT LED\n- RS232 interface\n- PS/2 keyboard interface\nThe CPU is fed with 120Mhz, but 2 from 3 states is in WAIT. This way, the CPU runs at 40Mhz, allowing one clock state for the video generator to read the memory (no contention between CPU and VGA).\nThe system clock is flexible, it can be adjusted from 120Mhz, by re-programming the DCM\nThe boot loader waits for RS232 (115200 bps) to receive a binary file. It places it at address 100h and then launches it. The binary file can be a .COM CP/M file, which uses at most BDOS 2 and 9 functions (print char and string) - this is the case for ZEXDOC.COM and ZEXALL.COM, which may be directly uploaded.\n\nA RS232 communication application is provided (SerialComm).\n \n\n\n \n \n \n\n===== \n Screenshots =====\n\nBenchmark results: \nThe ZEXALL/ZEXDOC Z80 instruction exerciser takes 5min:16sec to finalize." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ndumitrache name: nextz80 status: FPGA proven svn-updated: Feb 6, 2014 updated: Jul 3, 2014 wishbone-compliant: 0 - category: Crypto core created: Jun 27, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - arif_endro name: nfcc status: Alpha svn-updated: Jun 29, 2010 updated: Jun 27, 2010 wishbone-compliant: 0 - category: Crypto core created: Jun 24, 2010 description: "===== \n Description =====\n\nNugroho Free Hash Cores (NFHC) currently support SHA-1, SHA-256, SHA-512 from FIPS-180 standard." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - arif_endro name: nfhc status: Design done svn-updated: Jun 25, 2010 updated: Jun 24, 2010 wishbone-compliant: 0 - category: Other created: Feb 23, 2012 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tklauser name: nios2ci status: Alpha svn-updated: Jan 17, 2013 updated: Feb 23, 2012 wishbone-compliant: 0 - category: System on Chip created: Apr 27, 2009 description: "===== \n NoC(Network-on-Chip) =====\n\nNoC(Network-on-Chip)\n\nFeatures\n-Maximum 4 by 4 Tiles\n-The synchronizing FIFO\n-Wormhole routing\n-Virtual channel(3 stage buffer)\n-User reconfigure PE(Processing element)'s program" language: SystemC license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - imori name: noc status: Planning svn-updated: May 1, 2009 updated: Nov 9, 2009 wishbone-compliant: 0 - category: System on Chip created: Apr 5, 2007 description: "===== \n Description =====\n\nA Network on Chip Emulation Tool, NoCem is a body of VHDL code configurable by a toplevel package file that can create a variety of Network on Chips on parameters of datawidth, virtual channel implementations, topology, and in-network buffering lengths. Once parameterized, the resulting NoC is generated automatically with heavy use of VHDL generics and generate statements.\n\nauthor - Graham Schelle\n \n\n\n \n \n \n\n===== \n Features =====\n\n- synthesizable VHDL code for network on chip creation\n - FPGA implemented\n - tested/verified\n- virtual channel implementation option\n- processor bridge for Xilinx Microblaze or PowerPC \n \n\n\n \n \n \n\n===== \n Status =====\n\n- Initial addition of codebase and documentation\n- Fully verified\n- Published at WARFP2006" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - schelleg name: nocem status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 1, 2013 wishbone-compliant: 0 - category: System on Chip created: Feb 24, 2011 description: "===== \n Description =====\n\nNoCmodel is a Python module for Network-on-Chip modeling, with add-ons for simulation (functional or RTL) and code generation (initially VHDL). \nBased on Python language, this module provides a framework for generic modeling of a NoC (IP Core nodes, routers, or channels), and provides some add-ons that extends the model to support design features like functional simulation, RTL simulation, VHDL code generation, etc. \nNoCmodel is based on NetworkX (http://networkx.lanl.gov) for graph modeling, and MyHDL (http://www.myhdl.org) for simulation support." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dargor name: nocmodel status: Alpha svn-updated: Jul 6, 2012 updated: Mar 4, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Jul 25, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: noekeon status: Empty updated: Sep 28, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nVHDL implementation of the NOEKEON block cipher (iterative architecture)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: noekeoncore status: Stable svn-updated: Jul 27, 2013 updated: Jul 27, 2013 wishbone-compliant: 0 - category: Video controller created: Apr 21, 2008 description: "===== \n Overview =====\n\nNova is a low-power realtime H.264/AVC baseline decoder of QCIF resolution, targeting mobile applications. It is a dedicated, full hardwired and self-contained ASIC design without utilizing any GPP/DSP cores. It has been successfully verified on Xilinx Virtex-4 FPGA and 0.18um ASIC chip. The measured power consumption is 293uW@1V for 30fps QCIF decoding.\n\nFrom April 30 2008, Ke Xu has the Copyright for nova. If you have interests of continuing to develop this core or implementing in commercial product, please drop me an email (eexuke@yahoo.com) for discussion.\n \n\n\n \n \n \n\n===== \n Features =====\n\n1.RTL coded in Verilog-HDL.\n2.Support real-time H.264/AVC baseline decoding of QCIF resolution. Can be extended to higher resolutions via minor modifications.\n3.Extensively pipelining & parallelism are utilized to improve the performance and reduce power.\n4.Hybrid and self-adaptive pipeline architecture to avoid unnecessary stall cycles and to improve performance:\n-Self-adaptive pipeline for both intra and inter prediction.\n -4\xC3\x974/16\xC3\x9716 hybrid pipeline.\n -1\xC3\x974 pixel column-level parallelism. \n5.Low cost intra prediction unit:\n-Self-adaptive pipeline.\n-Hierarchical memory organization to reduce external memory access.\n-\xE2\x80\x9CSeed\xE2\x80\x9D method for plane mode computation.\n-Exploring data reuse between 1\xC3\x974 columns.\n-Multi-function Processing Elements for all intra prediction modes processing. \n6.Optimized motion compensation (inter prediction) unit:\n-Self-adaptive pipeline.\n-Hierarchical memory organization to reduce external memory access.\n-\xE2\x80\x9CVariable-block-shape\xE2\x80\x9D to reduce redundant memory access and improve throughput.\n-On-chip reference pixel buffer to explore reference pixel reuse.\n-Pipelined and parallelized luma interpolator, consisting of 9 horizontal 6-tap filters, 4 vertical 6-tap filters, and 4 bilinear filters.\n-Innovative chroma interpolator utilizing smallest number of adders.\n7.High performance deblocking filter:\n-Innovative 5-stage pipeline architecture with data/structure hazards carefully managed.\n-Single-port SRAM based, no dual/two-port SRAM required.\n-204cycles/MB throughput with max. frequency of 200MHz (0.18\xC2\xB5m process). Can deliver up to 980kMB/s throughput.\n8.Manually inserted latch-based clock gating to reduce power.\n9.Low-power, low-cost design:\n-Requires only ~1.5MHz for QCIF 30fps real time decoding.\n-Only 169k logic gates.\n-Measured power consumption as low as 293\xC2\xB5W@1V in 0.18um process.\n\n \n\n\n \n \n \n\n===== \n Project News =====\n\n----------------\n2009-08-11\n----------------\nFor better understanding of nova design, you can refer to the following documents:\n1) Ke Xu, \"Power-efficient Design Methodology for Video Decoding\", PhD thesis, The Chinese University of Hong Kong, 2007.\n2) Ke Xu, T. M. Liu, J. I. Guo, C. S. Choy, \xE2\x80\x9CMethods for Power/throughput/area Optimization of H.264/AVC Decoding\xE2\x80\x9D, Journal of Signal Processing Systems, 2009, DOI 10.1007/s11265-009-0408-6. \n3) Ke Xu, C. S. Choy, \xE2\x80\x9CA 5-stage Pipeline, 204 Cycles/MB, Single-port SRAM Based Deblocking Filter for H.264/AVC\xE2\x80\x9D, IEEE Transactions on Circuits and Systems for Video Technology, vol. 18, issue 3, pp. 363 \xE2\x80\x93 374, 2008.\n4) Ke Xu, C. S. Choy, \xE2\x80\x9CA Power-efficient and Self-adaptive Prediction Engine for H.264/AVC Decoding\xE2\x80\x9D, IEEE Transactions on VLSI Systems, vol. 16, issue 3, pp. 302 - 313, 2008.\n5) Ke Xu, C. S. Choy, C. F. Chan, K. P. Pun, \xE2\x80\x9CPower Efficient VLSI Realization of Complex FSM for H.264/AVC Bitstream Parsing\xE2\x80\x9D, IEEE Transactions on Circuits and Systems, Part II, vol. 54, issue 11, pp. 984 \xE2\x80\x93 988, 2007. \n6) Ke Xu, C. S. Choy, C. F. Chan, K. P. Pun, \xE2\x80\x9CPriority-based Heading One Detector in H.264/AVC Decoding\xE2\x80\x9D, EURASIP Journal on Embedded Systems, vol. 2007, Article ID 60834.\n7) Ke Xu, C. S. Choy, \xE2\x80\x9CLow-power H.264/AVC Baseline Decoder for Portable Applications\xE2\x80\x9D, International Symposium on Low Power Electronics and Design, pp. 256 - 261, Sept. 2007, Oregon, USA.\n\nYou may send me an email to ask for my PhD thesis, while you can find other documents by Google or from IEEE website.\n\n----------------\n2009-04-04\n----------------\nThe design of a multi-standard (MPEG-2/H.264/VC-1, may even include Chinese AVS) decoder which supports QCIF to HDTV 1080p resolution is launched. The decoder is based on original nova core and is scheduled to complete at the end of 2009 (or early 2010). Any interests of license this high-performance/low-cost/low-power IP, please contact me at eexuke@yahoo.com for more details.\n\n----------------\n2008-05-02\n----------------\nSpecification, test files added.\n\n----------------\n2008-04-30\n----------------\nVerilog source code updated. Detailed specifications, documents, and test files to be updated soon." language: Verilog license: unknown maintainers: - eexuke name: nova status: ASIC and FPGA proven svn-updated: Mar 10, 2009 updated: Jul 4, 2014 wishbone-compliant: 0 - category: Video controller created: Apr 28, 2008 description: "===== \n Description =====\n\nThe design provides basic video function.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Configurable resolution up to 1600x1400\n- Configurable pixel width 16,32 bit per pixel\n- Configurable Burst Size and NPI width\n- Stride support\n- Direct memory access through Xilinx NPI channel\n- Support Spartan3x family, Virtex4, Virtex5\n- Demo design and bitstream available for EUS FS, ML403, ML405 and ML505\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Resolutions: 640x480x32/16; 800x600x32/16; 1024x768x32/16; 1600x1200x16\n- Tested platforms Spartan3E, Virtex4, Virtex5\n- Design is available in VHDL - XPS core\n \n\n\n \n \n \n\n===== \n To do =====\n\n- Docs\n- Add virtual DMA engine\n- Add multilayer support with an alpha-blending\n- Accelerator pipe\n- Graphical Library Support (Allegro and AGG)\n \n\n\n \n \n \n\n===== \n Reference designs =====\n\nNPI_VGA_CTRL resolution 800x600: Spartan 3E demo design with sources - EDK 10.1 - board EUS FS\n NPI_VGA_CTRL resolution 1280x1024x32b@60Hz: Virtex 4FX demo design with sources - EDK 10.1 - board ML405\n Spartan3AN - AGG Demo resolution 800x600x12bit resolution\n \n\n\n \n \n \n\n===== \n AGG Demo =====\n\nThe ML405 board AGG demo example that demonstrates clipping to multiple rectangular regions. The example is rendered at PPC. The resolution is 1280x1024x32bits without HW accelerator. \n\n\n\n\n\nThe demos can be downloaded at:\n\n\n ml405.rar AGG Demo\n eus_FS - Spartan 3E AGG Demo resolution 800x600x32\n eus_FS - Spartan 3E AGG Demo resolution 800x600x16 - agg_demo_eus_fs_16bits.rar\n Spartan3AN - AGG Demo resolution 800x600x12bit resolution\n\n\n\n After download unpack the file, initiate FPGA by downloading bitstream and download demo software by XMD:\n\n\n- cd demo_app_1 \n- dow executable.elf\n- run" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - slavek name: npigrctrl status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 20, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Apr 13, 2014 description: "===== \n Description =====\n\n// number sorting device, sequential, 2*N clocks for N\n// linear buffer implementation\n// sequential, stable, can be partly readed, decreasing order\n// reset is not implemented\n// see sort_stack_algorithm.png to catch the idea\n\n// number sorting, tree-like implementation, sequential, \n// energy efficient (theoreticaly) \n// see sort_tree_algorithm.png to catch the idea\n\nArticle(Russian): http://habrahabr.ru/post/222287/" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - leshabirukov name: numbert_sort_device status: FPGA proven svn-updated: Aug 22, 2014 updated: May 10, 2014 wishbone-compliant: 0 - category: Prototype board created: Sep 25, 2001 description: "===== \n Introduction =====\n\nAs you know, we have lots of free IP cores here, and we\xE2\x80\x99ll have more coming soon. We have to use these cores otherwise they are invaluable. For this reason the idea of designing serials and open design boards are going to be available for any designers around the world. \n \n\n\n \n \n \n\n===== \n Objective =====\n\nThis project is intended to: \n- To design schematic can deal with analog signal and transport through Ethernet. \n- To implementation CPU core and Ethernet core to one FPGA chip \n- To program the necessary operation system and application software to achieve the goal. \n- To build the prototype board. \n- To do the test for all functions. \n \n\n\n \n \n \n\n===== \n Design flow =====\n\nThis project can be divided into two parts. The board design and the cores design. Anyone can use free or commercial tools to design and implement this project\n\nBoard design flow can be done through four steps: \n\n- Block Diagram design: I hope we use word 97+ for easy modify and exchange. \n- Schematic entry: I will post schematic using PDF format. Anyone can also send me using PDF, protel99se or Cadence format. \n- Layout design: The final layout will use Allegro or Protel99se. \n- Board implementation: This is the final step in the design where the designer should work himself to produce his board unless we get funding or donation from PCB manufactory. \n\nCores design flow can be done through five steps: \n\n- Design entry: Doesn t matter the tools, we exchange only VHDL or Verilog codes. \n- Simulation: I hope to use ModelSim or Active-HDL, but other tools also welcome. \n- Synthesis: I hope to use FPGA express, but other tools also welcome. \n- Implementation: I hope to use Xilinx FPGA. \n- Programming Download: Using onboard parallel cable. \n \n\n\n \n \n \n\n===== \n System description =====\n\nThis is the Board block diagram\n \n\n\n \n \n \n\n===== \n IMAGE: ver02.jpg =====\n\nFILE: ver02.jpg\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== =====\n\nThe system is composed of 5 main blocks: \n- Xilinx FPGA, PROM and parallel interface \n- SRAM circuit \n- ADC and DAC interface \n- Ethernet interface \n- Power and reset circuit \n \n\n\n \n \n \n\n===== \n Schematic design =====\n\nTBD\n \n\n\n \n \n \n\n===== \n Layout design =====\n\nTBD\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 2001.8.20 Upload Board block diagram version 0.1\n- 2001.8.21 Upload Board block diagram version 0.2\n \n\n\n \n \n \n\n===== \n Reference tools and links =====\n\nXscope\nhome page \n\n\n\n\n\n\nSSM2141\nDatasheet\n\n\n\n\nDAC8248\nDatasheet\n\n\n\n\n\nAD7854\nDatasheet\n\n\n\n\n\nRTL8201\nDatasheet\n\n\n\n\n\nPE68515\nDatasheet\n\n\n\n\n\nXilinx\nVirtex-E Datasheet" language: '' license: unknown maintainers: - martinj name: oab1 status: Empty svn-updated: Mar 10, 2009 updated: Oct 15, 2001 wishbone-compliant: 0 - category: Arithmetic core created: Mar 9, 2011 description: "===== \n Description =====\n\nObject Tracking using Meanshift algorithm." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: object_tracking status: Empty updated: Apr 22, 2011 wishbone-compliant: 0 - category: System on Chip created: Aug 20, 2009 description: "===== \n Description =====\n\nThe goal is to develop an H.264 Encoder SoC (System-on-Chip) solution based only on open-source blocks.\n \n\n\n \n \n \n\n===== \n Status =====\n\n2009-08-24:\nA software-team is assembled and are now looking into the first task, which is to get profiling information about the VLC x264 encoder. \nWe basically need this to understand what functions are suitable to extract from the VLC-SW and then be implement as HW instead. We also need to discuss the pros/cons of moving different functions to hardware (size/performance issues etc)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - AndreasBrok - goldenmean - ajitsk - alex77 - andyzexia - apurvbhatt - bhavikhthakar - wyx008 - ckavalipati - gijoprems - gil_savir - gouthamnvaidhya - gshankara - krillobit - mike - sgirimaji - thiagu_comp - thsteinle - toanfxt - vintu - hakunamatata - newfish - jeffzhan - robinliuy - jackoc - julius name: oc-h264-encoder status: Planning svn-updated: Nov 17, 2009 updated: Jun 17, 2011 wishbone-compliant: 0 - category: Processor created: Apr 8, 2002 description: "===== \n Description =====\n\nThe OpenCores54x (OC54x) DSP core is a cleanroom implementation of a popular family of DSPs designed by the No.1 DSP supplier from the southern part of the US.\n\nThe core is designed to be software compliant with the original Texas Instruments C54x DSP. However, the core is not designed to be 100% compatible with the TI's C54x chips. The core features some extension and improvements over the original design, which make it not-compatible. Also, partially caused by the structure choosen, partially to not completely compete with TI, some operating modes and hence opcodes are not supported. See the compatibility section for more detailes.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 16/32, dual-16 bit DSP core\n- 4 Wishbone compliant external busses\n- highly pipelined for high performance\n- Up to 5 operations per cycle\n- structural & opcode compatible with TI's C54x family of DSPs\n- First synthesis results: >40MHz in FPGA, >300MHz in .18u\n \n\n\n \n \n \n\n===== \n Status =====\n\nFinished:\n- CPU\n- ALU\n- MAC\n- Barrel Shifter\n- Compare Select Store Unit (CSSU)\n- Auxiliary Register Arithmetic Unit (ARAU)\n\nToDo:\n- Data Address Generator\n- Program Address Generator\n- Instruction Decoder\n \n\n\n \n \n \n\n===== \n Tools =====\n\n- Texas Instruments C54x Code Composer Studio or C54x compiler/assembler/linker\n- GCC (GNU binutils 2.11 and later). Use tic54x as the target (--target=tic54x)\n \n\n\n \n \n \n\n===== \n Compatibility =====\n\nListed below are known issues between this implementation and Texas Instruments C54x DSPs.\n\n- CMPT is not supported.\nThe compatibility bit is not supported. As a result ARP is always set to zero.\n- EDB is 32bits wide,\nThe EB data bus is 32bits wide to support single cycle 32bit write accesses. Long words are always written in 1 cycle. In contrast to the C54x there's no difference between even and odd word addresses. The MSB is always written at the higher address." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rherveille name: oc54x status: Beta svn-updated: May 5, 2009 updated: Jan 20, 2004 wishbone-compliant: 1 - category: Communication controller created: Jun 11, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - prashb name: oc_xge_mac status: Empty updated: Jun 11, 2013 wishbone-compliant: 0 - category: Prototype board created: Sep 25, 2001 description: "===== \n Specifications =====\n\n- small form factor (1dm2) \n- inexpensive surface mount technology (no Ball Grid Array (BGA) chips) \n- fast 50k gates or bigger FPGA \n- basic I/O capabilities like RS232 and IRDA \n- FLASH memory for FPGA configuration and microprocessor code \n- fast SDRAM for main memory \n- direct access to important signals through Logic Analyzer connectors\n \n\n\n \n \n \n\n===== \n Description =====\n\nOpenCores Reference Platform 1 (OCRP-1) standalone board was designed as a common prototype platform for testing our IP cores. It has a central FPGA for evaluating and testing IP cores, I/O capabilities, DRAM and FLASH memory. It also has several I/O, JTAG and expansion connectors. It even has real-time clock and a battery. Current PCBs have four layers. \n \n\n\n \n \n \n\n===== \n IMAGE: block.gif =====\n\nFILE: block.gif\nDESCRIPTION: Block diagram of a OCRP-1 standalone prototype board\n\n \n\n\n \n \n \n\n===== \n Board snapshots =====\n\n\nbottom side (178 KB) - at this stage first prototype wasn't fully assembled\nupper side (173 KB) - at this stage first prototype wasn't fully assembled\nit works ! (175 KB) - first test design downloaded to Virtex FPGA was just a simple DLL with 40MHz input and 80MHz output clock\ntest environment (180 KB) - HP16500 in Iskratel labs\nPCBs (179 KB) - still waiting to be assembled\nupper side of PCB (90 KB) - close up of unassembled PCB\nbottom side of PCB (89 KB) - close up of unassembled PCB\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n\nfirst prototype assembled and fully functional (see snapshots)\nschematic is available as Adobe PDF document (674 KB)\ngerber is available (251 KB)\nbill of materials (30 KB) (some comments are in Slovene Language)\nBSDL files for JTAG chain:XC95288XL-TQ144C (40 KB),\nXCV50-TQ144C (33 KB) and\nXCV100-TQ144C (40 KB)\n\n\n \n\n\n \n \n Wilhelm Mikroelektronik GmbH\">\n\n===== wilhelm_mikroelektronik_gmbh\">\n Availability of bare PCBs through Wilhelm Mikroelektronik GmbH =====\n\nWilhelm Mikroelektronik GmbH\">\n It is a 4 layer multilayer with solder mask, hot air leveling finish and\ncomponent print on both sides. All boards have been electronicly tested\nagainst the Gerber data (picture).\n\n\n\nShipping is done by normal air mail in an envelope protected by sealed air.\nEach letter will contain an official invoice calling the product \"printed\ncarrier board for education and evaluation purpose\". \nWilhelm Mikroelektronik is not responsible for any problems with customs and they do not give any\nwarranty on the board. They don't take responsibility for any problems that\nmight occur when assembling the board and they can\xC2\xB4t provide any support for\nthe board. \n\n\n\nWe would like to stress that the fine pitch SMD parts are not intended for\nthe unexperienced people. You should be sure that you can assemble it.\nIf there is actually a problem with any of the boards (this should not\nhappen because of electronic testing) Wilhelm Mikroelektronik will of course provide a free replacement of the PCB.\n\n\n\nIf anybody need the stencils for solder cream. They can provide that, too.\nThe price per pair (top/bottom) is USD 100 including shipping. Just add to\nthe order sheet manually.\nFor manual soldering the stencils are not required.\n\n\n\n \n\n\n \n \n \n\n===== \n Availability of assembled boards =====\n\nDue to low demand we have decided not to offer assembled boards. \n \n\n\n \n \n \n\n===== \n Ordering =====\n\nJust completly fill in order form and it fax back to the Wilhelm Mikroelektronik. They will immediatly process the order. There should be sufficient number of boards on stock. Worldwide registered and insured shipping is now per piece. Payment options are credit card or prepayment to their account (if you can't do credit card payment).\nIf you need to get in contact with Wilhelm Mikroelektronik, you can send e-mail message to ocrp1@wilhelm.de.\n\n\n\nThe following options are available:\nunassembled board USD 30,- (plus USD 10 shipping)\nconnector set: J1/J2, CONN-F, POD 1-3, B1, KE1 USD 37,- (USD 15 shipping)\n\n\n\n\nThere won\xC2\xB4t be any component kits to avoid warranty problems.\n \n\n\n \n \n \n\n===== \n Acknowledgment =====\n\nSpecial thanks to Matija Golar and DD Digital Development for providing layout services.\n\n\nSpecial thanks to Janez Smid, Tomaz Stare, Matija Milostnik and Brane Lipar from Iskratel for help with design, organizing PCB manufacturing and layout services. Special thanks to Franc Dolenc and\nIskratel for sponsoring prototype development.\n\n\n\nSpecial thanks to Igor Mohor and Asyst Electronic for assembling the first prototype.\n\n\n\nSpecial thanks to info@wilhelm.de and Wilhelm Mikroelektronik GmbH for manufacturing and providing OCRP-1 boards to the OpenCores community.\n \n\n\n \n \n \n\n===== \n Authors =====\n\n\nOvidiu Lupas\ndamjanl@opencores.org\nIskratel" language: board schematic license: unknown maintainers: - lampret - olupas name: ocrp-1 status: Stable svn-updated: Mar 10, 2009 updated: Jan 22, 2004 wishbone-compliant: 0 - category: Communication controller created: Mar 9, 2005 description: "===== \n Description =====\n\nThe main file is modem.vhd\n\nI don't separate the test part from modulation part.\n\nThe main modulation part is ofdm.vhd, and you can chose if it will work as TX or RX, the bit size. But, don't change Point and Stage, it has a bug.\n\nAnother time I write more (and better).\n\nForgive my english.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\nHave a bug if change the fft size." language: VHDL license: unknown maintainers: - tmsiqueira name: ofdm status: Beta svn-updated: Mar 10, 2009 updated: Dec 30, 2012 wishbone-compliant: 0 - category: Processor created: Jan 20, 2006 description: "===== \n Description =====\n\nThe oks8 project is intended to provide a microcontroller in Verilog that like\nthe KS86C4204/C4208/P4208 microcontroller (Samsung Inc.). It is compatible\nwith the SAM87RI instruction set and has some changes to support uC/OS.\n\nTwo different top levels: \n\n- Less cycles of each instruction\n- 16bits program memory and data memory\n\nSAM87RI, KS86C4208, etc. are Trademarks of Samsung Inc. I have no idea if\nimplementing this core will or will not violate patents, copyrights or cause\nany other type of lawsuits. I provide this core AS IS, without any warranties. \n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Capable of executing all SAM87RI instruction set.\n- 8bit external data bus width.\n- 16bit (64Kb) program address space.\n- 16bit (64Kb) data memory space.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Fully tested in software simulation running code compiled with SASM. \n- Completed and verified on xilinx fpga." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - kongzilee name: oks8 status: Alpha svn-updated: Mar 10, 2009 updated: Jan 24, 2006 wishbone-compliant: 1 - category: Prototype board created: Jul 27, 2008 description: "===== \n Description =====\n\nOMRP (Openpattern Modular Routing Platform) is the first product-oriented project of the OpenPattern company. The target is to create a new open hardware FPGA-based network router that can be used for mesh wifi networks, as an alternative of ISPs home-gateway, and as a development platform for future open-hardware SoC projects.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Open hardware - schematics and HDL sources will be/are released.\n- Flexible - implement whatever hardware acceleration or protocol you want in the FPGA.\n- Modular - many standard extension ports are implemented.\n- Unbrickable - everything (filesystem, kernel, ...) is stored on a SD card you can easily replace.\n- Developer-friendly - even FPGA configuration is stored on the SD card, you don't need any special hardware to get into FPGA development.\n- ucLinux-based.\n\n \n\n\n \n \n \n\n===== \n Specifications =====\n\n- Xilinx XC3S1200E FPGA used as system-on-chip\n- 32 Mo SDRAM\n- 1x Mini PCI connector\n- 2x 10/100 Ethernet PHY\n- 1x USB peripheral port\n- 2x USB host port\n- 2x SDIO connector\n\n \n\n\n \n \n \n\n===== \n Availability =====\n\nThe board is not available yet. For more information and updates, visit http://www.openpattern.org" language: Other license: unknown maintainers: - debianiste - carcelle - florian name: omrpv2 status: Empty svn-updated: Mar 10, 2009 updated: Jul 1, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Apr 11, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Dbone name: on_chip_trace_system status: Empty updated: Apr 11, 2013 wishbone-compliant: 0 - category: Testing / Verification created: Apr 11, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Dbone name: onchip_trace_system status: Empty updated: Apr 11, 2013 wishbone-compliant: 0 - category: Memory core created: Oct 5, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jeaander name: onfi status: Empty updated: Oct 5, 2013 wishbone-compliant: 0 - category: Processor created: Mar 25, 2012 description: "===== \n Description =====\n\nOoOPs is intended to be a higher-performance alternative to other MIPS(TM)-compatible projects on OpenCores. Many of the other CPU cores are targeted for low resource utilization and/or higher energy efficiency. OoOPs will instead target higher performance (both frequency and IPC) through more aggressive pipelining and out-of-order execution. This means that OoOPs will be more resource intensive, especially due to the nature of out-of-order architectures. To help find better performance/area operating points for the user, many structure sizes and optional features/blocks will be either parametrized or removable through defines." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - smjoshua name: oops status: Planning svn-updated: Apr 9, 2012 updated: Apr 3, 2012 wishbone-compliant: 0 - category: Communication controller created: Nov 10, 2011 description: "===== \n Description =====\n\nOpen Peer to Peer Interface, Wishbone to Aurora Bridge (OP2P).\nThis interface logic has been designed to provide a very high performance multi-lane multi-gigabit fully non-transparent (independent address spaces) peer-to-peer (no master/slave or root-complex/endpoint relationships) communiction link where the rest of the communication stack is implemented in hardware. It can be used for both cable or backplnane links. The aim of the project is to provide a network-like, high-bandwidth, flexible, serial-I/O-based replacement of originally PCI-based multi-processor and storage systems.\n The destination of a transaction is specified with a 16-bit ID which is made of a 10-bit chassys ID and a 6-bit slot-ID. For point to point cable links we can use ID=0 which means the packet is intended for the device receiving it (the link partner). The OP2P protocol supports multi-hop mesh topologies where not every card has direct conenction to every other (like in a full-mesh), and the device receiving a packet with a non-matching destination ID will forward the packet on another port to reach the inteded recipient. This is called distributed switching, no switch cards are needed in the system/network. The system or network can be backplane-based or cable-based, or a mixture of them. There are similarities with PCI-express in the way of handlindling the packets, but without the limitation of speed, number of non-transparent ports on a device and the master-slave relationships. There are also similarities with Ethernet, without the excessive software overhead and the limitations of the link-width and speed unflexibility.\n This IP core is only one port. It implements a higher (transaction) layer of the communication stack, while the lower (physical) layer is implemented inside the Xilinx Aurora interface IP (using various types of the Xilinx multi-gigabit serial transceivers) generated in the Xilinx CoreGenerator program. The OP2P interface was developed to provide a low latency, low software-overhead board-to-board communication interface. It is basically a \xE2\x80\x9CBuffer-Copy\xE2\x80\x9D interface; it copies data from a DRAM memory buffer on one board to a memory buffer on another board, initiated by a command which specifies the address locations within both the source and the target buffers. The buffers should be memory mapped within the system address spaces of the boards independently (PCI/PCIe devices). It is based on PCI-express, with certain modifications: all ports are non-transparent and peer-to-peer supports packet forwarding in indirect mesh connections without the on-board system processor\xE2\x80\x99s (usually X86 high performance processor like Intel Core-x, Xeon\xE2\x80\xA6) intervention. This interface cannot be used to replace a master-peripheral type PCI system, since it requires more intelligence in a peripheral card, and it is not compatible with the PCI Plug&Play BIOS/software, also all ports are non-transparent. The host (x86) processor does not read/write data directly from/to the OP2P port, but instead it provides a command (fill up 5 FIFOs with transaction parameters) to allow the OP2P port logic to take the data from/to the local DRAM buffer. A complete bridge/switch (FPGA chip logic) would consist of multiple OP2P ports with a local DRAM buffer, and the host (X86 processor) will have to read/write that DRAM buffer directly instead of reading/writing the ports.\n\nAbout the Xilinx Aurora Interface IP Core: \n This core is used as the physical layer logic for the OP2P interface. It implements packet frame generation/detection, flow control, error detection and link initialization. The clocking architecture used is pleisosynchronous, meaning that the reference clock signal does not have to be distributed to each device, instead they use clock compensation packets inserted into the data stream.\nElectrical Characteristics: The actual silicon hardware electrical interface is implemented using the Xilinx FPGA's built-in multi-gigabit serial transceivers. The OP2P electrical characteristics therefore are equal to the Xilinx transceiver characteristics. These parameters are documented on the chosen FPGA device's datasheets and Characterization Report documents that are all available from the Xilinx website. Xilinx normally characterizes their transceivers against interface standards like SATA/PCIe, against electrical standards like various OIF (Optical Interface Forum) CEI (Common Electrical Interface) documents, and sometimes against mediums like CAT-5/6 UTP and other cables. The different Xilinx FPGAs have different types of transceivers built-in, for example the GTP, GTX, GTH, which all have their different maximum speed capability limits. In Q4 2011 they have FPGA built-in transceivers with maximum limits of 3.1Gbit/s to 28Gbit/sec on every differential pair.\n\nLimitations:\n This code is a proof of concept only. The data bandwidth is limited, since the on-chip data buses/processing is 32-bit. The Spartan-6 (-2 speed grade) device is able to run the interface with an around 100MHz on-chip parallel bus, but since the valid PLL settings don't allow for parallel bus speed in this range, the on-chip logic runs on 75MHz with serial line rate of 1.5Gbps. On a newer 7-series FPGA (Kintex-7, Virtex-7), it would run faster. \nThis code implements the on-chip Wishbone parallel bus as a single-dword/transaction method instead of using bursts for simplicity, which actually limits the data bandwidth. Therefore production boards it will have to be implemented with burst support. The burst support has to divide the incoming/outgoing packet payload data into smaller Wishbone-bus bursts up to a maximum specified size. For example a 1 Kbytes (256 Dword) packet will be loaded on the Wishbone bus in eight consecutive 32-Dword bursts (128 Bytes). This would increase the on-chip parallel bus performance to 60-80% of the theoretical bandwidth (based on width and clock frequency) of the parallel bus. Without burst support, the real bandwidth is about 10-25% of the theoretical limit. Implementing bursts in the existing VHDL code should be simpler than the bus-width increase, although it would still require lots of changes and debugging with the ChipScopePro logic analyser.\n\nTarget Devices:\n The Xilinx Spartan-6 LXT XC6SLX45T (for a 1.5GGbit/s x2 using CAT-6-UTP), device was used for initial debugging. Theoretically the core is suitable for the series-5/6/7 FPGAs. The aurora-5.x cores have the same TRN interface which was used on the reference design. The newer version of the core only has an AXI-bus interface, which would require a partial redesign of the OP2P core. For series-7 FPGAs the Coregenerator only allows to use the latest Aurora cores, with AXI parallel-interface and 64/128-bit buses, which is incompatible with the current design of the OP2P core. For using the interface on these series-7 FPGAs we would need a 128-bit bus anyway to avoid having an on-chip performance bottleneck, and to take an advantage of the available serial I/O bandwidth with x4 serial ports. An optimal device for backplane applications could be the Xilinx Kintex XC7K355T-2FFG901 (10.3Gbit/s 4x4, for 6U VPX), or a Kintex XC7K160T-2FFG676 (10.3Gbit/s 4x1, for 3U VPX), but any Xilinx Kintex or Virtex series FPGA would be suitable.\nDependencies:\nThis design includes the aurora interface core which was generated by the Xilinx CoreGenerator. All the VHD files were copied here, including the ones from the \"Reference Design\" folder. This file is the top level source of the module, and is not generated by CoreGen. Search for all VHD files in all subfolders, then copy all.\nTwo files had to be modified:\naurora_8b10b_v5_1_reset_logic.vhd\naurora_8b10b_v5_1_example_des_modified.vhd\nThe last one has its filename and module name also modified, not only the internal logic.\n\nProject status:\n The OP2P port IP core is fully functional and was tested on a PCIe card with Xilinx Spartan-6 FPGA, using CAT-6 UTP cable at 1.5Gbit/sec. The performance of the on-chip Wishbone bus is limited due to the simplified design (no Wishbone burst transactions implemented). This will have to be improved (adding Wishbone burst support) before using the core on a product.\n\nPlease check the SVN for the source code, the reference design code and the documentation.\nIf you are planning to use this core for a product development (not a student project), then please drop me an email about it: buenos@opencores.org" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - buenos name: op2p status: FPGA proven svn-updated: Nov 17, 2011 updated: Nov 17, 2011 wishbone-compliant: 1 - category: Communication controller created: Oct 1, 2007 description: "===== \n OPB OneWire Master =====\n\nThis is an easy-to-use OneWire master peripheral for the Microblaze OPB bus.\n\nThe following functions will allow your program to access this peripheral easily:\nOneWireReset();\ndata = OneWireRead();\nOneWireWrite(data);\n\nTo install, simply unzip the file into your projects' pcores directory. The functions are in a text file in the onewire core directory.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Ease of use\n \n\n\n \n \n \n\n===== \n Status =====\n\nFully operational and tested in hardware on a Spartan 3E with a DS2432 Secure EEPROM chip." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - madscientist159 name: opb_onewire status: FPGA proven svn-updated: Mar 10, 2009 updated: Oct 9, 2007 wishbone-compliant: 0 - category: Memory core created: Feb 9, 2008 description: "===== \n Description =====\n\nThe OPB PSRAM-Controller connect a Pseudo-Staic-RAM, also named CellularRAM\xE2\x84\xA2 to the OPB-Bus. \n \n\n\n \n \n \n\n===== \n Features =====\n\nDesign\n- max. 80 Mhz Memory Clock for a Spartan-3 1500 FPGA\n- synchronous design, no DCM/DLL needed\nPerformance with micron MT45W8MW16BGX-701\n- 32-Bit Write: 3 Clock cycles\n- 32-Bit Read: 8 Clock cycles\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Design Phase done\n- Simulation Tests done\n- Real-World Tests done" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - dkoethe name: opb_psram_controller status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 16, 2008 wishbone-compliant: 0 - category: Communication controller created: Jun 2, 2010 description: "===== \n Description =====\n\nopb_usblite - opb_uartlite replacement for Xilinx Microblaze processor written in VHDL and Verilog. The opb_usblite is compatible with the USB CDC profile and works with microsoft usbser virtual comport driver (VCD).\n \n\n\n \n \n \n\n===== \n Implementation =====\n\nThe opb_usblite connects directly to the OPB bus. For users that are using the processor local bus (PLB) it is possible to add a PLB2OPB bridge. See the reference design for the Spartan 3E starter board.\n\nThere are a few generics to configure the behavior of the core.\n\n C_SYSRST : std_logic := '1'; -- enable external reset\n C_PHYMODE : std_logic := '1'; -- phy mode\n C_VENDORID : std_logic_vector(15 downto 0) := X\"1234\"; -- VID\n C_PRODUCTID : std_logic_vector(15 downto 0) := X\"5678\"; -- PID\n C_VERSIONBCD : std_logic_vector(15 downto 0) := X\"0200\"; -- device version\n C_SELFPOWERED : boolean := false; -- self or bus powered\n C_RXBUFSIZE_BITS: integer range 7 to 12 := 10; -- size of rx buf (2^10 = 1024 bytes)\n C_TXBUFSIZE_BITS: integer range 7 to 12 := 10 -- size of tx buf (2^10 = 1024 bytes)\n\nThere are six I/O signals for connecting the core to an usb transceiver, e.g USB1T11A from Fairchild Semiconductor.\nA schematic drawing in pdf format can be found here.\n\n\n\n txdp : out std_logic; -- connect to VPO\n txdn : out std_logic; -- connect to VMO/FSEO\n txoe : out std_logic; -- connect to OE\n rxd : in std_logic; -- connect to RCV\n rxdp : in std_logic; -- connect to VP\n rxdn : in std_logic -- connect to VM\n\n\nThe core consumes around 527 slices in a Spartan 3s500. In addition it also needs a 48MHz clock, easily generated by a DCM or clock generator core. It does not need to be synchronized with the processor clock. All signals crossing the clock domains are handled in the opb_usblite core. An example of a clock generator is found in the reference design.\n\n\nDevice utilization summary:\n---------------------------\n\nSelected Device : 3s500efg320-4 \n\n Number of Slices: 527 out of 4656 11% \n Number of Slice Flip Flops: 396 out of 9312 4% \n Number of 4 input LUTs: 962 out of 9312 10% \n Number used as logic: 961\n Number used as Shift registers: 1\n Number of IOs: 118\n Number of bonded IOBs: 0 out of 232 0% \n Number of BRAMs: 3 out of 20 15% \n\n\n \n\n\n \n \n \n\n===== \n Software/Drivers =====\n\nThere is a basic driver for microblaze designs included in the project. It is compatible with the drivers supplied for opb_uartlite in most aspects. In software settings in EDK just select opb_usblite as stdio. Although microsoft windows\nis shipped with drivers for usb cdc devices it is necessary to supply an inf file with usb VID and PID information. Just point to the project supplied .inf file when the pnp manager is asking for a driver. Note that the usual bit rate, handshake etc. settings are not used and have no affect to the communication with the target.\n\n ADDRESS MAP\n ===========\n RX FIFO base + $0\n TX FIFO base + $4\n CONTROL REG base + $8\n STATUS REG base + $C\n\n CONTROL REG\n ===========\n -- Write Only\n -- bit 0 Reset_TX_FIFO -- not used\n -- bit 1 Reset_RX_FIFO -- not used\n -- bit 2 Dont'Care\n -- bit 3 Dont'Care\n -- bit 4 enable_rxinterrupts\n -- bit 5 Dont'Care\n -- bit 6 enable_txinterrupts\n -- bit 7 tx_enable -- not used\n\n STATUS REG\n ==========\n -- Read Only\n -- bit 0 rx_Data_Present\n -- bit 1 rx_Buffer_Full\n -- bit 2 tx_Buffer_Empty\n -- bit 3 tx_Buffer_Full\n -- bit 4 interrupt flag\n -- bit 5 not used always '0'\n -- bit 6 online flag\n -- bit 7 suspend flag \n\n \n\n\n \n \n \n\n===== \n Misc =====\n\n\n opb_usblite is using components by Rudolf Usselmann see\n http://www.opencores.org/cores/usb_phy/\n and Joris van Rantwijk see http://www.xs4all.nl/~rjoris/fpga/usb.html\n MAKE SURE TO READ THEIR LICENSE TERMS BEFORE USING THIS IP-CORE" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rehnmaak name: opb_usblite status: FPGA proven svn-updated: Jun 9, 2010 updated: Jun 8, 2010 wishbone-compliant: 0 - category: Video controller created: Oct 9, 2007 description: "===== \n Description =====\n\nThis is an OPB-compatible VGA character display for the Spartan 3E development board, which does not contain DACs.\n\nThe core is very small, requiring only 3 BRAMs and 533 slices.\n\nAll access is through write character commands, similar to an LCD display. 3-bit color is supported, as well as inverted characters.\n\nCurrent resolution is 640x480, 75x55 characters\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Ease of use\n - Includes write string function\n - Individual characters can also be written\n- Small footprint\n \n\n\n \n \n \n\n===== \n Status =====\n\n- status1\n- status2" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - madscientist159 name: opb_vga_char_display_nodac status: FPGA proven svn-updated: Mar 10, 2009 updated: Oct 17, 2007 wishbone-compliant: 0 - category: System on Chip created: Sep 12, 2004 description: "WISHBONE and WISHBONE->OPB bus interface wrappers\">\n\n===== wishbone_and_wishbone->opb_bus_interface_wrappers\">\n OPB ->WISHBONE and WISHBONE->OPB bus interface wrappers =====\n\nWISHBONE and WISHBONE->OPB bus interface wrappers\">\n OPB Bus to WISHBONE bus and WISHBONE bus to OPB bus interface wrappers.\n\nThe Interface wrappers are provided as a plug-in for Xilinx EDK. To install, untarr the dowloadable archive in $EDK_ROOT/hw/XilinxProcessorIPLib/pcores/.\nYou have to restart XPS to see the new wrappers.\n\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs - \n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis project is Done" language: netlist license: 3-clause BSD licenselink: http://opensource.org/licenses/BSD-2-Clause maintainers: - rudi name: opb_wb_wrapper status: FPGA proven svn-updated: May 19, 2009 updated: Sep 12, 2004 wishbone-compliant: 1 - category: Processor created: Sep 11, 2006 description: "===== \n 8-bit RISC processor core based on the Vautomation uRISC =====\n\nThis is a \"clean\" reimplementation of the Vautomation uRISC processor core (aka the \"V8\", also named the Arclite core) based on ISA documentation only.\n\n\n\nIt implements the full v8 architecture with a few additions, most of which are optional:\n\n\n\n* Thirty-six basic instructions (and four new instructions)\n\n* 8-bit PSR(Program Status Register) with Zero, Carry, Negative, and Interrupt status bits, and 4 general purpose status bits.\n\n* Eight 8-bit registers, R0 though R7.\n\n* Accumulator register (R0)\n\n* A 16-bit program counter\n\n* Any two adjacent registers may be paired to create a 16-bit index register.\n\n* Three basic addressing modes; addressed, indexed, and indexed with offset\n\n\n\nThe design adds a few new features, which can be enabled through generics:\n\n* An optional auto-increment for indexed addressing modes (\"LDX R4++\" is equivalent to \"LDX R4 ; UPP R4\" )\n\n* A new branching instruction, DBNZ (Decrement, and Branch if Not Zero)\n\n* A new math instruction, MUL, uses on-board multipliers.\n\n* The interrupt mask can now be set with the new instructions SMSK and GMSK\n\n\n\nThe Open8 is being designed to work optimally in newer FPGA architectures. It assumes 2 clocks for memory and register file latency.\n\n\n\nThis design has now fielded as a test stimulus controller hosted in an Altera 3C40, not once - but twice. It's primarily serving as a data acquisition controller / packet generator in those designs, and has performed trouble-free for well over a year. Additionally, as part of the test stimulus system, the Open8 is responsible for synchronizing output frequencies with the device under test. Due to the nature of these calculations, a 16-bit ALU/co-processor was written to \"hardware accelerate\" common math functions, rather than have to write emulations in assembly. This ALU has been included in the SVN repository. The Open8, and its ALU coprocessor, use about 2400 LE's in the FPGA.\n\n\n\nIt has also been fielded in several non-shipping test instruments and small emulators hosted in Altera 3C16's, where it performs a variety of tasks. I am presently looking to use it as a packet processor to bridge between a PC and a custom digital waveform generator design.\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Model is written in VHDL ('93)\n\n- Simple RISC architecture and instruction set. All instructions fit in a single byte, with either 1 or 2 operands.\n\n- 16-bit PC / address allows for 64kB of directly accessible memory (can be expanded with paging)\n\n- Moderate number of general purpose registers\n\n + Eight byte-wide registers.\n\n + Any two registers may be paired as (Rn+1:Rn) to create an index register\n + R0 acts an the accumulator\n- 8 interrupts, 1 NMI, 7 maskable. Interrupt controller is built into the core.\n + Interrupt controller keeps track of interrupt order and priority\n + Interrupt mask is controllable through two new instructions, SMSK and GMSK.\n- Reasonably small gate-count, with strong fMax in \"low-end\" devices.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Complete! The CPU has been synthesized and tested on an Altera DE2 board (Cyclone II 2C35).\n\n\n\n- [UPDATE: the Hi-Tech compiler is no longer available.] Hi-Tech has now made their C compiler for the v8/Arclite architecture available as a demo. Note, the Open8 implements instructions that aren't in the stock v8/Arc core, so some of the generated code could probably be accelerated with a bit of hand optimization. (the DBNZ Rn instruction won't be used in loops for example)\n\n\n\n- Source VHDL for the Open8 can be retrieved from either the \"download\" link, or from the SVN repository, above.\n\n\n\n- An assembly language reference manual has been added to the source repository (March 20, 2011)\n\n\n\n- A port of GNU binutils is in the SVN repository. This is a beta release, and has not yet been incorporated into the official binutils source base. Please report any bugs here, not at the binutils bugzilla.\n\n\n\n- The Open8 is getting its first real use in a test set. It is implemented alongside a number of hardware accelerators, relegating it to primarily moving things around in memory, but so far it has performed well. There are some minor alterations, including an option to replace BRK with WAI - or WAit_for_Interrupt. When selected, there is no longer a true NOP available, but the ability to halt the processor waiting for an interrupt is a useful capability.\n\n\n\n- BRK_Implements_WAI is tested, and shown to work correctly. An updated processor model has been checked in to SVN.\n\n\n\n- The Open 8 has now successfully been fielded! The core in question used the new features recently checked in, and has worked remarkably well as a supervisory processor in a larger FPGA design. The whole system features a lot of hardware accelerators, including a 16-bit, bus-addressed ALU to handle some of the math, but using the Open8 has allowed the design to be a lot more flexible.\n\n\n\n- A port of the GNU C/C++ compiler is underway, with no release date yet targeted. The calling conventions are still under design, and there will likely be changes to the instruction set to make it easier for the compiler to generate efficient code.\n\n\n\n- A few bugs were found while regression testing an updated version of the Open8 processor core. Apparently the vectored interrupt controller didn't always obey priority. Also, it appears that auto-incrementing indexed loads and stores didn't complete execution of the UPP command. These have been both corrected.\n\n\n\n- The ALU control signals were pipelined to improve fMax on smaller parts. This allowed a design targeting an Altera Cyclone 3C16 to go from ~60MHz to ~132MHz (without trying, the target frequency was 100MHz). Unfortunately, this also means that all math instructions (Opcodes 0 though 15 and GMSK) now take take 3 clock cycles to execute instead of one, like the MUL and UPP instructions. The only other instruction to suffer increased latency was the DBNZ instruction, which requires the status register to update before continuing. All other instructions retain their existing latencies. Unfortunately, this does imply that code should be regression tested on the model, as the total execution time in clock cycles will increase.\n\n\n\n- As part of the update, a lot of superfluous code was stripped out. The model should be a lot easier to understand." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - khays - jshamlet name: open8_urisc status: FPGA proven svn-updated: Sep 26, 2013 updated: Sep 23, 2013 wishbone-compliant: 0 - category: Memory core created: Jan 31, 2010 description: "===== \n Description =====\n\nOpen FreeList Readme\n\n\nGeneral Description\n\n\n\n\tThe Open FreeList module is used to manage a set of variable sized packets inside a fixed memory block.\n\tThe memory block is partitioned into fixed sized chunks and each packet uses one or more chunks.\n\tThe module offers three possible actions:\n\t\n\t\tWrite a packet into memory\n\t\tRead a packet from memory\n\t\tRelease a packet\n\t\n\n\n\nUsing the Module\n\n===== Parameters =====\n\n\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\tName\n\t\t\tDescription\n\t\t\tUnit\n\t\t\tDefault Value\n\t\t\n\t\t\n\t\t\tRAM_W\n\t\t\tMemory block width\n\t\t\tbits\n\t\t\t128\n\t\t\n\t\t\n\t\t\tRAM_E\n\t\t\tMemory block extra data\n\t\t\tbits\n\t\t\t0\n\t\t\n\t\t\n\t\t\tRAM_S\n\t\t\tMemory block size\n\t\t\tKBytes\n\t\t\t64\n\t\t\n\t\t\n\t\t\tCHK_S\n\t\t\tChunk size\n\t\t\tBytes\n\t\t\t128\n\t\t\n\t\t\n\t\t\tRAM_TYPE\n\t\t\tMemory block type\n\t\t\tstring\n\t\t\t\"MRAM\"\n\t\t\n\t\t\n\t\t\tFL_AEMPTY_LVL\n\t\t\tFreeList almost empty level\n\t\t\t#\n\t\t\t2\n\t\t\n\t\n\n===== Interface =====\n\n\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\tName\n\t\t\tDirection\n\t\t\tWidth\n\t\t\tDescription\n\t\t\n\t\t\n\t\t\tglobal signals\n\t\t\n\t\t\n\t\t\treset_n\n\t\t\tinput\n\t\t\t1\n\t\t\tasync reset (active low)\n\t\t\n\t\t\n\t\t\tclk\n\t\t\tinput\n\t\t\t1\n\t\t\tclock\n\t\t\t\n\t\t\n\t\t\twrite interface\n\t\t\n\t\t\n\t\t\tfl_q\n\t\t\toutput\n\t\t\tclog(#_of_chunks)\n\t\t\tfirst chunk number for a new packet.capture this value and use it to read/release the packet\n\t\t\n\t\t\n\t\t\tfl_aempty\n\t\t\toutput\n\t\t\t1\n\t\t\tindicates that the number of chunks reached the almost empty level\n\t\t\n\t\t\n\t\t\tfl_empty\n\t\t\toutput\n\t\t\t1\n\t\t\tno more chunks available. do not write any more\n\t\t\n\t\t\n\t\t\twren\n\t\t\tinput\n\t\t\t1\n\t\t\twrite pulse. writes the data on din into the memory block\n\t\t\n\t\t\n\t\t\tdin\n\t\t\tinput\n\t\t\tRAM_W+RAM_E\n\t\t\tdata to write into memory block\n\t\t\n\t\t\n\t\t\teop\n\t\t\tinput\n\t\t\t1\n\t\t\tend-of-packet indication. assert on last write of packet\n\t\t\n\t\t\n\t\t\tread interface\n\t\t\n\t\t\n\t\t\tchunk_num\n\t\t\tinput\n\t\t\tclog(#_of_chunks)\n\t\t\tfirst chunk in a packet to be read or released\n\t\t\n\t\t\n\t\t\tload_req\n\t\t\tinput\n\t\t\t1\n\t\t\trequest to read a packet starting at chunk number 'chunk_num'\n\t\t\n\t\t\n\t\t\trel_req\n\t\t\tinput\n\t\t\t1\n\t\t\trequest to release a packet starting at chunk number 'chunk_num'.also required after a packet is read\n\t\t\n\t\t\n\t\t\tload_rel_ack\n\t\t\toutput\n\t\t\t1\n\t\t\tacknowledge a read or release request\n\t\t\n\t\t\n\t\t\trden\n\t\t\tinput\n\t\t\t1\n\t\t\tread request. data on 'dout' is valid one clock later\n\t\t\n\t\t\n\t\t\tdout\n\t\t\toutput\n\t\t\tRAM_W+RAM_E\n\t\t\tdata read from memory block\n\t\t\n\t\n\n===== Operations =====\n\nWrite\n\t\n\n\n\tTo write a packet, do the following:\n\t\n\t\tmake sure 'fl_empty' is de-asserted\n\t\tcapture the value on 'fl_q'. it will be used later to reference this packet\n\t\twhile 'fl_empty' is not asserted do:\n\t\t\n\t\t\twrite the next data line in 'din'\n\t\t\tassert 'wren'\n\t\t\ton the last line of the packet, assert 'eop' as well\n\t\t\n\t\n\t\n\n\n\tRead\n\t\n\n\n\tTo read a packet that was previously written, do the following:\n\t\n\t\tset 'chunk_num' to the value of the first chunk in the packet.\n\t\tthis value was obtained from 'fl_q' when the packet was written\n\t\tassert 'load_req'\n\t\twhen 'load_rel_ack' is asserted, for each line of data do:\n\t\t\n\t\t\tassert 'rden'\n\t\t\tcapture 'dout' one cycle later\n\t\t\n\t\n\tTo determine the last line of data, you could:\n\t\n\t\tstore the packet length in an external structure\n\t\tuse the extra bits in the memory block to hold an indication such as end-of-packet\n\t\n\t\n\n\n\t\n\n\n\tNote that the 'eop' indication that is written in the write operation is not available on a read operation.\n\t\n\n\n\t\n\n\n\tImportant: after a read is complete, a release operation must be explicitly performed.\n\tThere is no need to set the 'chunk_num' value after a read operation.\n\tThe chunks are released when the packet is read, but the last chunk requires an explicit release operation. \n\t\n\n\n\tRelease\n\t\n\nA packet can be released under two circumstances:\n\t\n\t\twhen a read is complete, a release must be issued\n\t\tif a packet is not needed, it can be released without reading it\n\t\n\tTo release a packet, do the following:\n\t\n\t\tset 'chunk_num' to the first chunk of the packet (not required after a read)\n\t\tassert 'rel_req'\n\t\twhen 'load_rel_ack' is asserted, you are done\n\t\n\n===== Memories =====\n\nThree memories are used in this module:\n\t\n\t\tram - dual port memory. two cycles to read\n\t\tfree_list - single clock lookahead FIFO\n\t\tlink_list - dual port memory. two cycles to read\n\t\n\tThe target architecture is Altera Sratix. There should be matching memory blocks in other architectures.\n\t\n\n\n\t\n\n\n\n\n\t\n\n\n\tCode: Alex Manash - Crescendo Networks\n\tDocs: Amit Fridman - Crescendo Networks" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - amif2000 name: open_free_list status: Beta svn-updated: Feb 16, 2010 updated: Feb 16, 2010 wishbone-compliant: 0 - category: Processor created: Mar 26, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: opencpu32 status: Planning svn-updated: Apr 19, 2012 updated: Mar 31, 2012 wishbone-compliant: 0 - category: System on Chip created: Mar 27, 2007 description: "===== \n Description =====\n\nThe OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire was developed by Stephen Craven specifically for configurable array research. As such, certain features of the MicroBlaze are not currently implemented. The OpenFire lacks interrupts, exceptions, debugging facilities, and Local Memory Bus and On-chip Peripheral Bus interfaces. These functions may be added in the future. The page of the author is: http://www.ccm.ece.vt.edu/~scraven/openfire.html\n\nThe version posted in opencores is an improved version of the Openfire I'm working on with the author permission and the goal is to have a functional SoC with a 32 bit RISC CPU and a set of peripherals ready to be used by several projects.\n\nThe initial target board / FPGA are the Spartan3 starter board with XC3S200. Althought I'm using plain verilog some borrowed peripherals (mainly from the Xilinx application notes) are Xilinx specific. In the near future vendor independent peripherals will be added.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- OpenFIRE CPU\n - Features can be enabled/disabled with `defines\n - ISA compatible with Microblaze\n - FSL link\n - Interrupts\n - Exceptions (invalid opcode and alignment)\n - Special registers support (not completed)\n - Memory interface\n - Dissasembler for simulation of CPU with applications\n\n- OpenFIRE SOC\n - All parameters are configurable via `defines\n - Peripherals selectables via `defines and mapped in memory\n - VGA (640x480) : mapped into SRAM\n - Up to 2 UART\n - PROM loader (as FPGA PROM is not 100% full you can add programs and data at the end of the FPGA bitstream)\n - board GPIO (7seg displays, switches and push buttons)\n - External memory controller (SRAM)\n - SPI / I2C\n-\n \n\n\n \n \n \n\n===== \n Status =====\n\n- OpenFIRE CPU\n - ISA almost completed\n - MSR bits (IE, BIP, EIP, etc..)\n - Special register handling 50% (mfs, mts)\n - Pending: div and barrel shift\n - Memory access code rewritten in order to allow multicycle read/writes for INS/DATA ports\n - Unaligned data read/write removed from cpu (moved to memory handler at soc level).\n\n- OpenFIRE SOC\n - Work in progress in several peripherals\n\n- Software\n - Boot monitor in 2Kbytes of FPGA BlockRAM with minimal monitor capabilities (dump/write/fill, etc..) and able to load/execute programs from UART(Motorola S records) or PROM (binary file)\n - Port of FreeRTOS in progress (Microblaze port is not working due to different peripherals and minimal differences in MSR)\n - Port of lwIP TCP/IP stack in progress (with slip interface at the moment)\n - low level driver for uart input/output used by gnu libc (printf, etc..)\n - vga library (display texts and limited drawing). work in progress.\n-\n \n\n\n \n \n \n\n===== \n Links =====\n\n- Microblaze toolchain:\n - Source code / linux binary: http://www.petalogix.com/resources/downloads/mb-gcc\n - Windows binary: http://www.xilant.com/downloads/mb_gnu_8_2.zip\n\n- Microblaze uClinux: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux\n\n- Microblaze documentation: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=micro_blaze\n \n\n\n \n \n \n\n===== \n Deployment #1 =====\n\nInstructions to install/configure working testbench for Spartan3 Starter Kit:\n\nPlease note that all the helper utilities (bin2xx.c) are compiled only for Windows; you may need to recompile they if using linux.\n\n1. Create an ISE project with all the verilog files (except openfire_template_bootram.v). Adjust openfire_define.v as needed.\n2. Include constraint file: sp3_devboard.ucf\n3. Make the monc program with Microblaze toolchain (cd sw/monc and make then a file monc.v will be generated). Include it in the project openfire_soc\n3. Generate a bitstream for the openfire_soc.v module\n4. Burn the bitstream to the FPGA prom.\n5. Connect a serial port to SP3SK board (115200-n-8-1). Push \"reset\" (reset is pushbutton #4) a welcome and a prompt should appear.\n\nNow you have the openfire cpu/soc with a set of peripherals and a monitor loaded in block ram.\n\n6. Make the low level library (sw/lib then make)\n7. Make FreeRTOS library (sw/freertos then make)\n8. Make vga library (sw/vga then make) and the vga example (vga.srec)\n\nNow you are ready to make programs and load them into SRAM. In order to load a program you can use load.bat to upload Motorola SREC dumps. Previously configure COM1 port (mode com1:115200,n,8,1). When the program is loaded you must connect with a terminal to SP3SK board and type \"x 04000000\"\n\nGood luck\nAntonio" language: Verilog license: MIT (Expat) licenselink: http://opensource.org/licenses/MIT maintainers: - toni32 name: openfire2 status: FPGA proven svn-updated: Mar 10, 2009 updated: Jun 11, 2012 wishbone-compliant: 0 - category: Processor created: Aug 24, 2007 description: "===== \n Description =====\n\nThe OpenFire Processor Core is an open-source, binary-compatible MicroBlaze clone written in Verilog. Binary-compatible means exactly that - a binary compiled for a MicroBlaze embedded system will run on an OpenFire that is placed in the same embedded system. The OpenFire was designed for use in SCMP (Single Chip, Multiple Processor) and ASIP (Application Specific Instruction-set Processor) research. The OpenFire has an advantage in these areas as the entire HDL source is available, creating ultimate flexibility.\n\nThe OpenFire Processor Core was written by Stephen Craven, a PhD student at Virginia Tech. It has been most recently upgraded by Alex Marschner, a Masters student at the same university. The OpenFire Processor Core is released under the MIT license.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- binary compatibility with the Xilinx MicroBlaze\n- full FSL (Fast Simplex Link) support\n - 8 master ports (output)\n - 8 slave ports (input)\n- full OPB (On-chip Peripheral Bus) support\n - Data-side OPB support allows access to Xilinx OPB peripherals.\n - Instruction-side OPB support allows programs to run from off-chip memory.\n- The latency of the LMB (Local Memory Bus) is removed by using a direct BRAM memory.\n- The OpenFire can be used in the EDK, although programming is still done manually.\n- 50MHz operation\n \n\n\n \n \n \n\n===== \n Project Status =====\n\n- 2007.12.12 OpenFire v0.6a is released\n \n\n\n \n \n \n\n===== \n Future Work =====\n\n- Add XMD debug support\n- Add PLB support\n- improve memory-mapping design\n- move more #define values to module parameters (where appropriate)\n- improve speed to 100MHz +\n- improve integration with the Xilinx EDK\n - allow software creation from within the EDK\n - force the EDK to recognize the OpenFire as a processor" language: Verilog license: MIT (Expat) licenselink: http://opensource.org/licenses/MIT maintainers: - cutullus - scraven name: openfire_core status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 13, 2007 wishbone-compliant: 0 - category: Arithmetic core created: Apr 17, 2010 description: "===== \n Description =====\n\nFree and open source double precision Floating Point Unit (FPU).\n\nThe openFPU64 currently features:\n- double precision\n - Addition/Subtraction\n - Multiplication\n - rounding (to nearest even)\n - subnormals/denormals\n\n - validated against IEEE754\n\t - Compatible with Avalon Bus\n\t - Wishbone interface will be provided soon\n\nNew algorithms can be added easily, just modify the code marked\n with ADD_ALGORITHMS_HERE\nEverything marked with FUTURE is not yet implemented,\n but already added for easier transition.\nTested on CycloneII and Cyclone III FPGAs.\nIf any questions arise, don't hesitate to contact me.\n\n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Performance =====\n\nAdd/Sub have an fmax of 112Mhz on a Cyclone II.\nMultiply has a fmax of 70Mhz on a Cyclone II.\n\nA faster implementation of Multiply will be provided soon.\n(faster in regard to fmax, with only 2 clock cycles more delay) \n \n\n\n \n \n \n\n===== \n Testsuites =====\n\nDue to the size and a 'bug' in the websvn which got the tar.bz2 corrupted I removed the testsuites from svn.\n\nI uploaded them to\nhttp://www.hs-augsburg.de/~phuewe/openFPU64/tests.tar.bz2\nplease download them from there.\n\nAfter downloading them, untar them to tests/\n\nFrom openfpu64 root directory you can now create the testsuites using \nmake TESTSUITENAME_testsuite\ne.g.\nmake add_testsuite\n\nYou can then compile the openfpu64_tb.vhd with modelsim or ghdl.\n\nIf you use ghdl you can generate the executable testbench by simply running make.\n\n\n\nThe testsuites contain 45k testcases for add/sub each and 90k for multiply." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - bro name: openfpu64 status: Beta svn-updated: Jun 2, 2010 updated: May 7, 2010 wishbone-compliant: 0 - category: Memory core created: Sep 30, 2014 description: "===== \n Description =====\n\n\n\nopenHMC is an open-source project developed by the Computer Architecture Group (CAG) at the University of Heidelberg in Germany. It is a vendor-agnostic, AXI-4 compliant Hybrid Memory Cube (HMC) controller that can be parameterized to different data-widths, external lane-width requirements, and clock speeds depending on speed and area requirements.\n\nThe main objective of developing the HMC controller is to lower the barrier for others to experiment with the HMC, without the risks of using commercial solutions.\n\nFor more information check the official openHMC documentation, available here on opencores.org or on the official project website openHMC Home\n \n\n\n \n \n \n\n===== \n The openHMC controller =====\n\nThe openHMC controller is presented as a high-level block diagram in the figure below. The asynchronous input and output FIFOs allow the user to access the memory controller from a different clock domain. On the transceiver side, a registered output holds the data reordered on a lane-by-lane basis; allowing seamless integration with any transceiver types. A register-file provides access to control and monitor the operation of the memory controller.\n\n\n\n\n***** Features *****\n\nThe openHMC controller implements the following features as described in the HMC specification Rev 2.0:\n\n- Full link-training, sleep mode, and link retraining \n- 16Byte up to 128Byte read and write (posted and non-posted) transactions\n- Posted and non-posted bit-write and atomic requests\n- Mode Read and Write\n- Full packet flow control\n- Packet integrity checks (sequence number, packet length, CRC)\n- Full link retry" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - juko name: openhmc status: FPGA proven svn-updated: Feb 6, 2015 updated: Jan 2, 2015 wishbone-compliant: 0 - category: Testing / Verification created: Jun 1, 2010 description: "===== \n Description =====\n\nThe Open JTAG project has as objetive to give to the public domain a complete hardware and software JTAG project. Based on a simple hardware board, composed basically by a FT245 USB front end and an Altera EPM570 MAX II CPLD, this board is capable to output TCK signal at 24 MHZ using macro-instructions sent from the computer end.\n\nIt is not as others JTAG projects based on the PC parallel port: Open JTAG project uses the USB channel (still not at high speed) to communicate with the internal CPLD, sending macro-instruction as fastest as possible.\n\nYou can visit the official page of the project at http://www.openjtag.org/" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rmileca name: openjtag-project status: Beta svn-updated: Jun 27, 2010 updated: Oct 22, 2010 wishbone-compliant: 0 - alternate-download: https://github.com/linuxbest/lzs/archive/master.zip category: Arithmetic core created: Feb 13, 2013 description: "===== \n Description =====\n\nPlease download source code from:\n\nhttps://github.com/linuxbest/lzs" homepage: https://github.com/linuxbest/lzs language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - linuxbest name: openlzs status: Stable updated: Feb 18, 2013 wishbone-compliant: 0 - category: Processor created: Jun 30, 2009 description: "===== =====\n\n\n\n \n \n Introduction\n The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is\n compatible with Texas Instruments' MSP430 microcontroller\n family and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.\n \n The core comes with some peripherals (16x16 Hardware Multiplier, Watchdog,\n GPIO, TimerA, generic templates) and most notably with a two-wire Serial\n Debug Interface supporting the MSPGCC GNU Debugger (GDB) for in-system\n software debugging. \n \n While being fully FPGA friendly, this design is also particularly\n suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements).\n In a nutshell, the openMSP430 brings with it:\n \n Low area (8k-Gates), without hidden extra infrastructure overhead (memory backbone, IRQ controller and watchdog timer are already included).\n Excellent code density.\n Good performances.\n Build-in power and clock managment options.\n Multiple times Silicon Proven.\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n\nDownload\nDesign\nThe complete tar archive of the project can be downloaded here (OpenCores account required).\n\nThe following SVN command can be run from a console (or GUI):\n\n\n\n\n\n\n\n\n\n\n\tsvn export http://opencores.org/ocsvn/openmsp430/openmsp430/trunk/ openmsp430\n\n\n\n\nChangeLog\n\n The Core's ChangeLog lists the CPU updates.\n The Tools' ChangeLog lists the Software development tools updates.\n Subscribe to the following RSS feed to keep yourself informed about ALL updates.\n\n\nDocumentationBeing fully compatible with the original MSP430 architecture, TI's official documentation is applicable: SLAU049F.PDF\nIn addition, the openMSP430 online documentation is also available in pdf.\n\n\nFeatures & Limitations\n\n===== Features =====\n\n\n\tCore:\n\t\n Full instruction set support.\n Interrupts: IRQs (x14, x30 or x62), NMI (x1).\n Low Power Modes (LPMx).\n Configurable memory size for both program and data.\n Scalable peripheral address space.\n Two-wire Serial Debug Interface (I2C or UART based) with GDB support (Nexus class 3, w/o trace).\n FPGA friendly (option for single clock domain, no clock gate).\n ASIC friendly (options for full power & clock management support).\n \n\n Small size (Xilinx: 1650 LUTs / Altera: 1550 LEs / ASIC: 8k gates).\n\t\n\t\n\t\t\n\tPeripherals:\n\t\n 16x16 Hardware Multiplier.\n Basic Clock Module.\n Watchdog.\n Timer A (FPGA only).\n GPIOs (FPGA only).\n Templates for 8 and 16 bit peripherals.\n\t\n\t\n\n\n===== Limitations =====\n\n\n\tCore:\n\t\n Instructions can't be executed from the data memory.\n\t\n\t\n\t\n\n\nLinks\nFollow on Google+:\n\n \n\nDiscussion group:\n\n\t\n \n \n \n \n \n Subscribe to openMSP430\n \n \n \n Email: \n \n \n \n \n Visit this group\n \n \n \n\nDevelopment has been performed using the following freely available (excellent) tools:\n\n\tIcarus Verilog : Verilog simulator.\n\tGTKWave Analyzer : Waveform viewer.\n\tMSPGCC : GCC toolchain for the Texas Instruments MSP430 MCUs.\n\tISE WebPACK : Xilinx's free FPGA synthesis tool.\n\nA few MSP430 links:\n\n\tWikipedia: MSP430\n\tTI: MSP430x1xx Family User's Guide\n TI: MSP430 Competitive Benchmarking\n \n\n\tTI: a list of available MSP430 Open Source projects out there on the web today.\n\n\nLegal informationMSP430 is a trademark of Texas Instruments,\nInc. This project is not affiliated in any way with Texas Instruments.\nAll other product names are trademarks or registered trademarks of\ntheir respective owners." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: [] name: openmsp430 status: ASIC and FPGA proven svn-updated: Jan 21, 2015 updated: May 10, 2015 wishbone-compliant: 0 - category: Prototype board created: Apr 11, 2008 description: "===== \n Description =====\n\nOpensource OpenRisc Development Board. All CADsoft Eagle design files available to recreate the board using EagleLite, a freeware PCB design tool. Uses the largest Cyclone 2 device available in a QFP package, thus allowing larger RTL designs to be ported, and at the same time allowing easier PCB design and board assembly. Board design is double sided, and can be manufactured using low cost batch PCB services. But despite only being double layer, it has an almost continuous bottom side ground plane.\nA complete system consists of two separate boards;\n- Main FPGA board that contains the FPGA, SDRAM, regulators, Santa Cruz expansion header, and Support board expansion header. \n- Support board containing SD card slot, SPI flash, C8051, fpgaConfig header, JTAG header, OpenRisc debug header and RS-232 DB9 connector.\nA complete FPGA project is available for the board set. This includes a minimal OR1K\n, SDRAM memory controller, UART peripheral, and SD memory interface. Simulation is possible using Icarus Verilog simulator, and the design can be compiled under Altera Quartus.\nSoftware is available to demonstrate copying a software image file from SD flash memory to SDRAM, and then executing the copied image.\nSee fpgaConfig project for details of configuring FPGA from SD flash memory:\n\nYou can use this project as a basis for a compact OpenRisc implementation. A complete OpenRisc implementation requires just an FPGA, SDRAM, microSD card, and a tiny C8051.\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Eagle design files compatible with free Eagle Lite \n- Simple PCBs can be manufactured using batch PCB services.\n- No BGA devices\n- Large FPGA (20,000 logic cell Altera Cyclone 2)\n- Single 16MByte x32 SDRAM\n- Santa Cruz expansion header.\n- Support for fpgaConfig \n- Support for SD/MMC controller \n \n\n\n \n \n \n\n===== \n Status =====\n\n- OR1K running on board, and able to copy software image from SD flash TO SDRAM, and execute.\n- Support for USB and SD/SPI flash Santa Cruz daughter cards.\n- Software projects for SDRAM memory test, SD memory test, USB loop back test, and USB mouse emulation.\n- Full Icarus simulation of complete OpenRISC system, including software\n\n \n\n\n \n \n \n\n===== \n IMAGE: dscn1315.jpg =====\n\nFILE: dscn1315.jpg\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n Development Kit =====\n\nComplete Development kit available.\nContents:\n\n- FPGA Main Board\n- FPGA Support Board\n- USB2Flash programming adapter and USB cable\n- Connecting ribbon cables\n- Wall wart 5V power supply\n- RS-232 cable\n- CD-ROM \n\nEverything is included to allow you to start running right out of the box. And it's all open source! The CD-ROM includes several tools such as Icarus Verilog, GTKwave, Cygwin, OpenRISC tool chain, and of course example projects which you can compile into hardware using Altera Quartus, or simulate using the Icarus simulator. \n \n\n\n \n \n \n\n===== \n News =====\n\nNow supports i2Slave. Everything you need to test the i2cSlave IP core. An on board connector supports the Aardvark I2C Host Adapter. Complete Altera hardware project files, documentation, and Aardvark scripts and test software are available." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - sfielding name: openriscdevboard status: Stable svn-updated: Mar 10, 2009 updated: Dec 29, 2008 wishbone-compliant: 0 - category: Library created: Jul 31, 2007 description: "===== \n openVeriFLA - FPGA logic analyzer =====\n\nopenVeriFLA is an FPGA integrated logic analyzer.\nIt can be used for in-circuit debugging and verification\nof the FPGA based applications.\nThe FPGA part is written in verilog. The PC part \nis written in java and is platform independent.\n Being simple and well documented, the openVeriFLA library\nis well suited for didactical purposes and academic use.\n\n For more information, please unzip the project archive\nand read the reference manual.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- on-the-fly capture, graphical display, testing automation\n \n\n\n \n \n \n\n===== \n Status =====\n\n- ready to use\n \n\n\n \n \n \n\n===== \n IMAGE: verifla_keyboard_protocol_verification_50procent.jpg =====\n\nFILE: verifla_keyboard_protocol_verification_50procent.jpg\nDESCRIPTION: The FPGA capture of a keyboard controller signals" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - laurentiuduca name: openverifla status: FPGA proven svn-updated: Mar 10, 2009 updated: Mar 3, 2008 wishbone-compliant: 0 - category: Other created: Nov 26, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - freakngoat name: opl3_20 status: Empty updated: Nov 27, 2014 wishbone-compliant: 0 - category: System on Chip created: Aug 4, 2010 description: "===== \n Description =====\n\nThe Open Tiled Multicore SoC is a scalable manycore platform based on compute, memory and I/O tiles. Such tiles are connected by a Network-on-Chip (NoC).\n\nSuch platforms are based on standard open source components, such as the OpenRISC processor and FPGA-NoC. \n \n\n\n \n \n \n\n===== \n Planned Output =====\n\nThe main element will be a python program, that creates diverse simulators and implementations (see below). The parameters are the NoC size and the instances and layout of compute tiles, memory tiles and i/o tiles.\n \n\n\n \n \n \n\n===== \n Implementation and Simulator Abstraction Levels =====\n\n- Implementation (HDL): NoC: Verilog, Compute Tile: Verilog\n- Register Transfer Level (RTL): NoC: Verilated, Compute Tile: Verilated\n- Cycle Accurate (CA):NoC: Verilated, Compute Tile: Verilated\n- Approximately-Timed (TLM-AT):NoC: Verilated, Wishbone TLM Adapter, Compute Tile: or1ksim, TLM Models" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - wallento name: optimsoc status: Empty updated: Aug 13, 2010 wishbone-compliant: 1 - category: Processor created: Oct 22, 2010 description: "===== \n Description =====\n\nThe project is based on OpenCores' OR1200 project.\n\nThe core is now hyper pipelined. It is a technique to multiply the functionality \nof a design by adding registers (called pipeline stage registers) to the core logic \nin order to multiply its functionality. If you are interested in the technology, go to www.cloudx.cc\n\nThe functional behavior of the OR1200 remains the same, the hyper pipelined\nversion is used when multiple OR1200 cores (2, 3, ...) are instantiated in the \nsame design (multicores). \n\nThe main benefit is the multiplication of the core's functionality by only \nimplementing registers. This leads to a reduced size compared to the \nindividual instantiation of the cores. This is a great advantage for ASICs \nbut obviously very attractive for FPGAs with their already existing registers. \n\nAnother issue is the performance of the resulting hyper pipelined OR1200 core. \nThe pipeline stage registers are timing driven placed to partition the critical \npath into equal parts, which leads to an almost multiplied performance of the \ndesign. The timing is optimized for a Virtex 5 device from Xilinx. \n\nThe modifications are done on RTL, so that the project can be used in an \nRTL based testbench. \n\nThe project shows the modified RTL code with 2, 3 and 4 times multiplied \nfunctionality. It is delivered with a testbench and a detailed documentation. \n\n\nEnjoy ..." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tobil name: or1200_hp status: Stable svn-updated: Nov 12, 2010 updated: Aug 6, 2013 wishbone-compliant: 0 - category: System on Chip created: Mar 16, 2009 description: "===== \n Overview =====\n\nThis project is an example of using OpenRISC on an Terasic DE1 development board. UBoot has been ported. The old ecos 2.0 has been ported to ecos 3.0. The adv_debug_sys unit was integrated but not tested." language: Verilog license: unknown maintainers: - qaztronic name: or1200_soc status: FPGA proven svn-updated: Mar 29, 2011 updated: Feb 27, 2010 wishbone-compliant: 1 - category: Other created: Sep 23, 2004 description: "===== =====\n\n\n \n\n===== =====\n\n\n \n\n===== \n Description =====\n\nThis is a Tcl/Tk script to configure OpenRisc 1200 options. \nI use it to configure the core and I think it could be usefull for other people.\nThe look is very similar to LEON graphicall configuration tool.\n\nFor comments, feedback, patches or whatever you want javier.castillo@urjc.es\nThis tool is provided under the GPL license Universidad Rey Juan Carlos (Spain)\nwww.gdhwsw.urjc.es" language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - jcastillo name: or1200gct status: Stable svn-updated: Mar 10, 2009 updated: Apr 9, 2010 wishbone-compliant: 0 - category: Processor created: Apr 23, 2004 description: "===== \n Status =====\n\nCPU passes simple tests. Verification is not complete.\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis is a new implementation of the OpenRisc 1000 architecture in the Confluence language.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- OpenRisc 1000 32-bit CPU\n - ORBIS32-I instructions implemented\n - Exception handling partially implemented\n - C test harness runs S-record programs\n- Cache\n - Not implemented\n- MMU\n - not implemented\n- Other stuff\n - not implemented\n \n \n\n\n \n \n \n\n===== \n News =====\n\n16 June 04 Upgraded to Confluence 0.9.0" language: Confluence license: 3-clause BSD licenselink: http://opensource.org/licenses/BSD-2-Clause maintainers: - kenr name: or1k-cf status: Alpha svn-updated: Mar 10, 2009 updated: Jun 17, 2004 wishbone-compliant: 0 - category: Processor created: Sep 25, 2001 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tac2 - julius - rdaddio - jeremybennett - sfielding - unneback - olof - rherveille - yannv - jonibo - stekern - filepang - skrzyp - paknick - tadejm - antygan - pgavin - gscrivano name: or1k status: ASIC and FPGA proven svn-updated: Feb 24, 2011 updated: Mar 1, 2012 wishbone-compliant: 1 - category: System on Chip created: May 1, 2014 description: "===== \n Description =====\n\nThis project is based on the OR1K2 SoC. \n\nIt is enhanced using System Hyper Pipelining (SHP) technology. You can achieve a higher performance on a given area and you can run up to 16 different OR1K2 cores at the same time.\n \n\n\n \n \n \n\n===== \n Schematic =====\n\n\n \n\n\n \n \n \n\n===== \n Board =====\n\nIt is mapped on a Low Cost FPGA Arduino board. The board has a Spartan 6, (LX16), HS-USB interface, 2 independent SDRAM interfaces to 512MBit / 64MBit SDRAM at 166MHz.\n \n\n\n \n \n \n\n===== \n Board Pic =====\n\n\n \n\n\n \n \n \n\n===== \n Crowdfunding =====\n\nIf you would like to support my Indiegogo crowdfunding campaign for this board, please check it out till 29th June 2014:\n\nhttps://www.indiegogo.com/projects/arduissimo-multicore-arduino-for-more-arduino-and-raspberry-pi-interfacing#home\n\nCheers, Tobias" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tobil name: or1k2_shp_soc status: Empty updated: May 9, 2014 wishbone-compliant: 0 - category: Arithmetic core created: May 9, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lmkjim name: or1k_20110509 status: Empty updated: May 9, 2011 wishbone-compliant: 0 - category: System on Chip created: Nov 16, 2009 description: "===== \n Description =====\n\nThis project is to implement a SoC of using OpenRISC 1200 and many open source IP cores from opencores.org on Nios II Embedded Evaluation Kit (Cyclone III Edition).\n\n\n\n\n\nThe system architecture is shown as below\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nHardware:\n\n32-bit Openrisc 1200 with 8k cache and mmu enable (done)\n16KB on-chip RAM for boot loader (done)\nWishbone-to-Altera DDR/DDRII SDRAM core bridge (done)\nAdvanced Debug System core. Debugging via Altera Virtual JTAG (done)\nEthernet 10/100 MAC (done)\nUART 16550 core (done)\nSD/MMC core (done)\nGPIO core (done)\nVGA/LCD core + Touch screen (TBD)\nI2S core for audio codec (TBD)\nPS2 core for keyboard (TBD)\nMEM I/F core for FlashRAM and on-board SRAM (TBD)\n\n\nSoftware:\n\nLinux 2.6.35 (successes boot up on this dev kit, but need to enhance)\nBusyBox 1.7.5 (boot passed with above kernel)\nSD card boot loader (done)\nEthernet driver (done, web server up)\nGDB debugging supported (done)\nBlock device driver for SD/MMC core (working)\nFramebuffer driver for VGA/LCD core (TBD)\nTouch screen driver (TBD)\nSound card driver for I2S audio codec (TBD)\nPS2 keyboard driver for PS2 core (TBD)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - xianfeng name: or1k_soc_on_altera_embedded_dev_kit status: Mature svn-updated: Sep 8, 2010 updated: May 30, 2012 wishbone-compliant: 1 - category: Processor created: Jul 12, 2010 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback - julius - rherveille - jeremybennett name: or2k status: Planning svn-updated: Jul 26, 2010 updated: Jul 14, 2010 wishbone-compliant: 0 - category: System on Chip created: Aug 31, 2011 description: "===== \n Description =====\n\nThe goal of ORPSoC is to provide a complete System On Chip based on the OpenRISC CPU.\nThe current version ORPSoCv2 is hosted in the openrisc tree. It can be checked out with\nsvn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2\nThe documentation for ORPSoC is currently spread out in the OpenRISC project,\nbut a good starting point is the OpenRISC wiki, especially this page http://opencores.org/or1k/ORPSoC\nThe bugtracker for the ORPSoC project is found in OpenCores bugzila:\nhttp://bugzilla.opencores.org/buglist.cgi?product=OpenRISC&component=ORPSoC\n\n\nA new version, orpsocv3 has just started planning.\nSome ideas are gathered here http://opencores.org/or1k/ORPSoCv3\nMore information is yet to come" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - olof - julius - stekern name: orpsoc status: Empty updated: Aug 31, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Mar 22, 2012 description: "===== \n Description =====\n\nThe ORSoC Graphics Accelerator can:\nDraw Lines.\nDraw Filled or Textured Rectangles.\nDraw Filled, Interpolated or Textured Triangles.\nDraw Filled Quadratic B\xC3\xA9zier Curves.\nWrite Text with Bitmap Fonts or Vector Fonts.\nDraw Alphablended shapes.\nDraw Colorkeyed images. \nDraw 3D meshes with support for depth buffer.\nTransform points (scaling & rotation of triangles and vector fonts).\n\nThe ORSoC GFX have support for the following formats:\nSupport for .TTF fonts.\nSupport for .OBJ files for 3D meshes.\nSupport for .bmp, .png, .jpg, etc. (all formats supported by SDL_image). \n\nObserve that this core does not drive a display, we recommend you to pair this core with the Enhanced LCD/VGA Driver core.\n\nTested & Verified on the Spartan 6 based ATLYS board.\nContains testbenches based on iVerilog and GTKWave.\nThe implementation takes ~10 000 Slice Luts.\n\nTo make the development of applications easier there is a software implementation of the graphics accelerator.\nThis software implementation uses the same drivers as the hardware implementation. While its not an exact emulation of the hardware, its very close. The ORGFX simulator is implemented with LibSDL." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - maiden - Orka - bigsascha3 name: orsoc_graphics_accelerator status: FPGA proven svn-updated: Jun 7, 2012 updated: May 5, 2013 wishbone-compliant: 1 - category: Other created: Sep 18, 2012 description: "===== \n Description =====\n\nSee video on YouTube: http://www.youtube.com/watch?v=UsYXRPRBsmk" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - olegodintsov name: oscilloscope status: Beta svn-updated: May 20, 2014 updated: Sep 18, 2012 wishbone-compliant: 0 - category: Communication controller created: Jun 28, 2010 description: "===== \n Description =====\n\nOpen Source Documented Verilog UART\n \n\n\n \n \n \n\n===== \n Purpose =====\n\nThis module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. All the open source UART modules I found were difficult to interface with, usually due to being more clever than I wanted them to be, and had poor documentation for their interfaces. They were also generally written in VHDL, which since I've never written VHDL made it a little difficult to read to work out the interfacing issues for myself. The frustration of finding such a simple component so hard to use prompted the decision to create my own, and document it for beginners like myself.\n\nI hope that this module will be documented to a better standard than most I've come across. Please send me a message if you have trouble understanding it. Confusing documentation should be treated as much like a bug as a flaw in the code - please feel free to file one. Improvements are also welcome!\n\nThis is released under the MIT licence, which freely permits use in both open source and closed source / commercial projects.\n \n\n\n \n \n \n\n===== \n What would I use this for? =====\n\nA UART is a useful component for controlling asynchronous (without a separate clock line) serial buses. It can be used via a level converter to talk to the RS232 serial port of a computer. This is not, however, the only application. It can also be used in a circuit to communicate with peripherals, or over other types of cables (such at RS485 with a differential driver) to connect to other circuits over quite long distances.\n \n\n\n \n \n \n\n===== \n I/O Standards, Compatability =====\n\nThis follows standard UART signalling methods with the following properties:\n\n* Expects to send and receive data as 8 data bits, no parity bits.\n* Default baud rate is 9600 with a 50MHz clock. This is configurable.\n* Samples values roughly in the middle of each bit (may drift slightly).\n* Sends and receives least significant bit first.\n* Expects to receive at least 1 stop bit. Will not check for more, but won't fail if more are present either.\n* Transmits 2 stop bits.\n* Tested connecting over a computer serial port at standard rates up to 57600 baud.\n \n\n\n \n \n \n\n===== \n Speeds, Recommended Testing =====\n\nThe maximum speed this can operate at depends on the clock rate used, the accuracy of the UART at the other end and connection quality. At the moment I'd recommend testing this at a low baud rate such as 9600 baud, then scaling it up until you encounter errors. For example, using a 50MHz clock I encounter quite a few errors at 115200 baud. I will be working to increase stability and allow higher rates in the near future.\n \n\n\n \n \n \n\n===== \n Source Control =====\n\nThe source for this project is maintained using Git ( http://git-scm.com ). The latest source can be obtained by installing Git and running:\n\ngit clone git://goddard.net.nz/osdvu\n\nThe source can be browsed online at:\n\nhttp://goddard.net.nz/cgi-bin/gitweb.cgi?p=osdvu.git\n\nThe OpenCores SVN will be updated with each packaged release, but does not contain interim development." language: Verilog license: MIT licenselink: http://opensource.org/licenses/MIT maintainers: - pruby name: osdvu status: FPGA proven svn-updated: Jun 29, 2010 updated: Dec 16, 2013 wishbone-compliant: 0 - category: Prototype board created: Oct 23, 2010 description: "===== \n Short Description =====\n\nMinMax game tree search with alpha-beta pruning implemented in FPGA.\n\nRules and heuristics implemented for Reversi/Othello game. The system is capable of analyzing ~5M game states/second @50MHz. (no selective search).\n\nRTL design Verilog 2001 compliant. \nVGA output, pushbuttons input (for playing), using Spartan3E Starter Kit board.\n\n\n\n \n\n\n \n \n \n\n===== \n General Features =====\n\n Transition from a current game state to another is done in 1cc. \n Determining all possible transitions from a game state to another is also done in 1cc.\n Evaluation of one game state is done in 1cc. \n The heuristic evaluation function consists of pattern matching between current game state configuration and empirically determined board patterns (about 100 patterns), all comparisons are done concurrently. \n Capable of analyzing ~5M game states/second, compared to ~0.2M game states/second obtained with a software version running on P4 processor. \n MinMax with alpha/beta pruning, but no selective search. \n Maximum frequency is 50MHz. \n All RTLs are Verilog. Some RTL's are python generated. \n VGA output of the board game. \n RS232 transmission: AI-time in clock cycles, number of game positions analyzed. \n Number of Slices: 3292 out of 4656 (70%). \n Number of BRAMs: 8 out of 20 (40%). \n \n\n\n \n \n \n\n===== \n Description =====\n\nA Game Tree is a directed graph whose nodes are states of a game. A game state is a configuration of the game on a specific time. The complete game tree of a game consists of all possible game states, from the initial game position to the every possible end-game position, containing all transitions from a game state. Of course, when analyzing a game you cannot look at every game state to choose the best move using reasonable time resources, so this problem is intractable.\n\nAnyway, AI for such games are based on searching only a partial game tree starting from the current game position and going a few plies deep, than based on a function that will heuristically evaluate the game state, you will pick a good, hopefully the best, move. Generally, increasing the search depth will improve your chance to pick the best move. (In rare cases this is not true).\n\nThe well-known algorithm to search a game tree and choosing the best move, is MinMax. This search method will start from a game state considered initial game state and expand it to generate all possible next-states, and then for every new state will generate the next game states and so on, until a specific depth is reached. When a leaf-node is reached, we can consider that to be an end-game state (because we cannot see deeper), and we will evaluate it. Evaluation of a game state should return a score reflecting the win-lose quantity. Then, going backwards in game tree, we have to maximize or minimize this value. For example, for your point of view, you will have to maximize your wining score and minimize mine. So from a game state you will pick the move which is best for you and worst for me. When it's mine turn, I will maximize my winning score and so on. MinMax will consider playing both roles, alternating. This mathematical model works very well for turn based games like chess, reversi/othello, checkers, etc.\n\nAn improvement for this search is alpha-beta pruning. The difference is that will not search all branches from the partial game tree. This improvement is also implemented in this system." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - marius_mtm name: othellogame status: Design done svn-updated: Dec 6, 2011 updated: Dec 6, 2011 wishbone-compliant: 0 - category: Processor created: Jul 26, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - joaocarlos name: ourisc status: Alpha svn-updated: Aug 29, 2013 updated: Jul 26, 2013 wishbone-compliant: 0 - category: Other created: Mar 13, 2003 description: "===== \n Description =====\n\n\n \n\n===== \n Status =====\n\nI just started reading the Ogg Vorbis spec. and I'm seeing if other people are interested." language: '' license: unknown maintainers: - bkorsedal name: ovcodec status: Empty svn-updated: Mar 10, 2009 updated: Apr 19, 2010 wishbone-compliant: 0 - category: System on Module created: Nov 7, 2014 description: "===== \n Description =====\n\nSystem on Module based on Xilinx ZYNQ SoC that combines dual Core ARM Cortex-A9 CPU cores with Programmable Logic in single device. This open hardware System on Module is designed to be very low cost, for this purpose large external DDR memory is not included, neither are any PHY devices (USB/Ethernet) on the module.\n \n\n\n \n \n \n\n===== \n Features =====\n\n* Real Open Source(tm): All production and support files released to public!\n* Low cost 6 layer PCB technology, no buried or blind vias\n* Small form factor, 40x75mm - smaller than credit card\n* Single 3.3V supply\n* Xilinx ZYNQ XC7Z7010 (can be upgraded with XC7Z7020)\n** Dual ARM Cortex A9 Core\n** Artix(tm) FPGA Programmable Logic\n** Microblaze(tm) Soft Processors can be implemented in fabric with free Vivado tools\n** own soft-processors and peripheral cores can be implemented in FPGA\n* 16 to 256MB NOR Flash (max 32Mbyte usable as linear XiP memory for the CPU's)\n* one push-button that works as reset or user button (uses MSP430 as \"button controller\")\n* 3 LED's (connected to: CPU GPIO, FPGA, button controller)\n* SMD DIP switch to select boot mode either from SD Card or SPI Flash\n* up to 54 user I/O (in all 3 connectors: 42 + 8 + 4)\n* \"cloud ready\" when used with \"Electric Imp\" smart Wifi SD Card\n* iSDIO Wifi Card support (to be confirmed!)\n \n\n\n \n \n \n\n===== \n Connectivity =====\n\n* Bluetooth BT/BLE with either onboard Antenna or U.fl connector\n* one 12 pin Pmod Slot: 8 I/O pins connect to Zync SoC MIO pins\n* one 8 pin Pmod I2C Slot: 4 I/O pins connect to Zync SoC MIO pins\n* 50 pin IDC style connector, can be fitted as pin header, max 42 I/O\n* one SD/SDIO slot, can be used for SD card, iSDIO Wifi or electric imp wifi card\n* one micro SD card slot\n* HS USB 2.0 Host/Device/OTG can be implemented (need ULPI PHY)\n* up to two Ethernet interfaces (need RMII or MII PHY)\n \n\n\n \n \n \n\n===== \n Form Factor =====\n\nCustom form factor: 40x75mm This form factor was choosen from following constraints:\n* Should fit largest commonly used IDC connector (50 Pin) with 100 mils spacing\n* Should fit standard SD Card socket\n* Must be room for BGA IC sized 19x19 at least\nFrom the above constraints the minimal board size is about 40x75 mm" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - antti name: ozoma status: Empty updated: Dec 16, 2014 wishbone-compliant: 0 - category: Processor created: Oct 28, 2013 description: "===== \n Description =====\n\nThis project implements a single cycle core for the emulation of PIC16C5x microcomputers. The core requires the integrator to implement the I/O registers and program memory. The core provides these standard base architecture peripherals: timer, pre-scaler and clock multiplexer, and watchdog timer. The core provides selects and read/write strobes for the three I/O ports and the corresponding TRIS registers.\n\nThe timer peripheral supports all normal functions of the timer 0 in the PIC16C5x family of 12-bit instruction processors. A fully synchronous architecture for the clock source logic and the pre-scaler has been selected. This facilitates the integration of the core with FPGAs. The watchdog timer length is parameterized, so the period can be determined by the application and integrator. \n\nPA[2] is implemented, and the 2-deep stack is 12 bits in width. Thus, program memory can be extended to 4096 x 12 instead of the standard of 2048 x 12.\n\nThe core uses inference for all memory, and should be easily ported to any FPGA family that supports LUT or Block RAMs.\n\nThe core has been integrated into a Spartan 3A XC3S50A-4VQ100I FPGA using its the three block RAMs as a 4096 x 12 program memory. All instructions, except program branches, execute in a single memory cycle. Thus, as provided the core has been demonstrated in this application supporting a memory cycle rate greater than 60 MHz.\n \n\n\n \n \n \n\n===== \n Tool Set Compatibility =====\n\nThis core has been used with MPLAB and the CCS C compiler tools. A utility for converting from Intel Hex to Xilinx MEM files has been provided as part of the M16C5x SoC project (found here on OpenCores).\n \n\n\n \n \n \n\n===== \n Synthesis/PAR Results =====\n\nWhen used in an implementation of a soft-core processor, the P16C5x exhibits the following results for synthesis in an XC3S50A-4VQ100I FPGA. As a module of the soft-core processor, the P16C5x core occupies 389 slices, utilizes 202 slice registers, and 488 LUTs.\n\n\n\n ModulePartition\n Slices\n Slice Reg\n LUTs\n LUTRAM\n BRAM\n MULT18X18\n BUFG\n DCM\n\n\n\n [-] M16C5x\n \n 166/1089\n 26/608\n 73/1265\n 0/211\n 3/3\n 0/0\n 1/4\n 0/1\n\n\n \xC2\xA0\xC2\xA0[-] CPU\n \n 233/389\n 116/202\n 306/488\n 40/40\n 0/0\n 0/0\n 0/0\n 0/0\n\n\n \xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0ALU\n \n 80/80\n 13/13\n 112/112\n 0/0\n 0/0\n 0/0\n 0/0\n 0/0\n\n\n \xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0IDEC\n \n 76/76\n 73/73\n 70/70\n 0/0\n 0/0\n 0/0\n 0/0\n 0/0\n\n\n \xC2\xA0\xC2\xA0[+] ClkGen\n \n 10/21\n 12/25\n 5/8\n 1/1\n 0/0\n 0/0\n 1/3\n 0/1\n\n\n \xC2\xA0\xC2\xA0[+] SPI\n \n 8/93\n 8/75\n 0/135\n 0/34\n 0/0\n 0/0\n 0/0\n 0/0\n\n\n \xC2\xA0\xC2\xA0[+] UART\n \n 0/420\n 0/280\n 0/561\n 0/136\n 0/0\n 0/0\n 0/0\n 0/0\n\n\n\n\nThe timing constraints used to achieve the best results with the -4 speed grade of the XC3S50A FPGA are shown in the following table:\n\n\nTiming Constraints\n\n\n Met\n Constraint\n Check\n Worst Case Slack\n Best Case Achievable\n Timing Errors\n Timing Score\n\n\n\n Yes\n TS_Clk = PERIOD TIMEGRP \"Clk\" 16.666 ns HIGH 50%\n SETUP/HOLD\n 0.011ns/0.651ns\n 16.655ns\n 0/0\n 0/0\n\n\n Yes\n TS_SPI_SCK = PERIOD TIMEGRP \"SPI_SCK\" 15 ns HIGH 50%\n SETUP/HOLD\n 0.108ns/1.026ns\n 14.784ns\n 0/0\n 0/0\n\n\n Yes\n TS_Clk_UART = PERIOD TIMEGRP \"Clk_UART\" 10 ns HIGH 50%\n SETUP/HOLD\n 0.513ns/0.680ns\n 9.487ns\n 0/0\n 0/0\n\n\n\n\n\nWith the lower speed grade part, the P16C5x will operate at just over 60 MHz. The single cycle operation of this core provides a soft-core processor that delivers nearly 60 MIPs. (Note: jumps, calls, and branches require two cycles, but all other instructions are single cycle instructions.)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelA name: p16c5x status: FPGA proven svn-updated: Nov 1, 2013 updated: Apr 20, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jan 17, 2012 description: "===== \n Description =====\n\nThe Tate Bilinear Pairing core is specially designed for running Tate bilinear pairing algorithm for hyperelliptic curve $y^2=x^3-x+1$ defined over $GF(3^m)$, where $m=97$ and $GF(3^m)$ is defined by $x^97+x^12+2$.\n\nGenerally speaking, The Tate bilinear pairing algorithm is a transformation that takes two points on an elliptic curve and outputs a nonzero element in the extension field $GF(3^{6m})$. Details of the algorithm is in the document. \n\nThe core is written in Verilog 2001, and it is carefully optimized for FPGA. For example, input signals are synchronous and sampled at the rising edge of the clock. Output signals are driven by flip-flops, and not directly connected to input signals by combinational logic. There is no latch, and only one clock domain in entire core.\n\nThe core runs at 131MHz on the Xilinx Virtex-4 XC4VLX200-11FF1513 FPGA board. It computes one Tate bilinear pairing within 75,839 clock cycles, which is 0.76 milliseconds @ 100MHz clock.\n\nThe core uses 49205(27%) LUTs, 35381(39%) slices, 31425(17%) flip-flops of the XC4VLX200-11FF1513 FPGA board. \n\nThe core is an open source Tate Bilinear Pairing core, under the license of LGPL version 3.\n \n\n\n \n \n \n\n===== \n Technical specification =====\n\nSpecification rev 0.1\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Tate bilinear pairing for hyper-elliptic curve $y^2=x^3-x+1$\n- The irreducible polynomial is $x^97+x^12+2$\n- Input length is 4*194 bits and output length is 1164 bits\n- Fully synchronous design \n- Fully synthesize-able\n- ONLY ONE clock domain in entire core\n- NO latch\n- All output signals are buffered\n- Vendor independent code\n \n\n\n \n \n \n\n===== \n Status =====\n\n- The core is ready and available in Verilog from OpenCores svn\n\n \n\n\n \n \n \n\n===== \n TODO =====\n\n- Increase the degree of the irreducible polynomial for improving the security level\n- Use a better algorithm for the final exponentiation in $GF(3^{6m})$\n \n\n\n \n \n \n\n===== \n Donation =====\n\nIf this project has helped you, please consider donating an FPGA to Homer Hsing (Xilinx FPGA is preferred). To donate him will help him develop more valuable project, and is to help you." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: pairing status: FPGA proven svn-updated: Mar 4, 2012 updated: Apr 18, 2012 wishbone-compliant: 0 - category: Communication controller created: Dec 12, 2013 description: "===== \n Description =====\n\nA device that convert a PC parallel port to serial , then serial to parallel. It can transport all signals of the PC parallel port into a single wire. Moreover, the data wire is intended to be a fiber optic in the final form of the project.\n \n\n\n \n \n \n\n===== \n Overview =====\n\nProject idea :\n\n\n\n\n\nI would like to show you how I control my CNC equipment (which is usually controlled by a PC parallel port) with a single wire using a special FPGA device.\n\n\n\n\n\nThe FPGA device serialize the control signals from the parallel port , transport the data through a single wire , then deserialize the data at arrival.\n\n\n\n\n\nThis is the close view of the data wire (white color). The other wire (Green) is reference 0V.\n\n\n\n \n\n\n \n \n \n\n===== \n SUBD 25 socket =====\n\nParallel port SUBD-25 pin with controls (s0-s11) , input (i0,i4)\n\n\n\n\n\n\n\n\nThe 25 pin SUBD-25 socket is as follow :\n12 control signals S0-S11\n5 input signals I0-I4\n\n\n\n\n\n\nThe function of the control signals are either :\ndigital signals (RESET,ENABLE, RELAY)\nstepper motor signals (STEP and DIR) of each of 4 axis X,Y,Z,A\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Frame data format =====\n\n\n\n\n\n\nThe frame delimiter is 1.5 bit duration and is the overhead that add to payload of each frame.\nThe receiver can easily detect the frame delimiter pattern as well as each bit \"0\" or \"1\" of the frame.\n\n\n\n\n\n\n200.000 frames approx. are transmitted each second and this update frequency is ok for normal digital signals like clear, enable , relay control.\nIt is ok also for variable signals in the range 1000-3000Hz like PWM speed control.\n\n\n \n\n\n\nBut it is not enough for stepper motor control signals (STEP and DIR) . I will talk more about that in the next paragraph.\n\n\n\n \n\n\n \n \n \n\n===== \n STEP and DIR =====\n\nLets explain how a CNC stepper motor controller works\n\n\n\n\n\n\nThe controller count rising edges of the STEP signal. At each step edge, the controller sample the DIR signal and advance motor in the direction of DIR.\n\n\n\n\n\n\nThe STEP and DIR signals cannot be transmitted on the serial link like normal control signals , because they are registered pulse signals.\n\n\n\n\n\n\nThe serializer , in that case incorporate a 1-bit step counter and a dir latch . The Serializer transmit the number of step (modulo 2) + the DIR value on the most recent step edge.\n\n\n\n\n\n\nThe deserializer will compare the number of step of each frame with the previous frame and allow/disallow a pulse on the corresponding output.\n\n\n\n\n\n\nFortunately the serializer OR deserializer fit into a single XC9572XL CPLD . With 4 STEP+DIR signal pair.\n\n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Transmitter =====\n\n\n \n\n\n \n \n \n\n===== \n Receiver =====\n\n\n \n\n\n \n \n \n\n===== \n Bill of material =====\n\nXC9572XL Xilinx CPLD (1 for transmitter + 1 for receiver)\n50Mhz 3.3V CMOS oscillator\nPLR/PLT133-T7 Everlight electronic fiber optic modules\nAudio (SPDIF) fiber optic cable\n \n\n\n \n \n \n\n===== \n Perspective =====\n\nserial to parallel and Parallel to serial fiber optic PCB module including 5V to 3.3V IO buffer.\n\n\n\nDec 27 2013 ===>> Finished product (Work as expected)\n\n\n\n \n\n\n \n \n \n\n===== \n Bidirectionnal interface =====\n\nBoards with XC95144XL CPLD , implementing bidirectionnal link\n\n\n\n\n\n\n\n\n\n\nFinished jan/24/2014 work as expected\n \n\n\n \n \n \n\n===== \n Application =====\n\nAn application : A replacement card for a laser engraver (model K40) , with stepper motor driver.\nThe single fiber optic input, provide a complete electric insulation between the PC and the laser engraver. \n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Application 2 =====\n\nStepper motor PWM controller with single fiber optic input.\n\n\n\n\nAssembled (jan 6 2014)\n\n\n\nWorking video : http://youtu.be/0FW8_HkqzNM\n \n\n\n \n \n \n\n===== \n Application 3 =====\n\nHigh current PWM stepper board (4A /coil) with 6 DMOS full bridge ( 2 per motor) + fiber optic interface and 4th axis extension\n\n\n\n\nFinished - Transformed to 4 axis - added discharge diodes - Changed XC9572 to XC95144 - Added separate power setting for each axis\n\n\n\nUSB interface for CNC on fiber optic" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - chipmaker78 name: parallel_io_through_fiber status: FPGA proven svn-updated: Dec 14, 2013 updated: Apr 28, 2014 wishbone-compliant: 0 - category: ECC core created: May 19, 2011 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jfcastano name: parallel_reed_solomon status: Empty updated: May 25, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Jul 30, 2014 description: "===== \n Description =====\n\nThis is a behavioral module for parallel scrambler/descrambler.\nThere are RTL scrambler modules available, the purpose of this project is to built a code that is easier to understand and more flexible for reconfiguration. The code is synthesize-able, and should not cost more than RTL modules." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - sparkish name: parallel_scrambler status: FPGA proven svn-updated: Jul 31, 2014 updated: Jul 31, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Oct 4, 2010 description: "===== \n Description =====\n\nthe aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where number of entries = N, can be configured at compile time and also the width = M of each entry.\n\nthe design idea based on binary tree structure, where there are Log_2(N) levels in the tree, the best values of N where \n Log_2(N) = integer numbers like N = ( 4, 8, 16, 32, 64,...) where Log_2(N) = {2, 3, 4, 5, ...}. but to support general values of N like 29 the design will be Log_2(29)+1 which Log_2(32) where the values 30,31,32 is padded with zero's. for the width of each value the best is the even numbers but in case of odd the width is incremented by 1 and the LSB is = '0'.\n\n\n \n\n\n \n \n \n\n===== \n Files description =====\n\n\n \n File name\n description\n \n \n basic_size.vhd\n Define N = size of the data set, M which the WIDTH of each of Value\n \n\n basic_component.vhd\n Define all the component of the design , no need to change it\n \n\n parallel_find_top.vhd\n the top level file of the design\n \n\n mux_sel.vhd\n compare and select the value of maximum, no need to change it\n \n\n Ripple.vhd\n build the compare function based on ripple , no need to change it\n \n\n Result.vhd\n build the select the answer , no need to change it(but here is possible to change from maximum and minimum, i will make this configurable)\n \n\n\n carry_cell_NAND.vhd\n basic cell of the compare based on NAND gates,no need to change it \n \n\n carry_cell_NOR.vhd\n basic cell of the compare based on NOR gates,no need to change it" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - atalla name: parallel_search_for_maximum_weight status: Design done svn-updated: Oct 7, 2010 updated: Oct 5, 2010 wishbone-compliant: 0 - category: Other created: Jul 10, 2009 description: "===== \n Description =====\n\nCRC Generator is a command-line application that generates Verilog or VHDL code for a parallel CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The CRC can be custom or protocol specific, for example PCI Express, USB5, USB16, 802.3, SATA. \xC2\xA0 The code is written in C and is cross-platform compatible\n\xC2\xA0 There is an online version of the tool at OutputLogic.com\nIt's more convenient to access, but the online tool is slower to generate the code for CRC with large data and polynomial widths." language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - evgeni name: parallelcrcgen status: Stable svn-updated: May 1, 2011 updated: Jul 30, 2014 wishbone-compliant: 0 - category: Testing / Verification created: Sep 21, 2011 description: "===== \n Description =====\n\nThis is a video pattern generator which can be used for testing video displays. It currently supports four patterns; horizontal lines, vertical lines, moving horizontal lines, and moving vertical lines. It sends out 1 pixel every clock cycle and forms the pattern on the fly using counters. This module has been used sucessfully to test a Camera Link serializer, SDXC Card video streamer and video rotator." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lfmunoz name: patterngen status: Beta svn-updated: Sep 21, 2011 updated: Jun 12, 2013 wishbone-compliant: 0 - category: Processor created: Jan 1, 2003 description: "===== \n Description =====\n\nThis project implements an 8 bit controller that is compatible with Atmel's AVR architecture, using VHDL (Very High speed integrated circuits Hardware Description Language). \n\npAVR is not a specific controller of the AVR family, but rather a maximally featured AVR. It is configurable enough to be able to simulate most AVR family controllers. \nThe goal was to obtain an AVR processor that is as powerful as possible (in terms of MIPS), with a work budget of about 6 months*man.\npAVR is about 3x faster than the original core, if built with the same technology.\n\nThe sources are modularized. They are written starting from a set of common-sense conventions (the process splitting strategy, signals naming, etc)., so that pAVR is quite an easily maintainable design. A comprehensive documentation is provided.\n \nExtensive testing was carried out. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- 6 pipeline stages \n- 1 clock/instruction for most instructions \n- estimated clock frequency: ~50 MHz & 0.5 um; assuming that Atmel's core runs at 15 MHz & 0.5 um. That's ~3x Atmel original core's performance. \n- estimated MIPS at 50 MHz: 28 MIPS (typical), 50 MIPS (peak). That's ~3x Atmel original core's performance. At 15 MHz, Atmel's core has 10 MIPS typical, and 15 MIPS peak. \n- CPI (clocks per instruction): 1.7 clocks/instruction (typical), 1 clock/instruction (peak). That's ~0.75x (typical), 1.00x (peak) Atmel original core's performance. \n- up to 32 interrupt sources. Each interrupt has programmable priority and jump address.\n- heavily parameterized design that permits flexible costumization\n- pAVR architecture is rather computational-friendly than control-friendly. Jumps, branches, skips, calls and returns are relatively expansive in terms of clocks. A branch prediction scheme and a smarter return procedure might be considered as upgrades. \n \n\n\n \n \n \n\n===== \n Status =====\n\nSummer 2002: project done.\n\nNovember 2003: Stefan Kristiansson found a skips-related bug. It's fixed from version 0.33. Thanks Stefan! \nA new version is on its way. It's not fully tested tet. Hopefully I'll have time to upload it into an FPGA, and run some heavy weight programs, such as a C compiler.\nI am using Xilinx tools: the WebPack free synthesis software, and a Spartan 3 board from NU Horizons.\nIf you synthesize pAVR and think it would be useful to share your experience with others, you're very welcome to post your results here, in the newly created synthesis page. Just email me at doru@opencores.org. You'll be helping pAVR getting more and more reliable. Thanks.\n\nAutumn 2005: bugs discovered. Changed status from \"Stable\" to \"Alpha\". Don't know when I'll have time to debug it :(\n \n\n\n \n \n \n\n===== \n Downloads =====\n\nFor the latest version check here, or my web site. Note: pAVR's CVS repository is not updated - it contains the ancient version 0.32. I don't plan to use CVS much. Thus, take care to get the latest version from the downloads page, not from CVS repository." language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - doru name: pavr status: Alpha svn-updated: Mar 10, 2009 updated: Jul 1, 2009 wishbone-compliant: 0 - category: Communication controller created: Mar 12, 2011 description: "===== \n Description =====\n\nOpen-source implementation of a versatile UDP/IP core for FPGAs.\n\nC/C++ Software library for configuring the core and transmitting standard C types like characters, integers, floats and doubles.\n\nHardware interface for transmitting standard C types like characters, integers, floats and doubles.\n\nThe UDP/IP core can transmit and receive data to and from any PC. The only requirement is the use of the configuration function provided by the software library in order to initialize an internal lookup table." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - NikosAl name: pc_fpga_com status: Stable svn-updated: May 10, 2011 updated: Mar 7, 2014 wishbone-compliant: 0 - category: Prototype board created: Dec 19, 2005 description: "===== \n A small versatile pci board, using Spartan-II at 200k gates. =====\n\nThe v1.0 of board is builded, tested with opencores pci core, its state is functional.\n \n\n\n \n \n \n\n===== \n Features =====\n\nv 1.0 feautures:\n- PCI interface fully working with opencore pci project.\n- I/O pins routed externaly to an external connector\n- JTAG header, and small xilinx eeprom for holding the configuration.\n- Jumper select local eeprom or external download or debug.\n - Project aviable in gerber for manufacturing.\n - .ucf aviable specificaly for use with ISE.\n - Schematic aviable in pdf for description of the board.\nv 2.0b feautures [To be Come]:\n - Soon, as in-house prototype line will be upgraded.\n - Bigger chip, projected use Spartan-III 1500/2000 BGA.\n - More I/O pins with daughter card posibility expansion.\n - SD card support, onboard flash, one I2C flash and 2x16bit wide SDRAM @100Mhz.\n - TI high speed A/D chip [~200MS/s]with 2x analog input, analog level controled with OPA via i2c.\n - One more additional FPGA chip Spartan-III 50k gates for math computing of A/D signal.\n\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nV1.0 Status:\n\n- Prototype manufactured in-house.\n- Electricaly tested, passed noise or voltage stability issues.\n- PCI Core syntesed, tested with smal gpio application using a linux driver.\n- Not tested for full PCI compliance, speed or other edge parameter.\n\nV2.0 Status\n- Project finished, no prototype board executed yet.\n- Soon.\n\n For people interested in board aquisition it is posible to manufacture few pieces at low cost, please contact author, requests accepted only for Eastern Europe.\n \n FILES upload in progress, must gather all of tham and scan some photos about the board, patience please ;-) \n\n \n\n\n \n \n \n\n===== \n IMAGE: PCI-Board.jpg =====\n\nFILE: PCI-Board.jpg\nDESCRIPTION: Board v1.0 Photo" language: board schematic license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - rezso name: pci-board status: Mature svn-updated: Mar 10, 2009 updated: Dec 20, 2005 wishbone-compliant: 0 - category: System controller created: Sep 25, 2001 description: '' language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - mihad - tadejm name: pci status: Stable svn-updated: Mar 10, 2009 updated: Jul 4, 2006 wishbone-compliant: 1 - category: System controller created: Apr 29, 2005 description: "===== \n Description =====\n\nThe PCI32tLite IP core provides the funtionality of a PCI TARGET. The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC's in ALTERA CYCLONE II FPGA).\n\nWhisbone databus size and endianess configurable: \"BIG\"/\"LITTLE\",32/16/8 bits.\n\nPCI memory or I/O map configurable.\n\nUses BAR0 register; occupies 32Mbytes on PCI memory map or 512Bytes on PCI I/O map.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nTested on HW:\n\n- ALTERA MAXII Kit.\n- XILINX Raggedstone1 board.\n- Other custom HW.\n\nPCI32TLITE_OC_HOWTO. Document to evaluate the PCI32TLITE IP Core creating \"maxii_uart\" project:\n\n - Project to create a UART 16550 PCI peripheral using IP Cores from www.opencores.com: \n - PCI32TLITE_OC(Peio Azkarate)\n - A_VHDL_16550_UART(Howard LeFrevre)\n - GH_VHDL_LIBRARY(George Huber and Howard LeFrevre) \n - Permits easy evaluation of the IP on HW.\n - Using PCI32TLITE_OC UART with LINUX serial standard driver.\n\n\n \n\n\n \n \n \n\n===== \n Releases =====\n\nR02 2007-09-19:\n\n- \"intb\" and \"serr\" signals not defined as TRI. They have to be defined Opendrain in the FPGA (externally to the IP Core).\n- Small changes due to onalib.vhd improvement.\n- Removed TIMEOUT. Added wb_rty_i for Target termination with RETRY.\n- Support Burst Cicles.\n- Add Whisbone data bus configuration generics: WBSIZE and WBENDIAN\n- Add wb_adr_o(1..0) signals.\n- wb_dat_i,wb_dat_o,wb_sel_o size depends on WBSIZE.\n- Advice: Change WB to/from PCI databus routing for \"BIG\"/16 WB configuration and DWORD PCI transactions (DWORD is not recomended when WB 16 configuration).\n\n\nR03 2008-06-16:\n\n- PCI32TLITE_OC_HOWTO Document added and maxii_uart project\n- Add \"1BARIO\" configuration option for BARS generic.\n- fix bug with WBENDIAN generic in pciwbsequ.\n- Change PCI Burts to WB traslation behavior.\n- Add \"classcode\" generic.\n- Change BAR0 reset state to \"0\".\n- Fix pcidmux bug for LITTLE/8 configuration.\n\n\nR04 Next release.Not ready yet.\n\n- Add \"pci_\" prefix to PCI Bus signals names.\n- Change \"rst\" signal name to \"pci_rst\". And change from active High to active Low. Allowing straight-forward connection of the PCI32TLITE Core to PCI bus (without inverter on rst).\n- Add PCI Can Controller project. Uses PCI32TLITE (Peio Azkarate) and CAN (Igor Mohor) IP Cores from Opencores.\n- Add Linux driver for PCI Can Controller project.\n- Add basic Linux driver for PCI32TLITE IP Core.\n- Some suggestion or wishes contact me. Thanks." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - peio name: pci32tlite_oc status: FPGA proven svn-updated: Apr 23, 2009 updated: Aug 24, 2009 wishbone-compliant: 1 - category: ECC core created: Dec 8, 2007 description: "===== \n PCI express CRC verilog code 16 bit data 32 bit CRC =====\n\nFunctional Description\n\nDesigners commonly use Cyclic Redundacy Codes (CRC) as an alternative to parity and checksum calcutions for checking and correcting errors in data transmissions.\n\nThe CRC method for error detection and correction treats the data frame as a huge binary number. The binary number is divided (at the CRC generation end) by a fixed binary number (the CRC generator polynomial) and the resulting remainder of this division (CRC value) is appended to the end of the data frame. The receiver upon reception of the data frame repeats the calculation and compares its calculated CRC value the CRC value attached to the data frame. The traditional method for implementing a CRC generator uses a shift register with XOR gates and feedback taps.\n\nThe classic serial implementation is widely used, but it is too slow for PCI Express LCRC and Gigabit Ethernet where bit rates can top 100 Mb/sec. The alternative method is parallel CRC calculations. This parallel conversion effectively divides the input clock frequency by 8, 16, or 32.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n-feature1\t Verilog LCRC code for PCI Express TLP packets\n-reature1.1\t16 bit data in 32 bit LCRC out" language: Verilog license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - cmagleby name: pci_express_crc status: Stable svn-updated: Mar 10, 2009 updated: Dec 17, 2007 wishbone-compliant: 0 - category: Communication controller created: Jan 8, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this).\n \n\n\n \n \n \n\n===== \n ROM.V =====\n\nmodule rom(address,data);\n\ninput [9:0]address;\n\noutput [7:0]data;\nreg [7:0]data;\n\n\nalways@(address)\ncase(address)\n\n0\t:\t\t\t\t\tdata 1\t:\t\t\t\t\tdata 2\t:\t\t\t\t\tdata 3\t:\t\t\t\t\tdata 4\t:\t\t\t\t\tdata 5\t:\t\t\t\t\tdata 6\t:\t\t\t\t\tdata 7\t:\t\t\t\t\tdata 8\t:\t\t\t\t\tdata 9\t:\t\t\t\t\tdata 10\t:\t\t\t\t\tdata 11\t:\t\t\t\t\tdata 12\t:\t\t\t\t\tdata 13\t:\t\t\t\t\tdata 14\t:\t\t\t\t\tdata 15\t:\t\t\t\t\tdata 16\t:\t\t\t\t\tdata 17\t:\t\t\t\t\tdata 18\t:\t\t\t\t\tdata 19\t:\t\t\t\t\tdata 20\t:\t\t\t\t\tdata 21\t:\t\t\t\t\tdata 22\t:\t\t\t\t\tdata 23\t:\t\t\t\t\tdata 24\t:\t\t\t\t\tdata 25\t:\t\t\t\t\tdata 26\t:\t\t\t\t\tdata 27\t:\t\t\t\t\tdata 28\t:\t\t\t\t\tdata 29\t:\t\t\t\t\tdata 30\t:\t\t\t\t\tdata 31\t:\t\t\t\t\tdata 32\t:\t\t\t\t\tdata 33\t:\t\t\t\t\tdata 34\t:\t\t\t\t\tdata 35\t:\t\t\t\t\tdata 36\t:\t\t\t\t\tdata 37\t:\t\t\t\t\tdata 38\t:\t\t\t\t\tdata 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936\t:\t\t\t\t\tdata 937\t:\t\t\t\t\tdata 938\t:\t\t\t\t\tdata 939\t:\t\t\t\t\tdata 940\t:\t\t\t\t\tdata 941\t:\t\t\t\t\tdata 942\t:\t\t\t\t\tdata 943\t:\t\t\t\t\tdata 944\t:\t\t\t\t\tdata 945\t:\t\t\t\t\tdata 946\t:\t\t\t\t\tdata 947\t:\t\t\t\t\tdata 948\t:\t\t\t\t\tdata 949\t:\t\t\t\t\tdata 950\t:\t\t\t\t\tdata 951\t:\t\t\t\t\tdata 952\t:\t\t\t\t\tdata 953\t:\t\t\t\t\tdata 954\t:\t\t\t\t\tdata 955\t:\t\t\t\t\tdata 956\t:\t\t\t\t\tdata 957\t:\t\t\t\t\tdata 958\t:\t\t\t\t\tdata 959\t:\t\t\t\t\tdata 960\t:\t\t\t\t\tdata 961\t:\t\t\t\t\tdata 962\t:\t\t\t\t\tdata 963\t:\t\t\t\t\tdata 964\t:\t\t\t\t\tdata 965\t:\t\t\t\t\tdata 966\t:\t\t\t\t\tdata 967\t:\t\t\t\t\tdata 968\t:\t\t\t\t\tdata 969\t:\t\t\t\t\tdata 970\t:\t\t\t\t\tdata 971\t:\t\t\t\t\tdata 972\t:\t\t\t\t\tdata 973\t:\t\t\t\t\tdata 974\t:\t\t\t\t\tdata 975\t:\t\t\t\t\tdata 976\t:\t\t\t\t\tdata 977\t:\t\t\t\t\tdata 978\t:\t\t\t\t\tdata 979\t:\t\t\t\t\tdata 980\t:\t\t\t\t\tdata 981\t:\t\t\t\t\tdata 982\t:\t\t\t\t\tdata 983\t:\t\t\t\t\tdata 984\t:\t\t\t\t\tdata 985\t:\t\t\t\t\tdata 986\t:\t\t\t\t\tdata 987\t:\t\t\t\t\tdata 988\t:\t\t\t\t\tdata 989\t:\t\t\t\t\tdata 990\t:\t\t\t\t\tdata 991\t:\t\t\t\t\tdata 992\t:\t\t\t\t\tdata 993\t:\t\t\t\t\tdata 994\t:\t\t\t\t\tdata 995\t:\t\t\t\t\tdata 996\t:\t\t\t\t\tdata 997\t:\t\t\t\t\tdata 998\t:\t\t\t\t\tdata 999\t:\t\t\t\t\tdata 1000\t:\t\t\t\t\tdata 1001\t:\t\t\t\t\tdata 1002\t:\t\t\t\t\tdata 1003\t:\t\t\t\t\tdata 1004\t:\t\t\t\t\tdata 1005\t:\t\t\t\t\tdata 1006\t:\t\t\t\t\tdata 1007\t:\t\t\t\t\tdata 1008\t:\t\t\t\t\tdata 1009\t:\t\t\t\t\tdata 1010\t:\t\t\t\t\tdata 1011\t:\t\t\t\t\tdata 1012\t:\t\t\t\t\tdata 1013\t:\t\t\t\t\tdata 1014\t:\t\t\t\t\tdata 1015\t:\t\t\t\t\tdata 1016\t:\t\t\t\t\tdata 1017\t:\t\t\t\t\tdata 1018\t:\t\t\t\t\tdata 1019\t:\t\t\t\t\tdata 1020\t:\t\t\t\t\tdata 1021\t:\t\t\t\t\tdata 1022\t:\t\t\t\t\tdata 1023\t:\t\t\t\t\tdata endcase\n\nendmodule\n\n\n\n\nmodule device(dataout,address,clk,rst,length,addressrom,datarom,enable);\n\ninput clk,rst,enable;\n\n\ninput [9:0]address;\n\n\noutput [7:0]dataout;\n\n//wire [9:0]addressrom;\n\ninput [7:0]datarom;\n\ninput [9:0]length;\n\noutput [9:0]addressrom;\n\nreg [9:0]addressrom;\n\n//rom r1(addressrom,datarom);\n\n\n\n//assign addressrom=address;\n\n\n\nassign dataout=datarom;\n\nreg [9:0]counter;\n\nwire read;\n\nassign read=(counter\n\n\n\n\nalways@(posedge clk)\nif(rst)\nbegin\ncounter=0;\n\nend\n\nelse\n\nbegin\n\nif(read && enable)\nbegin\naddressrom=address;\nend\n\nif (read)\nbegin\naddressrom=addressrom+1;\ncounter=counter+1;\nend\n\n\nend\n\n\nendmodule\n\n\n\n\nmodule device_request_system(address,clk,rst,dataout,length,enable);\n\n\ninput clk,rst,enable;\n\ninput [9:0]address;\n\noutput [7:0]dataout;\n\ninput [9:0]length;\n\nwire [9:0]addressrom;\n\nwire [7:0]datarom;\n\nrom r1(addressrom,datarom);\n\n\ndevice d1(dataout,address,clk,rst,length,addressrom,datarom,enable);\n\n\nendmodule" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - arslanmajid name: pci_express_model_design status: Empty updated: Jan 9, 2011 wishbone-compliant: 0 - category: System controller created: Feb 5, 2008 description: "===== \n Description =====\n\nThis is a very simple PCI-target to Wishbone-master bridge. \nPCI-Target only, the bandwidth is quite low, fixed memory-image size (16MB), but it has a very low FPGA logic resource need. \nThis is a single VHDL (old version was verilog) file, so easy to use. \n\nThe original PCI module is from: Ben Jackson http:www.ben.com/minipci/verilog.php \nRedesigned for wishbone : Istvan Nagy, Hardware Design Engineer. www.buenos.extra.hu \n\nCode variants/versions:\n----------------------- \n- Up till v3.3 (verilog) the code was tested on Xilinx Spartan-2/3 FPGAs using XST to synthesise. These versions don't have the automatic read-retry feature implemented, so the software developer has to read every location twice. Files: pci-33.v, sample_timing_constraints.ucf.txt. \n- V3.4 (verilog) contains modifications to make it work on Actel/Microsemi ProASIC3 FPGAs using Synplify for synthesis, and also implements the automatic read-retry PCI feature. It means that the read transactions are terminated by the target with \"retry\" so next time the host accesses the device with read from the same address will return the right read data and the target terminates with successful access. This effects the software development in a way that we don't have to read every location twice just once. v3.4 was not tested on Xilinx FPGAs. Files: pci_mini-34.v, pci_mini-34_timing_constraints.sdc\n- v4.0 (VHDL) is completely rewritten from scratch in VHDL. The reason for that was to improve static timing and to avoid strange behaviour of the v3.4 seen on Actel FPGAs with a few certain configurations. For example the input setup time and clock-to-output-delay was reduced from ~10ns to ~3ns. A few features were removed, like address remapping and user-reset-control. This version has to be used with the pci_mini_40_timing_constraints.sdc timing constraints file. This was only tested on Actel ProAsic3 FPGAs.\n\nTest results:\n-------------\nTested on hardware: \n-PCI card (with SP2 FPGA) plugged into an old PC with Pentium-II CPU and VIA VT82C693A+VT82C596B chipset \n-Custom motherboard designed by me, with the AMD Geode-LX processor, Geode chipset, and a Xilinx Spartan-3 FPGA. \n-Com-Express carrier board with Intel Atom Z520 processor (on the COMe), and Actel ProASIC3 FPGA (on the carrier). \nTest software: Hardware-Direct, Read-Write-Everything. \nFPGA project: a peripheral block, consisting: Wishbone intercon module, CAN controller, some custom peripherals, and the PCI2WB bridge. \nAlthough it was working in the 3 test systems, it was not validated against all the specifications of the PCI standard, it means it was not tested with standard compliance test methods (like Agilent PCI excercisers and analyzers). So no guarantee for anything, if you want to use it, you should test it. The 33MHz PCI 2.0 I/O-timing specifications were met (can be seen on the timing reports of the ISE development tool.), guaranteed by the timing constraints in the ucf/sdc files and the development tools. On the Spartan-2 FPGA board, the maximum frequency in the Xilinx-ISE STA result was just a littlebit above the 33MHz target (it was 39MHz) for the whole PCI-wishsbone system (the wishbone system used the PCI clcok too, so it was a single clock-domain synchronous system). The v4.0 on the A3P400 device meets the timing requirements of the PCI-66MHz (post P&R STA report), although it was never tested on 66MHz.\n\nSynthesis: \n----------\nv3.3: 279 Slices on Xilinx Spartan-3 FPGA. (14.5% logic on SP3-200k)\nv4.0: 719 Core Cells on Actel ProAsic3 FPGA. (8% logic on A3P400)\n\n\nFor simulating the core: generate 2 pci config-write transactions for initializing the bridge: write a base address (multiple of 16MB) to BAR0 at 14h , then enable by writing 7 to address 4h. after this, your transactions (single memory read/write at the address range specified by the base address) will go through the bridge. (devsel timing = \"fast\") \n\nMy website: www.buenos.extra.hu \n\nLicense: You can use it for anything for free, even to put it into your products and sell those products. thats all. (LGPL) \nAll the files can be found in the SVN view, the web downlaod tab might not contain all project files. \n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- PCI target interface\n- 16MB memory image\n- Wishbone master interface\n- Configurable address translation through a config space user register\n- Single dword buffering (only 32bit mode is supported)\n- No burst transactions (mem r/w multiple) supported.\n- Delayed read request and posted write data transfers. (on v3.3 the reads are not retried automatically, so the user software has to initiate two reads from the same address, for every Dword. v3.4/v4.0 implements auto-retry) \n- Configurable address translation through a config space user register (v3.3/v3.4 only) \n- Downstream system control by 8 GPIO signals, throug config space (reset, low power mode..., v3.3/v3.4 only) \n \n\n\n \n \n \n\n===== \n Status =====\n\n- finished, tested" language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - buenos name: pci_mini status: FPGA proven svn-updated: Jun 1, 2011 updated: Aug 17, 2011 wishbone-compliant: 1 - category: System controller created: Nov 9, 2011 description: "===== \n Motivation =====\n\nThere are already a few cores that translate PCI bus into Wishbone bus, but none of them really worked in my project. So I took the code of the project \"pci_mini\" and built my own core out of it. Thanks to the original authors of pci_mini! \nI'm quite new to VHDL, and this is my first big project. So I cannot guarantee that everything runs 100% smooth, but I try my best. :-)\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the minimum which is required by the PCI specification (and I'm really trying to stick exactly to the specs).\nThe whole source code is contained in one file, that makes it easy to implement into a project.\nIt's not officially WB compatible because master arbitration is not supported.\nThe biggest differences to pci_mini are:\n\xE2\x80\xA2 Generally more direct and faster accesses. Reads are not delayed, but are completed in the same cycle. After finishing a PCI cycle, a next cycle could begin immediately, no additional wait time is required.\n\xE2\x80\xA2 PCI Byte Enable bits are payed regard to when reading or writing to config registers (but not when accessing memory).\n\xE2\x80\xA2 Interrupts are not supported anymore. It would be easier to connect interrupts from WB directly to the other device instead of routing it through the PCI interface.\n\xE2\x80\xA2 More comments in the code body. My goal was that everyone should be able to understand what's going on (and eventually to change the core to his own needs).\n\nMore detailed information is given in the code file.\n \n\n\n \n \n \n\n===== \n Status =====\n\nFinally! I was able to upload the file. The documentation is useless for beginners like me... :-)\n\nGenerally, the core is work in progress.\nAt the moment, I can work with it in my project, but there are some bugs in special cases, e.g. access at an address that doesn't belong to a WB slave etc.\n\nFeel free to write me when you notice a mandatory PCI spec detail I haven't implemented (which is the part I'm most worried about)!" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Lord_Nelson name: pci_to_wb status: Alpha svn-updated: Dec 6, 2011 updated: Dec 6, 2011 wishbone-compliant: 0 - category: System controller created: Aug 10, 2012 description: "===== \n Description =====\n\nThe PCIe_DS_DMA core provides PCI Express controller for Xilinx HARD core for Virtex5, Virtex6, Spartan6 FPGA.\n\n===== Main features =====\n\n\n PCI Express 1.1 x1,x4,x8 or 2.0 x4\n two address space: BAR0, BAR1\n access to registers can only be single 32-bit instructions\n local bus: 64 bit, 250 MHz\n two independent bidirectional DMA channel\n DMA channel only works in the SCATTER-GATHER mode\n The minimum unit of data for channel DMA - 4 kB\n Descriptors combined into the block descriptors. The maximum number of descriptors in the block - 63\n DMA channel uses 40 bit addresses\n\n\n===== Resource =====\n\nThe main site of project: http://ds-dev.ru/projects/ds-dma\n\n\n\n\nEnglish Wiki: http://ds-dev.ru/projects/ds-dma/wiki/English\n\n\n\n\nRussian Wiki: http://ds-dev.ru/projects/ds-dma/wiki\n\n===== Struct of repository =====\n\n\ncore - common code \n\n ds_dma64\\pcie_src - pci express controller\n adm - common files to ADM projects\n wishbone - commons files to WISHBONE projects\n \nprojects - projects for several boards\nsoft\\linux - Software for Linux\n \n common - common code\n application - test application\n driver\\pex_drv - driver for linux core\n exam - simple examples\n \n\n\n===== ADM projects =====\n\nADM is internal inteface of Instrumental Systems company: http://www.insys.ru\n\n\nambpex5_v20_sx50t_core - example project for AMBPEX5 board.\nml605_lx240t_core - example project for ML605 board.\nsp605_lx45t_core - example project for SP605 board.\n\n\n===== WISHBONE projects =====\n\n\nsp605_lx45t_wishbone - example project for SP605 board.\nambpex5_sx50t_wishbone - example project for AMBPEX5 board.\n\n\n===== Main components =====\n\nPCI Express controller with PLD_Bus\n\nPLD_Bus is an internal packet bus of DS_DMA controller. PLD_Bus can be transform to another bus as LC_BUS, Wishbone, AXI, etc.\nThere are three main components:\n\npcie_core64_m1 - PCI Express controller for Virtex 5\npcie_core64_m4 - PCI Express controller for Virtex 6\npcie_core64_m6 - PCI Express controller for Spartan 6\n\n\nPCI Express controller with LC_Bus\n\nLC_Bus is a generic parallel bus. The bus contains 32-bit addres bus, 64-bit data bus and several contol signals.\n\nComponents:\n\npcie_core64_m2 - PCI Express controller for Virtex 5\npcie_core64_m5 - PCI Express controller for Virtex 6\npcie_core64_m7 - PCI Express controller for Spartan 6\n\n\n\nPCI Express controller with Wishbone bus\n\nComponents:\n\npcie_core64_wishbone - PCI Express controller for Spartan 6\npcie_core64_wishbone_m8 - PCI Express controller for Virtex 5\n\n\n===== Results =====\n\nSpeed of data transfer for PCI Express v1.1 x8 : http://ds-dev.ru/projects/ds-dma/wiki/Ambpex5_v20_sx50t_core_res_en\n\n===== Download =====\n\nDownload page: http://ds-dev.ru/projects/ds-dma/wiki/Download\n\n===== Contact =====\n\nDmitry Smekhov\n\nE-mail: dsmv@mail.ru\nLinkedIn: http://www.linkedin.com/pub/dmitry-smekhov/1a/b15/607\n\n\nIgor Kazinov\n\nE-mail: igor.kazinov@gmail.com\nLinkedIn: http://ua.linkedin.com/pub/igor-kazinov/21/432/792\n\n\nVladimir Karakozov\n\n E-mail: karakozov@gmail.com" language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dsmv - kuzmi4 name: pcie_ds_dma status: Alpha svn-updated: Mar 17, 2014 updated: Apr 20, 2013 wishbone-compliant: 1 - category: System controller created: Apr 23, 2011 description: "===== \n Description =====\n\npcie_mini IP core\nPCI-express to Wishbone Bridge for Xilinx FPGAs.\n\nDeveloper: Istvan Nagy, Bluechip Technology, 2011\n\nVery often we want to make a peripheral card or a peripheral block on an x86 motherboard using an FPGA, but not necesserily want to spend a lot of time on developing common blocks (like a PCI-express interface), we want to focus on our own custom logic design instead and use completely implemented IP cores for the common blocks. The \"mini\" in the name doesn't refer to a minicard formfactor, but it just signifies that the core is small and is implemented as a single VHDL file. This is a simple implementation of a PCI-Express target to Wishbone master bridge. \n\nThe Xilinx Series-5/6 FPGAs have a built-in PCI-Express Endpoint Block, however it does not contain the packet encoding/decoding logic. This IP core (pcie_mini) implements the missing parts of the Xilinx core and also adds a Wishbone back-end interface. Strangely the Xilinx PCIE-EP handles packet encoding/decoding for configuration accesses, but not for memory accesses. This core interfaces the Xilinx PCIE-EP with its Transaction (TRN) interface. The Xilinx Series-7 FPGAs have a more complete PCIE-EP, but they also support using the TRN interface, but unfortunatelly they only support 64-bit/128bit parallel buses at the moment (November 2011), which would require a redesign of the pcie_mini_core. The user has to use the Xilinx Coregenerator to generate a PCIE-EP wrapper (xilinx source files) for the chosen target FPGA device. pcie_mini still needs the Xilinx PCIE Endpoint block and the GTP transceivers.\n\nThis core works with a fixed 256Mbytes memory window, only BAR0 is implemented. It was tested with 32/16/8-bit single memory read and write transactions. The data fields in the PCIe packets get endianess-swap by the core, to match the internal 32-bit bus layout with the 32bit variable view in the test software.\nThe core was tested on a x1 PCIe card (custom designed card having Spartan-6 LX45T FPGA on it) with nVidia chipset on the test motherboard, ISE 12.1, RW v1.4.9 (debug program) and Windows-XP (on Windows-7 accessing the core with a debug program without an installed driver is not possible). The wishbone addresses are byte addresses just like the PCI-express addressing. The Wishbone byte enables are derived from the PCIe packets. \nThe output address of the core contails the 2 LSBs as well. The TLP logic is capable of handling up to 1k bytes (256 DWORDs) payload data in a single PCIe transaction, and can handle only one request at a time. If a new request is arriving while processing the previous one (e.g. getting the data from a wishbone read), then the state machine will not process it immediately, or it will hang. So the user software has to wait for the previous read completion before issueing a new request. The multiple data DWORDs in a single TLP generate separate Wishbone transactions. Theoretical Performance: WishBone bus: 62.5MHz, 32bit, 2clk/access -> 125MBytes/sec. Consecutive single write test showed 15.625 MBytes/sec bandwidth, read performance is expected to be a lot lower due to the turnaround time of the read transactions. The maximum data throughput could be achieved when using the maximum data payload size (1kBytes), although it was not tested in lack of such test software. The core uses INTA virtual wire to signal interrupts. It uses a 100MHz ref clock. The The generated Xilinx core had to be edited manually to support 100MHz, as per Xilinx AR#33761.\n\nImplementation tips:\n-make use of the attached UCF file and edit it,\n-Synthesis-KeepHierarchy=Yes, \n-Translate-AllowUnmatched_XX_Constraints=Yes\n-If there are timing errors we still might want to procees to be able to analyze the violation details. For this, we have to set the windows env.variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.\n-In the synthesis properties, pack IOB registers = off, Set the \"FSM Encoding Algorithm\" to \"user\". \n-To make the FPGA-chip to configure in 500ms, set the bitgen option \"config rate\" to 33 (MHz).\n\nResource utilization:\n(The pci_mini with the xilinx PCIE-EP wrapper files together)\n540 Slice registers,\n779 Slice LUTs,\n10 BRAMs (RAMB16BWER, 22kBytes total)\n3 BUFGs\n1 PLL\n\nFiles (browse CVS):\n-xilinx_pcie2wb.vhd - this is the pcie_mini IP core\n-blk_mem_gen_v4_1.vhd and .ngc - this is an internal BlockRam for the pcie_mini\n-pcie*.vhd and gtpa1*.vhd - these are the wrapper files from the Xilinx CoreGenerator. The user might have to re-generate them in case of using a different FPGA device (these were generated for the XC6SLX45T-2FGG484) or different settings like SS-VID.\n-pcie_mini_constraints.ucf - example constraints for the core to be included in your chip-level project. It has to be edited by the user.\n\nProject Status: (v1.1)\n-Tested and working with 32/16/8-bit single memory reads and writes, also fast consecutive single reads/writes. \n\nTest hardware: \nCustom designed x1 PCIe data acquisition card having Spartan-6 LX45T FPGA on it, nVidia chipset on the test motherboard, ISE 12.1, RW v1.4.9 (debug program) and Windows-XP. The card has its own DDR2 memory and peripherals (200MSPS ADC, DSP, communications interface) that all access to the same DDR2 memory. The PCIe accesses were all accessing either internal control registers or the on-board memory.\n\nTo-do:\n-Write a test program to generate bulk/burst read/write transactions where the TLP payload size >> 1 (eg 16Bytes or 1024Bytes). If someone could write such a program, then we could progress with the development to the high bandwidth bulk data transfer support.\n\nLicense: LGPL, you are free to use it and to build it into your products." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - buenos name: pcie_mini status: FPGA proven svn-updated: Aug 10, 2012 updated: Nov 14, 2011 wishbone-compliant: 1 - category: System controller created: Aug 24, 2011 description: "===== \n Overview =====\n\nThis package involves a PCIe Scatter-Gather DMA engine for Virtex5 and Virtex6.\n\nThe design implements MAC, Physical (Xilinx Hard and Soft IP Cores) and Transaction Layer (Custom Core) of PCIe. \n\nIt holds 3 BAR\xE2\x80\x99s, BAR[0], BAR[1] and BAR[2], as its memory space. Registers are accessed via BAR[0], including the system registers, DMA channel registers and some other control and status registers. Block RAM are assigned to BAR[1]. BAR[2] contains the FIFO data ports, both write and read. FIFO control and status registers reside in BAR[0]. All 3 applied BARs are accessible with PIO operation (PIO to the FIFO can only access 32 bits of the 64-bit bus). DMA can only target on BAR[1] and BAR[2], 64-bit full bus.\n\nThe design was split into two projects: one for Virtex5 (in \"Trunk\" folder) and the other for Virtex6 (in \"branches\" folder).\nIt was fully tested on:\n - AVNET Virtex5 PCIe Development Board\n - Xilinx Virtex6 ML605 Development Board \n\nSimulation is provided in Verilog HDL for both platforms.\n\nThe design is composed by some Xilinx IP Cores. Both the VHDL code and the CoreGen .xco file are provided. To change or upgrade them, a valid license for the cores from Xilinx Inc. should be available. The PCIe core is the 1.6 version in ISE12.3 and 1.7 versione in ISE 13.3. The old 1.3 version is also provided.\n\nThe DMA throughput depends on OS, machine, implementation and packet size:\nOn a Dell Precision T5500 with Linux Debian 2.6.32 64bit we measured:\n\nVirtex5 board:\n - PCIe gen1.0 x4: write: up to 700 MB/s - read: up to 380 MB/s\n\nVirtex6 board:\n - PCIe gen2.0 x1: write: up to 426 MB/s - read: up to 417 MB/s\n - PCIe gen1.0 x4: write: up to 828 MB/s - read: up to 524 MB/s\n\nAnother Virtex5 board DMA performance test under Linux achieves\n - PCIe Gen1 x4: write 790 MB/s; read 543 MB/s (FIFO) or 507 MB/s (BRAM).\n\nLinux driver are avaible at: http://li5.ziti.uni-heidelberg.de/mprace/ (THX to Dr. Guillermo Marcus)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - weng_ziti - hitechor - barabba name: pcie_sg_dma status: FPGA proven svn-updated: Mar 26, 2012 updated: Mar 26, 2012 wishbone-compliant: 0 - category: System controller created: Dec 5, 2007 description: "===== \n pcie_vera_tb =====\n\nFEATURES\n\xE2\x80\xA2\t16 bit PIPE Spec PCI Express Testbench\n\xE2\x80\xA2\tLink training \n\xE2\x80\xA2\tInitial Flow Control\n\xE2\x80\xA2\tPacket Classes for easy to build PHY,DLLP and TLP packets\n\xE2\x80\xA2\tDLLP 16 bit CRC and TLP LCRC generation\n\xE2\x80\xA2\tSequence Number generation and checking\n\xE2\x80\xA2\tACK TLP packets\n\xE2\x80\xA2\tScrambling\n\xE2\x80\xA2\tMemRd MemWr CfgRd CfgWr TLPs\n\n\n\nFunctional Description and Background\nThis testbench has been designed to resemble the TI XIO1100 X1 PHY which has a 16 bit 125 MHz PIPE spec interface. This is a great PCI Express starter VERA testbench. It can easily be added to, to get the desired results. The testbench performs link training, initial flow control and TLP generation. The entire packet is built up including starting and ending symbols as well as the correct LCRC values. The testbench can be modified fairly easily to put out 8 bits at a time rather than 16 bits. \n\nLink Training\nThe testbench looks for a receiver detect sequence and then a power change sequence to put it into operational mode. After the PHY is in operational mode training sets will be sent out. Initially TS1 order sets will be sent by the testbench. The testbench will also receive TS1 order sets and process them. When the device under test sends TS2 order sets the testbench will respond with TS2 order sets. Then the link and lane negotiation will be preformed. After the logical idles the Testbench will indicate link up.\n\nInitial Flow Control\nAfter link up the testbench will generate and receive DLLP initial flow control packets. These packets include initial credits for non-posted, posted and completion credits.\nThese are DLLP packets that have the correct LCRC values attached.\n\nThe initial flow control credits can be easily changed. Here is a table of there default values.\n\n\nType\tValue\nNon-Posted Credit\t4 header credits\nPosted Credit\t4 header credits, 1k data credit\nCompletion Credit\t4 header credits, 1k data credit\n\nSkip Order Sets\nThe testbench will send out skip order sets on a regular basis.\n\n TLP Packet Generation \nThere are built in tasks for CfgWr; CfgRd; MemWr and MemRd packet types. Based on these packets other packet types can easily be made. The sequence number and LCRC values are correctly generated by the Testbench. The tasks accept requestor id, byte enables, length, address, tag etc. to allow many unique packet to be generated.\n\nData Scrambling/De-scrambling\nThe testbench scrambles the 16 bits of data based on the PCI express rules. Scrambling can be bypassed in the testbench. Scrambling is applied to Data characters associated with DLLPs and TLPs including logical idles and Data characters TS1 and TS2 ordered sets. K characters are not scrambled and bypass the scramble logic. Compliance pattern related characters are not scrambled. When a COM character exits the scrambler the COM does not get scrambled, but it initializes the LFSR to 16\xE2\x80\x99hFFFF. Similarly on the receive side the COM character initializes the de-scrambler to 16\xE2\x80\x99hFFFF. The LFSR does not advance on SKP characters. Gutz Logic also offers a 16 bit RTL scrambler/descrambler code.\n\nFile Description\nFile\tDescription\nrun_vera\tThis is the command file to run\nti_phy_top.test.top.v\tTop level testbench linking Vera with the RTL\nti_phy_top.if.vrh\tInterface file\nti_phy_top.v\tTop level non-synthesizable RTL file(add your RTL HERE)\nreceive_packet.vri\tVERA file for receiving all PCIe packets 16 bits at a time\nsend_packet.vri\tVERA file for sending all PCIe packets 16 bits at a time\npcie_phy_packet.vri\tVERA file class for PHY layer packets\npcie_dllp_packet.vri\tVERA file class for DLL layer packets\npcie_tlp_packet.vri\tVERA file class for TLP layer packets\nlink_training.vri\tVERA file for Link Training\ntlp_gen.vri\tVERA file for generating TLP packets\nInitFC1.vri\tVERA file for Credit Initialization\nskip_order_set.vri\tVERA file for generating Skip Order Sets\nscramble8.vri\tVERA file for scrambling and descrambling the data\n\nAdditional Tasks to be Added\nThe testbench currently does not include credit updates and credit control. Additional Packet processing including Messages; IOWR; IORD and completion packets. Error Checking, Data compare functions and NACK generation needs to be added Additional PIPE spec functions such as loopback, electrical idles, Serdes errors\n\n \n\n\n \n \n \n\n===== \n pcie_vera_tb Features =====\n\n-feature1.1\t16 bit PIPE Spec PCI Express Testbench\n-feature1.2\tLink training \n-feature1.3 Initial Flow Control\n-feature1.4\tPacket Classes for easy to build PHY,DLLP and TLP packets\n-feature1.5\tDLLP 16 bit CRC and TLP LCRC generation\n-feature1.6 Sequence Number generation and checking\n-feature1.7\tACK TLP packets\n-feature1.8\tScrambling\n-feature1.9 MRd MWr CfgWr CfgRd functions\n\n \n\n\n \n \n \n\n===== \n pcie_vera_tb Status =====\n\n- working\n- beta" language: Other license: unknown maintainers: - cmagleby name: pcie_vera_tb status: Design done svn-updated: Mar 10, 2009 updated: Jan 15, 2008 wishbone-compliant: 0 - category: Arithmetic core created: May 19, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: pcle_dma_bram status: Empty updated: May 19, 2012 wishbone-compliant: 0 - category: Other created: Sep 11, 2012 description: "===== \n Description =====\n\nFast binary counter, designed to minimize logic path length in between flip-flops\nto one gate (MUX/AND) only, at the expense of not so straightforward binary counting.\nAimed to slow architectures without fast carry chain.\n \n\n\n \n \n \n\n===== \n Summary =====\n\nThe reason for this design has emerged while using Actel (MicroSemi)\nProASIC/IGLOO architecture, lacking any hardwired support for fast carry.\n\nDuring our work on Actel FPGAs (basically, 3-LUT & DFF only), we were\naware of following types of faster counters:\n- LFSR counter\n- Johnson counter\n- \"RLA counter\" (as tailored using Actel's SmartGen core generator)\n\nJohnson due to its O(2^n) (n as number of bits) can not be used for\nlonger counts; LFSR's are hard to invert (table lookup seems to be\nonly known method), therefore also impractical for wider counters. RLA\ncounter is still too slow and complex for wider counters and moderate\nspeeds (e.g. > 24bits @ >100MHz).\n\nAs a consequence, the proposed counter uses synchronous divide-by-two\nblocks, each using 1-bit pipeline and carry by single-clock\npulse. Design is simple and fast, preliminary results from Synplify\nand Actel Designer shows 32bits @200MHz feasible.\n\nHowever, output bit lines are non-proportionaly delayed by discrete\nnumber of clock periods. Therefore, to obtain linear bit word, an\ninversion formula needs to be applied. Fortunately, the inversion is\nsimple (unlike LFSR's), in C (pcount.c):\n\n for (k = 1; k < n; k++)\n if ((y & ((1<\n \n\n===== \n Figures =====\n\n\n\n \n\n\n \n \n \n\n===== \n Files =====\n\npdivtwo.vhdl ... basic building block -- 1-stage pipelined flip-flop\npdchain.vhdl ... counter top-level entity\npcount_tb.vhdl ... GHDL testbench\npcount.c ... C language encoder/decoder of counter bitword\ndoc/pcounter_4bit_trace.pdf ... simulated signals of 4-bit counter\ndoc/pcounter_sch.pdf ... schematic diagram of the counter\n\nmake testvcd ... produces .vcd file\nmake testrun ... runs GHDL simulation piped to C bitword decoder/encoder\n \n\n\n \n \n \n\n===== \n Results =====\n\nSynthesized within larger circuit for Actel ProASIC3E A3PE1500-Std\nas 32bit wide counter, typical frequency: 234MHz\n\n \n\n\n \n \n \n\n===== \n Comments =====\n\nIf you find this idea useful, apply it whenever you want, however,\nshare your improvements. E.g.:\n- (fast) HDL implementation of bitword encode/decode\n- preset/reset/match/enable logic\n\nTestimonials (usage/frequency/bits/architecture) are indeed welcome.\n \n\n\n \n \n \n\n===== \n Prior Art =====\n\nThanks to answers in comp.arch.fpga, there are some pointers to similar or same prior art.\nCheck it at http://www.fpgarelated.com/usenet/fpga/show/106762-3.php" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robotron name: pcounter status: FPGA proven svn-updated: Sep 11, 2012 updated: Oct 1, 2012 wishbone-compliant: 0 - category: System on Chip created: Feb 22, 2011 description: "===== \n Description =====\n\nPDP-1 reimplementation using an FPGA. The goal is to run old software like Spacewar!, the music compiler, and Expensive Typewriter on current FPGA hardware. Initial platform is a Spartan 3A starter kit.\nFor more information on the original machine, see http://pdp-1.computerhistory.org/pdp-1/" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - yannv name: pdp1 status: Alpha svn-updated: Mar 8, 2011 updated: Feb 23, 2011 wishbone-compliant: 0 - category: Processor created: Jul 8, 2012 description: "===== \n Description =====\n\nThe PDP-8 was one of the earliest minicomputers and was in use from the mid 1960s into the 1980s.\n\n\n\nBecause the PDP-8 was relatively inexpensive and was available in various forms for many years, the PDP-8\nis remembered fondly by many programmers and engineers\n\n\n\nThis project implements a complete PDP-8 system.\nThe system includes the many of the basic PDP-8 peripherals including:\n\n Configurable PDP-8 CPU \n MS8C 32K-word memory \n KC8E Front Panel\n KE8 Extended Arithmetic Element\n KM8E Extended Memory\n KM8E Time Sharing\n DK8EA/DK8EC/DK8EP Real Time Clock\n KL8E Asynchronous Serial Interface (x2)\n LS8E Printer Interface\n PR8E Paper Tape Reader\n KL8E Disk Controller with 4 RK05 Disks Attached\n\n\n\n\n===== Status =====\n\nThe system passes all relevant diagnostics (MAINDECs) with the exception of the RK8E\nDisk Controller. The system boots OS/8 and runs all applications. \n\n\n\nSuccessful Implementations\n\nNEXYS2\n\n\nThe design has been implemented and tested on a \nDigilent NEXYS2\nEvaluation Board using the Xilinx ISE Webpack Version 13.3 toolset.\n\n\n\n\n\n Note: The 1200K Gate version of the NEXYS2 board is required because all 32K words\nof RAM are implemented in FPGA block RAM.\n\nAltera DE2-115\n\n\nThe design has been implemented and tested on a \nAltera DE2-115\nEvaluation Board using the Quartus II 11.1 Build 173 Full Version toolset.\n\n\n\nORSoC ordb2a-ep4ce22\n\n\nThe design has been implemented and tested on a \nORSoC ordb2a-ep4ce22\nBoard using the Quartus II 11.1 Build 173 Full Version toolset.\n\n\n\nAltera DE0-Nano\n\n\nThe design is currently being implemented on a \nAltera DE0-Nano\nDevelopment and Education board using the Quartus II 12.0 Web Edition tool set.\n\n\n\n\n\nThe DE0-Nano is expected to be the least expensive platform for this device\nand is available at a cost of $86.25 from (among other places)\nDigikey." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - trurl - radioengr name: pdp8 status: Alpha svn-updated: Nov 1, 2013 updated: May 18, 2013 wishbone-compliant: 0 - category: Processor created: May 27, 2013 description: "===== \n Description =====\n\nThis is an implementation of a Digital (DEC) PDP8/L processor with 4k memory, a single DF32 disk and serial interface. The project target is the ALTERA NEEK (Cyclone III EP3C25F324C6N). Run the 4K Disk Monitor System using only the FPGA chip. Download contains the complete Altera Quartus II (11.0) project directories with simulation files." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Isysxp name: pdp8l status: FPGA proven svn-updated: May 28, 2013 updated: May 28, 2013 wishbone-compliant: 0 - category: Processor created: May 6, 2011 description: "===== \n Building team. If any beginner became inetersted in it, email me. =====\n\n\n \n\n===== \n About =====\n\nPepelatz MISC is a very small 16-bite processor written on Verilog.\nIt can be used for learning Verilog HDL and computer low-level architecture." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - 418ImATeapot name: pepelatz_misc status: Planning svn-updated: May 7, 2011 updated: May 25, 2011 wishbone-compliant: 0 - category: Other created: Jan 16, 2004 description: "===== \n Description =====\n\nPerlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. \n\nAt a smaller scale, Perlilog is a great starting point for writing scripts which handle Verilog code in general. It comes with a rich set of functions, that can be used for several purposes, such as instantiation of ASIC pads, automatic connection and generation of simple Verilog modules, and so on. \n\nThe philosophy behind Perilog is that an IP core should be like a black box. Fitting it for a certain purpose should be as easy as defining the desired requirements. Connecting the cores, to become a system, should be as easy as drawing a block diagram. \n\nWith plain Verilog, the reality couldn't be further away. But by using Perlilog correctly, integration can be that simple. \n\nPerlilog introduces a new meaning to \"IP core\". It also introduces a different way to approaching the task of interfacing cores with each other. \n\nPerlilog was built to make core programming and integration intuitive tasks. As such, it is based on new, rather natural concepts, which one must get used to in order to gain the most of the tool. \n\nPerlilog is written in Perl, currently with no GUI. While the scripts, that the system consists of, are rather sophisticated, only plain Perl knowledge is needed to use its scripting capabilities. \n \n\n\n \n \n \n\n===== \n Bye bye Verilog? =====\n\nAbsolutely not. Verilog is still the language to define the functionality of the core. The final output of a design, which incorporates Perlilog, is perfectly normal Verilog files. \n\nPerlilog will do the following tasks instead of you: \n- Instantiation of modules \n- Connection between modules \n- Setting up modules' attributes (word width, address mapping on buses etc.) \n \n\n\n \n \n \n\n===== \n Status of the project =====\n\nThe current version is highly usable for general scripts, which involve Verilog code. As for sophisticated SoC generation, it still lacks script pieces, which makes it directly useful to connect real-life cores. \n\nThe project is known to be used by a few Verilog designers, and despite the official \"beta\" stage, no significant bugs have been found. The project appears to be reliable. \n\nFeatures are added to Perlilog whenever the system is shown to be incapable of meeting a reasonable need. Those who want to try Perlilog are encouraged to contact the maintainer directly. \n\nThe project comes with a guide, which includes all knowledge needed to enrich the tool, so it can connect real-life IP cores as promised above. \n \n\n\n \n \n \n\n===== \n Maintainer =====\n\nThe Perlilog project is maintained by its author, Eli Billauer. He can be reached at elib@flextronics.co.il.\n\nThe project and its documentation can be downloaded by clicking the \"Downloads\"\ntag on the navigation bar on the top of this page." language: Perl and Verilog license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - eli_billauer name: perlilog status: Beta svn-updated: Mar 10, 2009 updated: Mar 6, 2004 wishbone-compliant: 0 - category: Prototype board created: Mar 29, 2012 description: "===== \n Description =====\n\n\n\n\n\n\n\n La Plataforma de Hardware Reconfigurable persigue el fin de facilitar la ense\xC3\xB1anza de sistemas digitales y fabricaci\xC3\xB3n de prototipos basados en FPGA. Utiliza el chip XC3S200A de Xilinx y posee los perif\xC3\xA9ricos cl\xC3\xA1sicos utilizados en los primeros cursos de electr\xC3\xB3nica, pero adem\xC3\xA1s deja disponibles para el usuario, conectores con acceso directo a los pines de la FPGA.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCaracter\xC3\xADsticas\n\n\n\n\n\n\tFPGA: Xilinx Spartan-3A XC3S200A (encapsulado VQG100).\n\tMemoria PROM: Xilinx XCF02S.\n\tVoltaje de entrada: 5V.\n\tRelojes: cuatro relojes en total:\n\t\n\t\tClock 0: 50 MHz.\n\t\tClock 1: Seleccionable entre 16 MHz, 1 MHz, 500 kHz y 250 kHz.\n\t\tClock 2: Seleccionable entre 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz.\n\t\tClock 3: Seleccionable entre 3.9062 kHz, 1.9531 kHz, 976,56251 Hz.\n\t\n\tConectores con Entradas/Salidas de prop\xC3\xB3sito general: 28 pines en total.\n\tPerif\xC3\xA9ricos: 8 LEDs, 8 llaves (DIP switch), 4 pulsadores, Display de 7 segmentos cu\xC3\xA1druple, Puerto serie.\n\n\n\n\n\n\n\nPlacas\n\n\n\nEl proyecto comprende tres placas:\n\n\n\n\n\tPlaca PHR: Es la placa principal que tiene la FPGA, su memoria y perif\xC3\xA9ricos.\n\tPlaca S3Power: Regula la energ\xC3\xADa para alimentar la FPGA en forma adecuada.\n\tPlaca OOCDLink: Forma un canal de comunicaci\xC3\xB3n para transferir los dise\xC3\xB1os de la computadora a la FPGA.\n\n\n\n\n\n\n\n\n\t \n\n\n\xC2\xA0 \xC2\xA0 \n\n\n\t \n\n\n\n\n\n\n\nDiagrama de bloques del hardware\n\n\n\n \n\n\n\n\n\n\n\n\n\n\n\n\nPHR GUI\n\n\n\n\n\nPara transferir el dise\xC3\xB1o del usuario a la FPGA, PHR se sirve de las funciones de xc3sprog. No obstante su funcionalidad, xc3sprog puede resultar no intuitivo para el usuario principiante, por lo que se ofrece una interfaz gr\xC3\xA1fica para invocar a xc3sprog de una manera muy simple. \n\n\n\n\n\nEl software PHR GUI se puede descargar de la secci\xC3\xB3n de Descargas. Asimismo se puede obtener la Gu\xC3\xADa de instalacion y uso de la interfaz.\n\n\n\n\n\n\n\n\nEsquem\xC3\xA1ticos\n\n\tPlaca PHR\n\t\n\t\tPHRboard.pdf\n\t\tPHRboard-Power.pdf\n\t\tPHRboard-IOports.pdf\n\t\n\tPlaca OOCDLink\n\t\n\t\tOOCD_placa.pdf\n\t\n\tPlaca S3Power\n\t\n\t\tS3Proto_Power.pdf" language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - guanucoluis - maximo - solmedo - pampamatus - leopassetti - maximiq - Joaquin61_1 - juliovilca name: phr status: Mature svn-updated: Mar 28, 2015 updated: Mar 18, 2015 wishbone-compliant: 0 - category: System controller created: Oct 25, 2010 description: "===== \n Description =====\n\n\xE2\x80\x9Cpic\xE2\x80\x9D is a soft core, programmable interrupt controller which can be used as an interface between peripheral interrupt lines and processor IRQ line. One of the popular PIC available in market is Intel 8259. This core is not compatible with 8259. The core was designed based on my ideas of how a PIC operates and its requirements. The first version is a really basic core which can take 8 interrupts as input. The interrupt detecting methods currently supported are polling method and fixed priority method.\n\nA testbench code is provided with the core testing the design under both the modes.simulate the core using the given testbench and you should be able to know the signalling in the core.\n\nIf you find this design useful or if you want to give your feedback on this core then please send an email to lalnitt(at)gmail.com.I would very much appreciate it." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lal87 name: pic status: Alpha svn-updated: Oct 27, 2010 updated: Oct 27, 2010 wishbone-compliant: 0 - category: Other created: Dec 13, 2006 description: "===== \n Description =====\n\nPicoblaze's interrupt controller expands picoblaze's interrupt (up to 8-interrupt sources is supported).\n\nThe controller is put as input port. If interrupt occurs, the firmware will need to read this port, do some interrupt handling, turn-off/ACK the interrupt source and ACK the interrupt controller.\n\nThe firmware's sample code, along with testbenches and picoblaze implementation is within the project.\n\nFree beer for any excellent ideas that is accepted..(but you will need to visit me in Bali first ^^ )..\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Configurable input sources \n- Based on Picoblaze version 3.0 (KCPSM3)\n- Resource : 15-slices\n- Tested tools : WebISE v8.2i\n\n\n \n\n\n \n \n \n\n===== =====" language: VHDL license: 3-clause BSD licenselink: http://opensource.org/licenses/BSD-2-Clause maintainers: - kunilkuda name: picoblaze_interrupt_controller status: Design done svn-updated: Mar 10, 2009 updated: Dec 22, 2006 wishbone-compliant: 0 - category: Arithmetic core created: Sep 20, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - aTomek132888 name: pid_controler status: Stable svn-updated: Oct 13, 2010 updated: Sep 20, 2010 wishbone-compliant: 0 - category: DSP core created: Jul 10, 2012 description: "===== \n Description =====\n\nThe PID controller IP core performs digital proportional\xE2\x80\x93integral\xE2\x80\x93derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).\n\nFeatures\n\xE2\x80\xA2 16-bit signed coefficient and data input: Kp, Ki, Kd, SP and PV.\n\xE2\x80\xA2 32-bit signed u(n) output.\n\xE2\x80\xA2 Containing one high speed 32-bit prefix-2 Han-Carlson adder and one high speed pipelined 16x16-bit multiplier.\n\xE2\x80\xA2 Latency from input of PV to finished calculation and update of u(n) is 9 clock cycles.\n\xE2\x80\xA2 Ki, Kp, Kd, SP, PV can be updated anytime after reset.\n\xE2\x80\xA2 After every update of Kp or Kd, register Kpd which stores Kp+Kd will be calculated and updated.\n\xE2\x80\xA2 After every update of PV, calculation and update of e(n), e(n-1), sigma and u(n) will be triggered in sequence.\n\xE2\x80\xA2 Overflow register records overflow signals when calculating Kpd, e(n), e(n-1), u(n) and sigma.\n\xE2\x80\xA2 Using 2278 of 4608 (49%) Core Cells in Actel A2F200M3F FPGA and running at 100MHz clock frequency.\n\xE2\x80\xA2 Wishbone B4 compliant interface. Support 16-bit, 32-bit and 64-bit bus width." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - m99 name: pid_controller status: FPGA proven svn-updated: Dec 26, 2012 updated: Feb 3, 2015 wishbone-compliant: 1 - category: System on Chip created: Aug 4, 2007 description: "===== \n Description =====\n\nThis is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- PIF master support\n - Wishbone slave support\n - Burst transfers support \n - VHDL RTL\n - Fully synthesisable\n \n\n\n \n \n \n\n===== \n Status =====\n\n- RTL: Complete\n - Document: Complete" language: VHDL license: unknown maintainers: [] name: pif2wb status: Design done svn-updated: Mar 10, 2009 updated: Aug 7, 2007 wishbone-compliant: 1 - category: DSP core created: Feb 1, 2010 description: "===== \n Description =====\n\nPipelined FFT/IFFT 128 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 128 \xE2\x80\x93 complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.\n\n\nMain Features:\n\n\n128 -point radix-8 FFT\nForward and inverse FFT. \nPipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 310 clock cycles (440 clock cycles when the direct output data order), simultaneous loading/downloading supported\nInput data, output data, and coefficient widths are parametrizable in range 8 to 16\nTwo and three data buffers are selected.\nFFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX35-12 FPGA at 215 MHz clock cycle, and on Xilinx XC5VLX30-3 FPGA at 260 MHz clock cycle,respectively.\nFFT unit for 10 bit data and coefficients, and 3 data buffers occupies 4147 CLB slices, 4 DSP48 blocks, and 5 kbit of RAM in Xilinx XC4SX35 FPGA, and 1254 CLB slices 4 DSP48E blocks, and 5 kbit of RAM in Xilinx XC5VLX30 FPGA.\nOverflow detectors of intermediate and resulting data are present.\nTwo normalizing shifter stages provide the optimum data magnitude bandwidth. \nStructure can be configured in Xilinx, Altera, Actel, Lattice FPGA devices, and ASIC.\nCan be used in OFDM modems, software defined radio, multichannel coding.\n\n\nPlease, contact us if you wish to have this IP core modified or adjusted to meet your requirements.\n\n\nThis core is provided by Unicore Systems http://unicore.co.ua. To view our product list of commercial IP cores, please, follow this link" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unicore - aser name: pipelined_fft_128 status: Stable svn-updated: Feb 2, 2010 updated: Feb 2, 2010 wishbone-compliant: 0 - category: DSP core created: Feb 1, 2010 description: "===== \n Description =====\n\nPipelined FFT/IFFT 256 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 256 \xE2\x80\x93 complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.\n\n\nMain Features:\n\n\n256 -point radix-8 FFT\nForward and inverse FFT. \nPipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 580 clock cycles (839 clock cycles when the direct output data order), simultaneous loading/downloading supported\nInput data, output data, and coefficient widths are parametrizable in range 8 to 16\nTwo and three data buffers are selected.\nFFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX25-12 FPGA at 250 MHz clock cycle, and on Xilinx XC5SX25-12 FPGA at 300 MHz clock cycle, respectively.\nFFT unit for 10 bit data and coefficients, and 2 data buffers occupies 1652 CLB slices, 4 DSP48 blocks, and 2,5 kbit of RAM in Xilinx XC4SX25 FPGA, and 670 CLB slices 4 DSP48E blocks, and 2,5 kbit of RAM in Xilinx XC5SX25 FPGA, data buffers are implemented on the distributed RAM.\nOverflow detectors of intermediate and resulting data are present.\nTwo normalizing shifter stages provide the optimum data magnitude bandwidth. \nStructure can be configured in Xilinx, Altera, Actel, Lattice FPGA devices, and ASIC.\nCan be used in OFDM modems, software defined radio, multichannel coding.\n\n\nPlease, contact us if you wish to have this IP core modified or adjusted to meet your requirements.\n\n\nThis core is provided by Unicore Systems http://unicore.co.ua. To view our product list of commercial IP cores, please, follow this link" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unicore - aser name: pipelined_fft_256 status: Stable svn-updated: Feb 2, 2010 updated: Jul 30, 2014 wishbone-compliant: 0 - category: DSP core created: Jan 5, 2010 description: "===== \n Description =====\n\nPipelined FFT/IFFT 64 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 64 \xE2\x80\x93 complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.\n\n\nMain Features:\n\n\n64 -point radix-8 FFT.\nForward and inverse FFT. \nPipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 163 clock cycles, simultaneous loading/downloading supported.\nInput data, output data, and coefficient widths are parametrizable in range 8 to 16\nTwo and three data buffers are selected.\nFFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX25-12 FPGA at 250 MHz clock cycle, and on Xilinx XC5SX25-12 FPGA at 300 MHz clock cycle, respectively.\nFFT unit for 10 bit data and coefficients, and 2 data buffers occupies 1513 CLB slices, 4 DSP48 blocks, and 2,5 kbit of RAM in Xilinx XC4SX25 FPGA, and 700 CLB slices 4 DSP48E blocks, and 2,5 kbit of RAM in Xilinx XC5SX25 FPGA, data buffers are implemented on the distributed RAM.\nOverflow detectors of intermediate and resulting data are present.\nTwo normalizing shifter stages provide the optimum data magnitude bandwidth. \nStructure can be configured in Xilinx, Altera, Actel, Lattice FPGA devices, and ASIC.\nCan be used in OFDM modems, software defined radio, multichannel coding.\n\n\nPlease, contact us if you wish to have this IP core modified or adjusted to meet your requirements.\n\n\nThis core is provided by Unicore Systems http://unicore.co.ua. To view our product list of commercial IP cores, please, follow this link" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unicore - aser name: pipelined_fft_64 status: Stable svn-updated: Jan 27, 2010 updated: Feb 25, 2010 wishbone-compliant: 0 - category: DSP core created: Dec 22, 2013 description: "===== \n Description =====\n\nConveyored (result on every clock) elementary functions, implemented with CORDIC for demoscene project (http://www.youtube.com/watch?v=oh1_MzuFtdU). Number sizes in bits parametrized. Tested by eye, on DE2-115 board with VGA display. \nTesting environments for DE2-115 and Marsohod II dev. boards included. DE2-115 testing environment may contain some board related code copyrited by Terasic or Altera.\nTest projects for DE0 and DE0_nano dev. boards may be added on request." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - leshabirukov name: pipelined_fixed_point_elementary_functions status: FPGA proven svn-updated: Dec 31, 2013 updated: Jan 7, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Feb 12, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: pipelined_serial_port status: Empty updated: Feb 14, 2012 wishbone-compliant: 0 - category: Processor created: Nov 25, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - abhishekj name: pipelinedriscprocessor status: Empty updated: Nov 25, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Jan 28, 2013 description: "===== \n Description =====\n\nPortable Infrastructure Support for OpenCL on FPGA\nLooking for codeveloper who knows about OpenCL, contact jefflieu@fpga-ipcores.com" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jefflieu name: pisof status: Empty updated: Mar 23, 2013 wishbone-compliant: 0 - category: Other created: Apr 13, 2009 description: "===== \n Description =====\n\nThe Programmable Interval Timer Module, PIT, is a simple timer to generate a\nperiodic signal for a microcontroller system. This signal may be used for\na variety of purposes such as triggering the start of an Analog to Digital or\nDigital to Analog conversion, as a periodic system interrupt, real time clock\nupdate, or to synchronize the start of various other hardware processes.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\xE2\x80\xA2\t16 bit Main Counter with programmable modulo\n\xE2\x80\xA2\t15 bit Prescale Counter with programmable modulo selections\n\xE2\x80\xA2\tSlave mode for synchronizing multiple PIT modules\n\xE2\x80\xA2\tInterrupt or bit-polling \n\xE2\x80\xA2\tStatic synchronous design\n\xE2\x80\xA2\tFully synthesizable\n\xE2\x80\xA2\tParameterized so each instance can be optimized for size" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - rehayes name: pit status: Design done svn-updated: Oct 25, 2011 updated: Feb 10, 2010 wishbone-compliant: 1 - category: Processor created: Sep 25, 2001 description: "===== \n Description =====\n\nThe Plasma CPU is a small synthesizable 32-bit RISC microprocessor. It is currently running a live web server with an interrupt controller, UART, SRAM or DDR SDRAM controller, and Ethernet controller. The Plasma CPU executes all MIPS I(TM) user mode instructions except unaligned load and store operations (see \"Avoiding Limitations\" below). \n\nThis \"clean room\" CPU core is implemented in VHDL with either a two or three-stage pipeline. It is running at 25 MHz on a Xilinx FPGA and also verified on an Altera FPGA.\n \n\n\n \n \n \n\n===== \n Success Stories =====\n\nThe Plasma CPU along with the Plasma RTOS and TCP/IP protocol stack are now running a live Web Server on a Xilinx FPGA.\n\n\n\xC2\xA0\xC2\xA0\n\xC2\xA0\xC2\xA0\n\n \n\n\n \n \n \n\n===== \n Block diagram =====\n\n\n \n\n\n \n \n \n\n===== \n IMAGE: cpu.gif =====\n\nFILE: cpu.gif\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n Example Instruction =====\n\nThe CPU is implemented with a two or three stage pipeline with an additional optional stage for memory read and writes. (Using the three stage pipeline enables \"pipeline.vhd\" which delays some control signals into the next stage.)\n\nAn ADD instruction would take the following steps:\nStage #0:\n\n 1. The \"pc_next\" entity passes the program counter (PC) to the \"mem_ctrl\" entity which fetches the opcode from memory.\n\nStage #1:\n\n 2. The memory returns the opcode.\n\nStage #2:\n\n 3. \"Mem_ctrl\" passes the opcode to the \"control\" entity.\n 4. \"Control\" converts the 32-bit opcode to a 60-bit VLWI opcode and sends control signals to the other entities.\n 5. Based on the rs_index and rt_index control signals, \"reg_bank\" sends the 32-bit reg_source and reg_target to \"bus_mux\".\n\nStage #3 (part of stage #2 if using two stage pipeline):\n\n 6. Based on the a_source and b_source control signals, \"bus_mux\" multiplexes reg_source onto a_bus and reg_target onto b_bus.\n 7. Based on the alu_func control signals, \"alu\" adds the values from a_bus and b_bus and places the result on c_bus.\n 8. Based on the c_source control signals, \"bus_mux\" multiplexes c_bus onto reg_dest.\n 9. Based on the rd_index control signal, \"reg_bank\" saves reg_dest into the correct register.\n\nStage #4 (part of stage #3 if using two stage pipeline):\n\n 10. Read or write memory if needed.\n\n \n\n\n \n \n \n\n===== \n Plasma Version 3 Features =====\n\nThe Plasma Version 3 core now contains a bidirectional serial port, interrupt controller, and hardware timer. Version 3.5 added a DDR SDRAM controller, Ethernet MAC, and Flash interface. There is C and assembly code for the Plasma Real-Time Operating System -- a fully preemptive RTOS supporting threads, semaphores, mutexes, message queues, timers, heaps, an interrupt manager, ANSI C library, single precision floating point library, TCP/IP protocol stack, and Web server.\n \n\n\n \n \n \n\n===== \n List of Files =====\n\n\n\n\n FILE\n PURPOSE (Directory: vhdl)\n\n\n code.txt\n Input opcodes for the test bench -- test.axf \"converted\"\n\n\n mlite_pack.vhd\n Constants and Functions Package\n\n\n tbench.vhd\n Test Bench that uses plasma.vhd\n\n\n plasma_if.vhd\n Top level interface to Xilinx or Altera FPGA\n\n\n plasma_3e.vhd\n Top level interface to Xilinx Spartan-3E with DDR\n\n\n -ddr_ctrl.vhd\n DDR controller\n\n\n -plasma.vhd\n CPU core with RAM and UART\n\n\n --cache.vhd\n Optional 4KB cache\n\n\n --ram.vhd\n Internal RAM for Altera FPGA\n\n\n --ram_xilinx.vhd\n Internal RAM for Xilinx FPGA\n\n\n --uart.vhd\n UART (can pause CPU if needed)\n\n\n --eth_dma.vhd\n Ethernet MAC with DMA\n\n\n --mlite_cpu.vhd\n Top Level VHDL for CPU core\n\n\n ---alu.vhd\n Arithmetic Logic Unit\n\n\n ---bus_mux.vhd\n BUS Multiplex Unit\n\n\n ---control.vhd\n Opcode Decoder\n\n\n ---mem_ctrl.vhd\n Memory Controller\n\n\n ---mult.vhd\n Multiplication and Division Unit\n\n\n ---pc_next.vhd\n Program Counter Unit\n\n\n ---reg_bank.vhd\n Register Bank for 32, 32-bit Registers\n\n\n ---shifter.vhd\n Shifter Unit\n\n\n\n\n\n FILE\n PURPOSE (Directory: tools)\n\n\n makefile\n Makefile for the PC for creating \"code.txt\"\n\n\n plasma.h\n Plasma header file for register addresses\n\n\n boot.asm\n Initializes $gp and $sp, clears .bss\n\n\n opcodes.asm\n Tests all the MIPS I(tm) opcodes\n\n\n convert.c\n Converts test.axf to code.txt\n\n\n ram_image.c\n Creates Xilinx RAM file ram_image.vhd from ram_xilinx.vhd and code.txt\n\n\n bootldr.c\n Serial port boot loader that can download another program\n\n\n\n etermip.c\n Terminal program to download code and transfer Ethernet packets\n\n mlite.c\n Simulates the CPU in software\n\n\n bintohex.c\n Converts test.exe to code[0-3].hex for lpm_ram for Altera FPGA\n\n\n test.c\n Test program (opcodes) for the CPU core\n\n\n pi.c\n Calculates the first 16 digits of PI\n\n\n count.c\n Test program that counts using words\n\n\n ddr_init.c\n Initialize the DDR chip\n\n\n cpu.gif\n Block Diagram\n\n\n\n\n\n FILE\n PURPOSE (Directory: kernel)\n\n\n makefile\n Makefile for Plasma RTOS\n\n\n rtos.h\n Header file for Plasma RTOS\n\n\n rtos.c\n Plasma pre-emptive Real-Time Operating System\n\n\n libc.c\n ANSI C library subset\n\n\n math.c\n Single precision floating point library\n\n\n uart.c\n Serial port driver\n\n\n rtos_test.c\n Test the RTOS functions\n\n\n tcpip.h\n TCP/IP header file\n\n\n tcpip.c\n TCP/IP protocol stack\n\n\n ethernet.c\n Ethernet MAC\n\n\n http.c\n Web server\n\n\n filesys.c\n File system\n\n\n flash.c\n Flash access\n\n\n netutil.c\n FTP server/client and telnet server\n\n\n\n \n\n\n \n \n \n\n===== \n Downloads =====\n\nThe Opencores Subversion web page can create the 130KB plasma_latest.tar.gz file containing all the latest code.\n \n\n\n \n \n \n\n===== \n Tools =====\n\nThe MIPS(tm) GCC ELF compiler for Windows is available gccmips_elf.zip (2.4MB). The OpenCores server wouldn't let me save zip files so I had to rename it with an '.odt' extention. Rename the file from gccmips_elf.odt to gccmips_elf.zip before unzipping the files into the trunk\\gccmips_elf directory. Add this directory to your executable PATH environment: set path=%PATH%;YOUR_DIR\\trunk\\gccmips_elf\nIf you use Windows and don't have a Microsoft C compiler for Windows, you will need pre-compiled versions of the tools (rename as tools.zip) which should be placed in the tools directory. \nYou may also need a Windows version of gmake. Rename the file gmake_zip.odt to gmake.zip before unzipping.\n \n\n\n \n \n \n\n===== \n Supporting Documentation =====\n\nSee the tabs at the top for additional build instructions:\n\nThe Plasma CPU instruction set\nBuilding the tools\nAdditional Linux GNU MIPS tools\nBuilding the Plasma RTOS\nBuilding the Plasma TCP/IP stack\n\n\nThe implementation is based on information found in: \n\n\"MIPS RISC Architecture\" by Gerry Kane and Joe Heinrich\n\"The Designer's Guide to VHDL\" by Peter J. Ashenden\n\n\nThe MIPS I(TM) instruction set can be found by:\n\nGo to the MIPS Technologies, Inc. Web site http://www.mips.com/.\nUnder the Products menu, click on Resource Library.\nClick on Product Materials in the submenu on the left.\nClick on MIPS Architecture from the next menu on the left.\nFinally, click on the link for \"MIPS32\xC2\xAE Architecture for Programmers Volume II: The MIPS32\xC2\xAE Instruction Set (.pdf)\".\n\n\n \n\n\n \n \n \n\n===== \n Big/Little Endian =====\n\nThe CPU core operates in Big Endian mode by default. To operate in Little Endian mode, change \"little_endian\" from \"00\" to \"11\" in the file mem_ctrl.vhd. \n \n\n\n \n \n \n\n===== \n Bus Interface =====\n\nAll signals are active high. Here are the signals for writing a character to address 0xffff when using a two stage pipeline:\n entity mlite_cpu is port(clk : in std_logic; reset_in : in std_logic; intr_in : in std_logic; address_next : out std_logic_vector(31 downto 2); --for synch ram byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0); mem_pause : in std_logic); end; --entity mlite_cpu\n Program: addr value opcode ============================= 3c: 00000000 nop 40: 34040041 li $a0,0x41 44: 3405ffff li $a1,0xffff 48: a0a40000 sb $a0,0($a1) 4c: 00000000 nop 50: 00000000 nop\n intr_in mem_pause reset_in byte_we Stages ns address data_w data_r 40 44 48 4c 50 3600 0 0 00000040 00000000 34040041 0 0 1 3700 0 0 00000044 00000000 3405FFFF 0 0 2 1 3800 0 0 00000048 00000000 A0A40000 0 0 2 1 3900 0 0 0000004C 41414141 00000000 0 0 2 1 4000 0 0 0000FFFC 41414141 XXXXXX41 1 0 3 2 4100 0 0 00000050 00000000 00000000 0 0 1\n \n\n\n \n \n \n\n===== \n Synthesis =====\n\nThe CPU core was synthesized for several different FPGAs:\nXilinx Spartan-3E Starter Kit Board with a XC3S500 used 2021 of 4656 slices (43 percent). Image includes DDR and Ethernet controllers.\nRemoving the multiplication unit reduces the size by 558 slices.\nXilinx Spartan-3 Starter Kit Board with an Xilinx XC3S200 Spartan-3 FPGA.\nAltera EP20K200EFC484-2X FPGA.\n \n\n\n \n \n \n\n===== \n Status =====\n\n\nAll MIPS I(TM) instructions are implemented and tested (except the unsupported previously patented unaligned load and store opcodes).\nCurrently running on an Altera EP20K200EFC484-2X FPGA and a Xilinx XC3S500 and XC3S200 FPGA.\nAlso running on a Xilinx Spartan-3E starter kit with DDR SDRAM, Ethernet MAC, and Flash Controller.\nRunning at 50 MHz on newer Xilinx FPGAs with three stage pipeline.\nSee \"opcodes.asm\" for regression test.\nSupports Interrupts.\nIncludes several C test programs: Calculating PI; Prime Numbers; Showing Numbers Using Words; the Plasma RTOS; and single precision floating point library.\n\n\n \n\n\n \n \n \n\n===== \n Disclaimer =====\n\nMIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. OpenCores and Steve Rhoads are not affiliated in any way with MIPS Technologies, Inc.\n \n\n\n \n \n \n\n===== \n Legal Notice =====\n\nThe Plasma CPU project has been placed into the public domain by its original author and is free for commercial and non-commercial use. \n\nThis software is provided \"as is\" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed.\n \n\n\n \n \n \n\n===== \n Avoiding Limitations =====\n\nThis section describes how to avoid the two main limitations of the Plasma CPU core. The first limitation is that unaligned load and store operations are not supported since they were patented. This means that when loading or storing 32-bit values the memory address must be on a 32-bit aligned address. [The patent for the unaligned memory access instructions expired Dec 23, 2006.]\n\nMost RISC CPUs have limited support for unaligned memory accesses. The GCC MIPS compiler does not normally generate unaligned memory accesses. Try compiling a C program and then look in the listing file if any of these MIPS instructions are used: LWL, LWR, SWL, or SWR. If needed, there is a GCC patch to never generate unaligned memory accesses at ultra-embedded->GCC Modifications.\n\nThe second main limitation of the Plasma CPU is that exceptions (BREAK and SYSCALL opcodes) must not be placed immediately after a branch instruction (in the branch delay slot). The main uses for exceptions are software interrupts for debugger support and calling operating system calls. \n \n\n\n \n \n \n\n===== \n Plasma CPU Web Articles =====\n\nSeveral groups have published how they have used the Plasma CPU.\n\nBook: System-level Test and Validation of Hardware/software Systems\nIEEE: Low-Cost Software-Based Self-Testing of RISC Processor Cores\nIEEE: A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA\nIEEE: Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores\nIEEE: Software-Based Self-Testing of Embedded Processors\nIEEE: Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors\nIEEE: Floating Point Hardware for Embedded Processors in FPGAs\nResearch: Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report\n\nAchieving Composability in NoC-Based MPSoCs \nThrough QoS Management at Software Level\n\n\nPredictive Dynamic Frequency Scaling for\nMulti-Processor Systems-on-Chip\n\n\nProviding Better Multi-Processor Systems-on-Chip Resources Utilization by Means\nof Using a Control-Loop Feedback Mechanism\n\n\nA Self-adaptive communication protocol allowing\nfine tuning between flexibility and performance in\nHomogeneous MPSoC systems\n\n\nEvaluating the Impact of Task Migration in Multi-Processor\nSystems-on-Chip\n\n\nExploration of task migration techniques for\ndistributed memory MultiProcessor Systems on Chips\n\nThesis: Efficient Verification of Bit-Level Pipelined Machines Using Refinement\nSpanish: Design, Evaluation and Implementation of a Multicore Processor\nPortuguese: Harvard Architecture?\nPortuguese: Report of the Draft Amendment of the Organization of Interface\nUsage: Plasma soft processor on the Spartan board\nVerilog: Veritak VHDL to Verilog Translator\nVerilog: YF32 - A simple 32-bit CPU SOC Platform [original Chinese]" homepage: http://plasmacpu.no-ip.org:8080/ language: VHDL license: Public domain maintainers: - rhoads name: plasma status: FPGA proven svn-updated: Aug 30, 2014 updated: Sep 24, 2014 wishbone-compliant: 0 - category: Communication controller created: Aug 13, 2010 description: "===== \n Description =====\n\nThe intention of the project is the development of a bus bridge, which enables the usage of WB compliant IP cores in a system, which uses the Processor Local Bus (PLB) as system and peripheral bus. The PLB-to-WB (PLB2WB) Bridge enables the access to slaves on the WB side for masters on the PLB side. \n\n\n\n\nFeatures: \n - separate clock domains for PLB and WB \n - separate resets for PLB and WB possible\n - PLB address pipelining (optional) \n - PLB fixed length burst transfers (only words, optional) \n - PLB line transfers (optional) \n - WB B.3 classic cycles (block and single, block cyckes are optional) \n - flexible address offset \n - handling of delayed write errors on WB side\n - transfers interrupts to PLB side\n\n\n\n\n \n\n\n \n \n \n\n===== \n File and Folder Structure =====\n\nYou can checkout all files with the following command:\n\n\n\nsvn co http://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk/\n\n\n\n\n\nBecause this bridge was intended to be used with Xilinx Platform Studio (XPS), the file and folder structure is a little bit different to other OpenCores projects. But if you are going to use XPS, just add \n\n\n\nsystems/EDK_Libs\n\n\n\nto your module search path. \nIf you are not going to use XPS, you can find all VHDL source files in \n\n\n\nsystems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/\n\n\n\n\n\nSome simulation systems for testing the functionality are located in\n\n\n\nsystems/test_system_sim/\n\n\n\nand \n\n\n\nsystems/dev_system_sim/\n\n\n \ncontains a simulation system to implement new features. \n\n\nIf you are using a Xilinx toolchain with Xilinx FPGAs, the folder\n\n\n\ncoregen/fifo_generator/\n\n\n\ncontains a Ruby script and a configuration file to auto-generate all necessary FIFOs (see documentation for more information).\n\n\nLast but not least, you will find the documentation in\n\n\n\ndoc/\n\n\n \n\n\n\n\n \n\n\n \n \n \n\n===== \n Development Status =====\n\nPLEASE NOTE: THIS PROJECT HAS NOT BEEN UPDATED SINCE 2010. THE PLB BUS IS NOT USED ANYMORE IN CURRENT XILINX SOCS AND THERE IS NO MORE NEED FOR THIS PROJECT.\n\nThis project was started as a student work at HS-Pforzheim University (Germany). \nThe project was finished in the middle of august 2010.\nThe PLB-to-WB Bridge is implemented and all functionality is tested via RTL simulation. \nIn addition, basic functionality is tested in a SoC for a Virtex-5 FPGA.\n\nBecause there is never an end, the following list shows some open issues\n - Implementation of WB B.4 interface\n - Implementation of WB registered feedback bus cycles" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - feddischson name: plb2wbbridge status: FPGA proven svn-updated: Aug 14, 2010 updated: Feb 23, 2014 wishbone-compliant: 1 - category: System on Chip created: Jul 25, 2008 description: "===== \n PLBv46 to Wishbone Bridge =====\n\nThis is a simple CoreConnect PLBv46 to Wishbone bridge that can allow Wishbone peripherals to be used on Xilinx processor designs. It conforms to the sub-set of the PLBv46 specification adopted by Xilinx in the EDK.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- PLBv46 Slave Attachment (non bursting)\n - 32-bit interface to PLBv46 bus.\n - 32-bit interface to Wishbone bus.\n\n- Supports\n - Handling of Retries.\n - User can set the retry wait time.\n - User can set number of times to retry\n - Result of unsuccessful retry is a PLBv46 bus error ack.\n - Handling of Bus Errors\n - User can set how long to wait for a bus-time out (no WB ack)\n - Results in a PLBv46 Bus Error\n \n\n\n \n \n \n\n===== \n Status =====\n\n- New" language: VHDL license: custom licensetext: "XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\"\nAS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND\nSOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,\nOR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,\nAPPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION\nTHAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,\nAND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE\nFOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY\nWARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE\nIMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR\nREPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF\nINFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE.\n" maintainers: - sasten name: plbv46_to_wb_bridge status: FPGA proven svn-updated: Mar 10, 2009 updated: Mar 5, 2010 wishbone-compliant: 1 - category: Communication controller created: Dec 16, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - pela name: plexcon status: Empty updated: Dec 2, 2014 wishbone-compliant: 1 - category: Testing / Verification created: Apr 14, 2013 description: "===== \n Description =====\n\nPlTbUtils makes it easy to create automatic, self-checking simulation testbenches, and to locate bugs during a simulation.\nIt is a collection of functions, procedures and testbench components that simplifies creation of stimuli and checking results of a device under test.\n\n\n\n\n\nFeatures:\n\nSimulation status printed in transcript windows as well as in waveform window (error count, checks count, number and name of current test, etc).\nCheck procedures which output meaningful information when a check fails.\nClear SUCCESS/FAIL message at end of simulation.\nEasy to locate point in time of bugs, by studying increments of the error counter in the waveform window.\nUser-defined information messages in the waveformwindow about what is currently going on.\nTranscript outputs prepared for parsing by scripts, e.g. in regression tests.\nReduces amount of code in tests, which makes them faster to write and easier to read.\n\n\n\n\n\n\nIt is intended that PlTbUtils will constantly expand by adding more and more functions, procedures and testbench components. Comments, feedback and suggestions are welcome to pela.opencores@gmail.com .\n\n\n\n\n\nThe project page on the web is http://opencores.org/project,pltbutils\n\n\n\n\nSubversion repository URL is http://opencores.org/ocsvn/pltbutils/pltbutils/trunk\n\n\n\n\nSubversion export command is svn export http://opencores.org/ocsvn/pltbutils/pltbutils/trunk pltbutils\n\n\n\n\nSee the PlTbUtils Specification.\n\n\n\n \n\n\n \n \n \n\n===== \n A quick look =====\n\n\n\n\n\n\n\nDuring a simulation, the waveform window shows current test number, test name, user-defined info, accumulated number och checks and errors. When the error counter increments, a bug has been found in that point in time.\n\n\n\n\n\n\n\n\n\n\n\nThe transcript window clearly shows points in time where the simulation starts, ends, and where errors are detected. The simulation stops with a clear SUCCESS/FAIL message, specifically formatted for parsing by scripts.\n\n\n\n\n\n\n\n\n\n\n\nThe testcase code is compact and to the point, which results in less code to write, and makes the code easier to read, as in the following example.\n\n\n\n\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse work.pltbutils_func_pkg.all;\n\n-- NOTE: The purpose of the following code is to demostrate some of the \n-- features in PlTbUtils, not to do a thorough verification.\narchitecture tc1 of tc_example is\nbegin\n p_tc1 : process\n begin\n startsim(\"tc1\", pltbutils_sc);\n rst <= '1';\n carry_in <= '0';\n x <= (others => '0');\n y <= (others => '0');\n \n testname(1, \"Reset test\", pltbutils_sc);\n waitclks(2, clk, pltbutils_sc); \n check(\"Sum during reset\", sum, 0, pltbutils_sc);\n check(\"Carry out during reset\", carry_out, '0', pltbutils_sc);\n rst <= '0';\n \n testname(2, \"Simple sum test\", pltbutils_sc);\n carry_in <= '0';\n x <= std_logic_vector(to_unsigned(1, x'length));\n y <= std_logic_vector(to_unsigned(2, x'length));\n waitclks(2, clk, pltbutils_sc);\n check(\"Sum\", sum, 3, pltbutils_sc); \n check(\"Carry out\", carry_out, '0', pltbutils_sc); \n \n testname(3, \"Simple carry in test\", pltbutils_sc);\n print(pltbutils_sc, \"Bug here somewhere\");\n carry_in <= '1';\n x <= std_logic_vector(to_unsigned(1, x'length));\n y <= std_logic_vector(to_unsigned(2, x'length));\n waitclks(2, clk, pltbutils_sc);\n check(\"Sum\", sum, 4, pltbutils_sc); \n check(\"Carry out\", carry_out, '0', pltbutils_sc);\n print(pltbutils_sc, \"\");\n\n testname(4, \"Simple carry out test\", pltbutils_sc);\n carry_in <= '0';\n x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length));\n y <= std_logic_vector(to_unsigned(1, x'length));\n waitclks(2, clk, pltbutils_sc);\n check(\"Sum\", sum, 0, pltbutils_sc); \n check(\"Carry out\", carry_out, '1', pltbutils_sc);\n\n endsim(pltbutils_sc, true);\n wait;\n end process p_tc1;\nend architecture tc1;" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - pela name: pltbutils status: Design done svn-updated: Feb 2, 2015 updated: Feb 2, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Jun 20, 2011 description: "===== \n Description =====\n\nC code for generating a stand-alone population counter with user-defined size (number of input bits) and latency (number of clock cycles) in VHDL." language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - NikosAl name: popcount_gen status: Stable svn-updated: Jun 27, 2011 updated: Jul 12, 2011 wishbone-compliant: 0 - category: System controller created: Oct 27, 2010 description: "===== \n Description =====\n\nLarge electronic systems often use multiple supply voltages that must come up and go down in a specified order. Also, it must be made sure that the system is not powered up only partly for a prolonged time. This power sequencer is composed of equal slices, one for each supply stage." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - dk4xp name: powersupplysequencer status: Design done svn-updated: Oct 27, 2010 updated: Apr 23, 2014 wishbone-compliant: 0 - category: Communication controller created: Feb 17, 2015 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jeaander name: ppi status: Empty updated: Feb 17, 2015 wishbone-compliant: 0 - category: Processor created: May 14, 2002 description: "===== \n Description =====\n\nMicrocontroller core compatible with 16C55 and 16F84.\n\nSingle cycle VHDL implementations of 16C55 and 16F84. Four times faster than the original MCUs, otherwise timing compatible. Watchdog and EEPROM are not implemented. Both implementations use the configurable PPX16 12/14 bit instruction width core, other MCUs using the same instruction set can easily be implemented by creating a new top level.\n\nThere are utilities included that can create VHDL ROMs for simulation and synthesis. The utilites create generic ROMs that can be used for simulation and for synthesis with Leonardo and also Xilinx specific ROMs that can be used for XST synthesis.\n\nBatch files for runnning XST and Leonardo synthesis can be found in syn/xilinx/run/.\n\nBefore you can run the scripts you need to compile hex2rom and xrom or download binaries from here.\nYou must also put your hex file in either sw/c55.hex or sw/f84.hex.\nIf you need to change target device and settings you need to edit the batch files and some of the files in syn/xilinx/bin/.\n\nThe Leonardo batch file also creates the VHDL ROMs you need to run the Modelsim compile script in sim/rtl_sim/bin/.\n\nIf you want to create ROMs without running the scripts use the following parameters for 16C55:\nhex2rom [-b] inputfile.hex ROM55 9l12s > ROM55.vhd\nAnd these for 16F84:\nhex2rom [-b] inputfile.hex ROM84 10l14s > ROM84.vhd\nHex2rom can read intel/motorola hex and binary files.\n\nBrowse source code here.\nDownload latest tarball here.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- High performance, > 30 MIPS in Spartan 2 -5\n- Supports synchronous ROM/RAM (Xilinx Block RAM compatible)\n- Parametric\n- Technology independent\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested in FPGA" language: VHDL license: 3-clause BSD licenselink: http://opensource.org/licenses/BSD-2-Clause maintainers: - jesus name: ppx16 status: Stable svn-updated: Mar 10, 2009 updated: Jan 19, 2007 wishbone-compliant: 0 - category: Testing / Verification created: Apr 15, 2011 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - slai name: prbs_suite status: FPGA proven svn-updated: Jul 18, 2011 updated: Dec 3, 2011 wishbone-compliant: 0 - category: Crypto core created: May 5, 2011 description: "===== \n Description =====\n\nPresent is a lightweight block cipher dedicated to implement in Hardware. It was developed by Knudsen team.\n\n\n\n\nThis cipher operates on the 64 bit text with use of 80 bit key. It uses S/P blocks and xor operations for encryption and key update through 32 rounds.\n\n\n\n\nIn this project I created:\n- Present module dedicated to 32 bit Hardware (32 bit I/O and working under state machine)\n\xC2\xA0\xC2\xA0 This is much for 'archive' state due to it was part of my students project, and it is not a 'pure' implementation of PRESENT.\n- \"Pure\" Present implementation \"as is\" in the Knudsen article\n- Present cipher Decoder\n- Some helpful programs written in Java used for testing VHDL modules\n- Some modules used for testing communication with PC\n- Full documentation for each subproject\n\n\n\n\n\nThese modules were tested on Digilent Spartan 3E Starter Boart (Spartan XC3S500E) - except 32 bit I/O version\n\n\n\n\nIf You have any questions write me an email gajos@opencores.org." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gajos name: present status: FPGA proven svn-updated: Sep 17, 2014 updated: Sep 17, 2014 wishbone-compliant: 0 - category: Crypto core created: Jan 18, 2011 description: "===== \n About Present Block Cipher =====\n\nPresent is a lightweight block cipher designed for hardware constrained applications such as RFID tags and Smart Cards.\nThis cipher is a true example of SPN ciphers. The block size is 64 bits, key size can be either 80 or 128 bits and the number of rounds is 31.\nThe S-Box used in Present is a 4-bit to 4-bit S-Box which is invoked both in the substitution layer and in the key scheduling routine.\nThis project entails an encryption-only implementation of Present cipher with key size equal to 80 bits." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rameli name: present_encryptor status: Stable svn-updated: Feb 17, 2011 updated: Feb 18, 2011 wishbone-compliant: 0 - category: ECC core created: Nov 6, 2005 description: "===== \n Product Code Iterative Decoder =====\n\nAn iterative decoder for Product Code, this decoder works for two dimensional product code.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Preliminary Check using http://asim.lip6.fr/recherche/alliance/ (Alliance 5.0)\n- Synthesized using ISE Xilinx 6.3i for target XC2V2000-FF896-4\n- Bit errors rates:\n - SNR 100 dB got 0000 errors from 10000 samples\n - SNR 009 dB got 0000 errors from 10000 samples\n - SNR 006 dB got 0012 errors from 10000 samples\n - SNR 003 dB got 0279 errors from 10000 samples\n - SNR 000 dB got 1314 errors from 10000 samples\n- http://www.opencores.org/pstats.cgi/view/product_code_iterative_decoder (Project status)" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - arif_endro name: product_code_iterative_decoder status: Design done svn-updated: Jun 25, 2010 updated: Mar 19, 2010 wishbone-compliant: 0 - category: Communication controller created: Jan 31, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - roelofburger name: profibus_dp_protocol_for_fpga status: Empty updated: Jan 31, 2011 wishbone-compliant: 0 - category: Prototype board created: Jun 15, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - xprot name: prospart status: Empty updated: Jun 15, 2011 wishbone-compliant: 0 - category: Other created: Sep 25, 2001 description: "===== \n Description =====\n\nThe PS/2 interface project (ps2_interface) is interface hardware to allow using a ps2 mouse or keyboard in your project. The code is written in Verilog, and was sythesized into a Xilinx SpartanII XC2S200 chip. Debugging was done with an HP16500 series logic analyzer, and there is no testbench for these interfaces.\n\nFor the keyboard interface, there is translation from scan codes into ASCII characters, for those scan codes that have ASCII equivalents. Also, the keyboard interface traps the left/right shift scan codes, and produces uppercase ascii when appropriate. This means that the keyboard interface can be used with a serial port core to create an ASCII terminal type of interface on chip. The keyboard interface is bi-directional, so the user can send commands to change the operation of the keyboard, or light up the \"Num Lock\", \"Caps Lock\" and \"Scroll Lock\" LEDs as desired.\n\nThe mouse interface implements \"hot plugging\" of the mouse. This means that the mouse may be unplugged and then re-connected, and the interface hardware will recognize this, and issue the command to put the mouse into \"streaming mode\" so that it starts sending out data packets. The position updates from the mouse are provided in terms of two 10-bit signed quantities: an X-increment and a Y-increment. In actual use, the Y-increment appears to be negative of the sense you would expect (i.e. moving the mouse up produces a negative increment...) For simplicity, this interface only sends one command to the mouse, which is the command to put it into streaming mode.\n\nThe design team of ps2_interface welcomes any kind of help and feedback on these cores. If you are interested in further development of this project, please contact us.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- These cores have been coded completely, synthesized and tested for correct operation (and debugged!) inside a Xilinx XC2S200 chip. The tools used for development were the Xilinx Foundation 3.1i (non-ISE) tools. \n- These cores were also tested using the free Xilinx Webpack ISE (9/10/01) tools. However, the \"rs232_syscon.v\" module has to be modified to work with ISE (only important for the \"soc\" type downloads). The ASCII characters must be coded as numbers in ISE... \n- There are no technology-dependent elements used in these cores. \n- The cores consume about 100 Xilinx Virtex slices each (depending on parameters) \n- The cores are parameterized to allow changing timer values to accomodate different clock speeds. \n- The code has comments. The interface to the mouse and keyboard use tri-state I/O for the bi-directional clk and data lines. These lines must have pullup resistors! (the value is not very critical.) \n- The interface is currently implemented using state-machines (no processor is involved.) \n- \"Debounce\" states are provided in the state machines, to make the interfaces more tolerant of different types of mice and keyboards.\n\nIn the future, a bare bones version of the keyboard interface could be implemented which implements only receive, to save on resource utilization and eliminate the bi-directional interface. For the mouse interface, this is impossible, since the mouse requires a \"streaming mode\" command in order to begin sending its data packets." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jclaytons name: ps2 status: Stable svn-updated: Mar 10, 2009 updated: Mar 10, 2013 wishbone-compliant: 0 - category: Communication controller created: Dec 16, 2011 description: "===== \n Description =====\n\nThis core aims at implementing host side of IBM PS/2 keyboard and mouse communication protocol.\n\nTo run testbench:\n%> iverilog -DSYS_CLOCK_HZ=100000 -o ps2_host_testbench ps2_host_testbench.v\n%> vvp ps2_host_testbench -lxt2\n%> gtkwave ps2_host_testbench.lxt" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tesla name: ps2_host_controller status: FPGA proven svn-updated: Dec 19, 2011 updated: Dec 19, 2011 wishbone-compliant: 0 - category: Other created: Oct 22, 2010 description: "===== \n Description =====\n\nThis project is a Logic Unit that works as an interface between the PS/2 keyboard and any other microprocessor. It outputs the scan code of the key being pressed, it count the number of pressings.\nAs an FPGA test , this project includes displaying the last 2 keys pressed on 7-Segment Display Units, it displays the numbers of pressings on some other LEDs.\n \n\n\n \n \n \n\n===== \n Status =====\n\nTill Now, it outputs the Hexa Scan Code on the 7-Segment Display Units on an FPGA Kit for test and debugging purposes." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - OmarMokhtar name: ps2_keyboard_interface status: FPGA proven svn-updated: Dec 3, 2010 updated: Dec 3, 2010 wishbone-compliant: 0 - category: Communication controller created: Oct 27, 2003 description: "===== \n Description =====\n\nCompact and optimized PS/2 controller for Keyboard and Mice.\n\nPS2 Core is build modular. There are one principal module that contains all communications logic, this can be used alone for hardware-only desings or used together with an wishbone bus top-level module for use in microprocessor systems.\n\nThe main goal of PS2 Core is create an fully functional PS2 controller with a very efficient use of logic and resources but without loss any functionality. The wishbone top-level has been designed to be as small as possible, giving an very simple and easy to use interface to the microprocessor. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Technology independent.\n- Fast and small PS2 controller.\n- Can be used on hardware-only or microprocessor designs.\n- Wishbone compatible with the top-level interface module.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- PS2 low level module completed and tested on FPGA\n- Preliminary Wishbone support\n \n\n\n \n \n \n\n===== \n download =====\n\nBrowse project CVS repository" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - danielqg name: ps2core status: Beta svn-updated: Mar 10, 2009 updated: Dec 9, 2010 wishbone-compliant: 1 - category: Other created: May 28, 2012 description: "===== \n Description =====\n\nPSG16 is an audio interface circuit for use within a programmable system to interface the system to an audio output. It supports four ADSR audio channels with a wavetable option.\n \n\n\n \n \n \n\n===== \n Features =====\n\n-\tfour ADSR / wave table channels\n-\tprogrammable frequency and pulse width control\n-\t0.06 Hz frequency resolution\n-\tattack, decay, sustain and release\n-\ttest, ringmod, sync and gate controls\n-\tfive voice types: triangle, square, pulse, noise and wave\n-\texponential decay and release" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: psg16 status: Planning svn-updated: May 28, 2012 updated: May 28, 2012 wishbone-compliant: 0 - category: Other created: Sep 25, 2001 description: "===== \n Description =====\n\nPWM/Timer/Counter (PTC) IP core is a user-programmable PWM, Timer and Counter controller. Its use is to implement functions like Pulse Width Modulation (PWM), timer and counter facilities. \n \n\n\n \n \n \n\n===== \n Features =====\n\nThe following lists the main features of PTC IP core: \n\n- 32-bit counter/timer facility \n- single-run or continues run of PTC counter Programmable PWM mode \n- System clock and external clock sources for timer functionality \n- HI/LO Reference and Capture registers \n- Three-state control for PWM output driver \n- PWM/Timer/Counter functionalities can cause an interrupt to the CPU \n- WISHBONE SoC Interconnection Rev. B compliant interface \n\nMore information about the WISHBONE SoC and a full specification can be found here. \n\nFor further information, questions and general discussions related to the PTC core, please visit the Cores Mailing list.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Verilog RTL and verification suite under development \n- The Specification is complete: ptc_spec.pdf (see Downloads)" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - lampret name: ptc status: Stable svn-updated: Mar 10, 2009 updated: Nov 17, 2006 wishbone-compliant: 1 - category: Other created: Sep 13, 2011 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - panda_emc - plem name: pulse_processing_algorithm status: FPGA proven svn-updated: Sep 21, 2011 updated: Dec 5, 2011 wishbone-compliant: 0 - category: Other created: Sep 19, 2012 description: "===== \n Description =====\n\nPulse Width Modulator\nFeatures\n\xE2\x80\xA2 Work as one PWM or one timer.\n\xE2\x80\xA2 16 bits main counter.\n\xE2\x80\xA2 PWM/Timer can choose between Wishbone interface clock or external clock as working clock.\n\xE2\x80\xA2 PWM can choose between dedicated duty cycle input or internal register as source of duty cycle.\n\xE2\x80\xA2 Duty cycle and period can be changed at runtime.\n\xE2\x80\xA2 Hosted through Wishbone slave interface.\n\xE2\x80\xA2 Working clock's frequency can be divided to at most 1/65535 of original frequency.\n\xE2\x80\xA2 Period register also serves as timer target register when module is in timer mode." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - m99 name: pwm status: FPGA proven svn-updated: Oct 5, 2012 updated: Oct 13, 2012 wishbone-compliant: 1 - category: Other created: Apr 10, 2012 description: '' language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - open_core_slava name: pwm_controller status: Empty updated: Jun 17, 2012 wishbone-compliant: 0 - alternate-download: https://bitbucket.org/liubenyuan/pycs/get/7a45d60aff58.zip category: Arithmetic core created: Apr 27, 2013 description: "===== \n Description =====\n\nThe Compression Framework for Physiological Signal Telemonitoring. In this project, we had implemented the (1) state-of-the-art jpeg2000 standard compression for 1D signal, and the Le Gall 5/3 wavelet was used and a lifing scheme is implemented. (2) Compressive Sensing based signal compression. (3) Accompanied matlab code for simulation and data generation. Available at Bitbucket rightnow https://bitbucket.org/liubenyuan/pycs" homepage: https://bitbucket.org/liubenyuan/pycs language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - liubenyuan name: pycs status: FPGA proven updated: Nov 5, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Jul 10, 2003 description: "===== \n Description =====\n\nBefore You read\nThis is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed algorithms please refer to the full article... (see PDF file from downloads.)\n\nOverview\nOperation of multiplication is very important in microelectronics. Each modern microprocessor has this operation within its instruction set, and advanced microprocessors have special multiplication units, that perform multiplication during 1 synchronization period(cycle). Especially valuable multiplication is in DSP processors, where it is practically main operation. Performance of any DSP processor is defined with delays in it MAC (multiply and accumulate) unit. So efficiency of multiplication is very important.\n\n\n\n\nMethodology Overview.\nThe idea of algorithms is as follows. Unsigned multiplicands A and D may be represented in following form: A*D = (B * 2n + \xC3\xB3) * (E * 2n + F), where n \xE2\x80\x93 any number that is satisfied with following conditions:\n\n2n 2n \xC3\xB3 n; \nF n.\n\nThis approach is applied recursively to all multiplicands until multiplication result may be calculated easily (for example, until multiplicands have dimension of one or two bits). \n\n\n\n\xC2\xABPyramid\xC2\xBB algorithm.\nHave a look at basic formula A*D = (B * 2n + \xC3\xB3) * (E * 2n + F). In case n=m-1, C and D have dimension of one bit. This basic formula is applied recursively to\nall further multiplicands. As a result dimension of multiplicands is decreased by one at every iteration. That is why the algorithm was named as \xE2\x80\x9Cpyramid\xE2\x80\x9D. \n\n\n\n\nModified \xC2\xABpyramid\xC2\xBB algorithm.\nModified \xC2\xABpyramid\xC2\xBB algorithms is differ from prototype with value of n = m-2 and with dimension of operands C \xC3\x89 D equal to 2 bits. As may be seen Modified pyramid algorithm implementation such small change gives valuable results improvement for area allocation.\n \n\n\n \n \n \n\n===== \n Features =====\n\n \"Pyramid\" integer multiplication unit characteristics\nThe algorithm was written in VHDL, synthesized within Synopsys Design Compiler on 0.35u CMOS library. The data of the allocation areas are given only for a combinational part of algorithms. Operands Width Delay(ns) Gates allocated 8 9.8 890 16 19.85 2815 32 37.34 10550 64 No data No data \n\n\n\n\n\"Optimized pyramid\" multiplication IP core characteristics\nThe algorithm was written in VHDL, synthesized within Synopsys Design Compiler on 0.35u CMOS library. The data of the allocation areas are given only for a combinational part of algorithms. Operands Width Delay(ns) Gates allocated 8 9.92 700 16 17.7 2300 32 33.94 8580 64 69.78 33300 \n \n\n\n \n \n \n\n===== \n Links =====\n\nThese cores are developed and provided by ASIC reseach department member of DeverSYS Corp., Vladimir V.Erokhin. More usefull fundamental (and not only) FREE IP Cores can be found at DeverSYS web www.deversys.com." language: VHDL license: unknown maintainers: - vladvas name: pyramid_unit status: Stable svn-updated: Mar 10, 2009 updated: Jul 17, 2003 wishbone-compliant: 0 - category: Library created: Dec 6, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qaztronic name: qaz_libs status: Planning svn-updated: Mar 19, 2015 updated: Dec 6, 2014 wishbone-compliant: 0 - category: DSP core created: Aug 26, 2009 description: "===== \n Description =====\n\nThis project is a digital signal processing (DSP) implementation of a circuit that provides periodic samples of both sine and cosine waveforms. Technically, it is called a \"discrete-time discrete-amplitude binary recursion oscillator.\" Although that description sounds complex, the operation of the circuit is not complicated. This particular implementation uses a multiplier and an adder, and can be configured to produce sine/cosine output at the desired frequency and with the specified number of bits per sample.\n\nThe sine and cosine outputs represent the projections of a rotating vector, or complex phasor if you like, along the real and imaginary axes of a 2-dimensional Cartesian coordinate space. The vector is rotated a fixed amount with each new sample. Is this just as clear as mud?\n\nWell, it does take some multipliers to implement the rotation matrix, but otherwise, it's a fairly quick implementation...\n\nThe number of samples per cycle is given as a generic quantity, and the initial values for the vector are zero for sin_o, and +1 for cos_o. The numerical quantities are represented as signed 2's complement numbers, in Q1.(AMPL_BITS-1) notation.\n\nThe frequency of the oscillator has been fixed at the lowest possible value. The intention is that by varying the sample rate, sine and cosine waves of different frequencies can be produced. For example, if the system clock is at 50 MHz, and SAMPLES_PER_CYCLE=1000, then it should be possible to create output at 50 kHz by setting the clk_en_i input to '1'. For lower frequencies, just provide a stream of clock enable pulses at the appropriate rate.\n\nThis VHDL code has been tested via simulation, and synthesis in actual hardware. The rounding technique used in this module did not keep the output amplitude from decaying, so a once-per-cycle \"amplitude reset\" is included to ensure that the output is stable over time." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - fteichert - jclaytons name: qo status: FPGA proven svn-updated: Jun 8, 2014 updated: Jun 8, 2014 wishbone-compliant: 0 - category: Processor created: Nov 16, 2010 description: "===== \n Description =====\n\nProject Qrisc32 is academic research and implementation of 4 stages risc cpu. Testbench runs 3 different sorting algorithms on qrisc32 and shows cycles for each turn. For observing instruction set, please refer to \"risc_report.pdf\" file. For running simulation you can use Modelsim with run_sim.tcl file.\nQrisc32 is implemented by using SystemVerilog." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vinogradov name: qrisc32 status: Alpha svn-updated: Dec 5, 2011 updated: Dec 5, 2011 wishbone-compliant: 0 - category: Other created: Nov 6, 2009 description: "===== \n Description =====\n\nVHDL Implementation of a quadrature decoder module with a Wishbone bus interface. This module has the following features:\nUPDATED per version v1.0.0 Release (July 2010)\n-- July, 2010\n-- 1)Release version v1.0.0\n-- 2)Changes from prior release:\n-- a) Bit 3 of the Quadrature Control Register (offset 0x00) is now changed\n-- functions, to enable / disable of the Index Zero Count function. When\n-- the bit is 0, an index event does not affect the count. When the bit is\n-- 1, and index events are permitted, the internal quadrature count is set\n-- to 0.\n-- b) Added control bit 13, Index Read Count Bit. When set to 0, no count\n-- is latched. When set to 1, and index events are permitted, the internal\n-- quadrature count is automatically latched to the QRW (offset 0x08)\n-- register when an index event is true. This is VERY useful for detection\n-- of missed encoder counts, as you can assume that the delta counts in\n-- between each index event is fixed, so any deviation from the expected\n-- amount indicates that there were missed encoder counts.\n-- 3)Tested the FPGA implementation with a real encoder, verified proper\n-- operation with count frequencies up to 1.3MHz (50MHz system clock)\n-- This test used an instrumented motor driver, with a hardware qudrature\n-- decoder in parallel with this encoder module. This module did not miss\n-- any counts with a 2048 quad counts / rev encoder running at 40e3 rpm.\n-- 4) Fixed a minor bug with the QCR_PLCT bit and the QCR_INZC bit; under\n-- a specific condition that both the PLCT bit and the INZC bit were asserted\n-- at the same clock cycle, the PLCT would have been executed while the INZC\n-- event would have been missed.\n-- 5) Added an additional feature: Quadrature Count Compare Match Event;\n-- when the CCME bit is set in the QCR register, and the quadrature count\n-- matches the QRW register, a signal is asserted and the status bit of the\n-- QSR register is set. This event can also generate an interrupt.\n\nPREVIOUS UPDATES------------------------------------------------------------\n\n--Wishbone module for interfacing to optical encoders\n--4X Quadrature decoding of encoder signals\n--Programmable external interrupt request output\n--Dedicated 'latch quadrature count' input for multi-axis syncronization\n--Memory mapped control, status, and count registers\n--Verified on a Xilinx FPGA with a soft core processor (Altium TSK3000)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - scottnortman name: quad_decoder status: FPGA proven svn-updated: Jul 15, 2010 updated: Jul 12, 2010 wishbone-compliant: 1 - category: Arithmetic core created: Feb 16, 2009 description: "===== \n Description =====\n\nQuadratic_func is a fully pipelined quadratic polynomial that computes the relation y = ax^2 + bx + c. On each rising-edge of the clock (when en is high), the coefficients and input x term are sampled at the function inputs. The result has a latency of 3 clock cycles. All inputs to the function are 8-bit signed fractions, with the generic parameter 'fw' specifying the number of fraction bits. The output result is a 24-bit signed fraction. If integer arithmetic is preferred, then the parameter fw should be set to 0. For larger bit-widths, the design can easily be scaled up to suit the application.\n\n\n\n\n\n\n\nThe quadratic core is ideal for curve-fitting applications such as estimating SIN/COS or ATAN. It provides a useful alternative to LUT-based estimation or it may be used in conjunction with a small LUT to generate more precise results. As an example, the following plot shows the output result of the function: y = 0.86x^2 - 0.22x + 0.3 in the range [-2, 2]. For a full description of the core, please review the following Quadratic function pdf datasheet.\n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Computes the relation y = ax^2 + bx + c\n- Signed 8-bit fixed-point input\n- Signed 8-bit fixed-point coefficients\n- Signed 24-bit fixed-point output\n- Configurable number of fraction bits\n- Dynamic coefficients updated every clock cycle\n- No internal loss of precision (no rounding or truncation)\n- Fully pipelined architecture\n- Result has a 3 clock-cycle latency\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Fully tested and complete\n- Future versions to support generic input data and coefficient widths as well as fraction width\n \n\n\n \n \n \n\n===== \n Help and Support =====\n\nSimon Doherty is a Senior Design Consultant at ZIPcores If you require further assistance regarding the implementation of this core, you may contact me directly via my Opencores email alias at sdoherty@opencores.org. Alternatively you may contact me through customer support at ZIPcores." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - sdoherty name: quadratic_func status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 26, 2011 wishbone-compliant: 0 - category: Communication controller created: Dec 23, 2003 description: "===== \n Description =====\n\nThis is a very simple project for reading a quadrature device, such as an optical encoder. The counter is initialized to zero, and then counts up and down when valid quadrature is present at the inputs\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Simple VHDL for beginners; well documented; shows use of hierarchical design.\n- Count limited only by bit length of counter vector; simple to count very large values\n- VHDL Implementation of Xilinx application note #012 (xapp012.pdf)\n- NPL project file for immediate evaluation in Xilinx ISE/Webpack tools\n- Questions/Comments: http://www.franks-development.com\n \n\n\n \n \n \n\n===== \n Project Contents =====\n\n- QuadratureCounter.vhd, top-level VHDL\n- QuadratureDecoder.vhd, sub-level file\n- Quadrature.npl, Xilinx project file for ISE/Webpack\n- Quadrature.ucf, optional constraints file for pin assignment" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - franksdevel name: quadraturecount status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 23, 2004 wishbone-compliant: 0 - alternate-download: http://liberatedcontent.de/openhardware/r2000-r29.tar.gz category: Processor created: Jan 12, 2008 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ameziti name: r2000 status: Alpha svn-updated: Aug 9, 2009 updated: Nov 24, 2011 wishbone-compliant: 1 - category: Crypto core created: Sep 25, 2001 description: "===== =====\n\nThanks to Mr. Thomas Blum (tblum@ece.wpi.edu) who provide his documentation about High Radix Montgomery modular exponentiation.\n \n\n\n \n \n \n\n===== \n Description =====\n\nRSA Cryptosystem is widely used in information technology. It encrypts\nand decrypts messages using public key mechanism. The security of this\ncryptosystem is based on the fact that it's very difficult to factorize\nlarge prime number.\n\nRSA algorithm was proposed in 1978 by Rivest, Shamir, and\nAdleman. Since 1978 its algorithm has changed to get an efficient\ncryptosystem. The high radix Montgomery algorithm is used to get the\nfaster calculation of modular exponential which used in RSA algorithm.\nThis algorithm was proposed by Peter Montgomery in 1985 and now widely used in modern RSA cryptosystem. \n \n\n\n \n \n \n\n===== \n Specifications =====\n\n- Uses public key and private key to encrypt and decrypt messages\n- Uses 512 bit private key exponent(the minimum size recommended by RSA Laboratories)\n- Uses Fermat prime as public key exponent(as recommended by International Telecommunications Union)\n- Uses 512 bit modulus n\n- Blocks 512 bit to encrypt plaintext and decrypt ciphertext\n- Uses Radix 256 Montgomery reduction modul and Radix 256 Blakley multiplication modul to calculate the modular exponential\n \n\n\n \n \n \n\n===== \n Design stages =====\n\n- Making core specification\n- Designing behavioral and structural\n- Converting to symbolic layout\n- Verifying and simulating\n- Making full report \n \n\n\n \n \n \n\n===== \n Documentation =====\n\n- see Download section\n \n\n\n \n \n \n\n===== \n The cores =====\n\n1. Montgomery modular multiplication module\n2. Montgomery modular exponentiation module" language: '' license: unknown maintainers: - frans025 name: radixrsa status: Empty svn-updated: Mar 10, 2009 updated: Oct 14, 2001 wishbone-compliant: 0 - category: Prototype board created: Mar 29, 2006 description: "===== \n An inexpensive PCI FPGA development board =====\n\nThis is a port of the Opencores PCI core ported to the Enterpoint Raggedstone1 PCI card.\n\nThis is a very inexpensive card: (~$100 USB). You can order one from Enterpoint:\nhttp://enterpoint.co.uk/moelbryn/raggedstone1.html\n \n\n\n \n \n \n\n===== \n A PCI based FPGA card =====\n\n-Inexpensive\n -PCI core works\n -All the code is in CVS\n -Uses the OC PCI core\n \n\n\n \n \n \n\n===== \n Version is in cvs =====\n\nTo check this project out of cvs:\ncvs -d:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous checkout raggedstone" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - jcarr name: raggedstone status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 8, 2007 wishbone-compliant: 1 - category: Memory core created: Apr 24, 2009 description: "===== \n Overview =====\n\nThis is a wishbone B3 compliant RAM memory. The memory array is defined as a 32 bit memory. This gives two valuable benefits\n\n\n\n\nmemory array can be mapped into one block RAM with no need for byte select during synthesis\nmemory content can be initialized with CPU instructions with no need to split content into byte chunks" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback name: ram_wb status: Design done svn-updated: Apr 30, 2009 updated: Mar 10, 2011 wishbone-compliant: 1 - category: Processor created: Apr 26, 2012 description: "===== \n Description =====\n\nRaptor64 is a 64-bit multi-context RISC cpu that supports hyper-threading. There are 16 register sets that the processor automatically switches between at high speed. The processor is fully pipelined with a nine-stage pipeline. Stages: IF/RF/EX/M1/M2/M3/M4/WB/TR. Communication with memory is via a 32 bit MIG bus. The processor has a 8kB instruction cache and 16kB data cache. Also included is a 16 entry TLB for memory management. The processor uses 32 bit instructions.\n\nI've created two versions of the processor a non-hyper-threaded version (sc) in addition to the hyper-threaded multi-context(mc) one. \n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 32 entry 64 bit general register file\n- 32 bit opcodes (4 per 128 bits) \n- SQRT,Multiply/Divide/bit field/ + all the regulars\n- conditional move, exec,\n- explicit I/O instructions ( also useful for uncached access)\n- immediate constants may be built using SETLO,SETMID,SETHI instructions\n- two address modes, displacement (d15[ra]) and scaled indexed (d2[ra+rb*scale])\n- 16 segmentation registers\n- SimpleMMU - 32 tasks supported with mapping of 128MB space into 256kB pages\n- 64 single bit semaphores\n- 8kiB instruction cache, 16kiB data cache\n- 8 way 8 entry set associative TLB\n- single cycle execution of most instructions (loads stall the pipeline)\n- branch prediction with a 256 entry branch history table\n- return address stack prediction\n- internal Harvard architecture\n- communicates externally using a 64-bit WISHBONE bus\n \n\n \n\n\n \n \n \n\n===== \n Software =====\n\nIn the works is currently a high level language compiler for a language similar to 'C'. Several additional keywords have been added (eg. interrupt). Well I finally fed the output of the compiler through the assembler. A couple of bug fixes later the sieve is able to run from SD Card.\nThere is also an assembler (also a work in progress).\nTiny Basic is available in the boot rom. Works with a few bugs yet.\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nCurrently the processor is running code in an FPGA. The bootrom is slowly expanding. Numerous software and processor fixes have taken place. Still a long way to go. The processor is being revamped to use a 32 bit ISA, it was originally a 42 bit ISA.\n\nThe core is running on an Atlys board, and now able to load a boot program from an SD Card. Hopefully that will speed the software development up. Prior, the only software was updated by updating a Verilog source file, requiring the entire system to be rebuilt for a software update.\n\nThe ISA is still under constant review; it may change to use an 8-bit master opcode field as opposed to 7-bits. There's lots of instructions I'd like to add, and no room with only 7 bits.\n\n\n \n\n\n \n \n \n\n===== \n Pics =====" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: raptor64 status: Planning svn-updated: Feb 18, 2013 updated: Feb 16, 2013 wishbone-compliant: 0 - category: Library created: Jun 7, 2010 description: "===== \n Description =====\n\n\"ratpack\" is a rational arithmetic package written in VHDL.\n\nCurrently, the \"ratpack\" package implements the following:\n\n - the RATIONAL data type.\n - to_rational: construction function of a rational given two integers\n (numerator and denominator).\n - int2rat: conversion function of an integer to its rational\n representation.\n - numerator: extracts the numerator of a rational number.\n - denominator: extracts the denominator of a rational number.\n - \"+\", \"-\", \"*\", \"/\": implementation of the basic arithmetic\n operations for rationals.\n - abs: extracts the absolute value of a given rational number.\n - \">\", \"=\", \" rationals.\n - gcd: computes the greatest common divisor of two integers (positive,\n covers the pathological case of division by zero).\n - mediant: computes the mediant rational of two given rationals.\n\n\"ratpack\" is distributed along with two VHDL testbenches: a simple one \n(ratpack_tb1.vhd) and a testbench generating the Farey series of orders 1 to 12 \n(ratpack_tb2.vhd).\n \n\n\n \n \n \n\n===== \n Contact =====\n\nFeel free to visit http://www.nkavvadias.com for updates to my development projects.\n\nContact me at: nikolaos-dot-kavvadias-at-gmail-dot-com" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - kavi name: ratpack status: Beta svn-updated: Feb 20, 2014 updated: Feb 20, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Jan 7, 2011 description: "===== \n Description =====\n\nRay Tracing : A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General.\n\nThe Main Goal of this project is to create an engine to Render 3D models. This engine is made over HW/SW. What Im planning to do is to make a RTL generic enough to plug it along with a processor, by means of a bus or any connector the developer wishes. \n\nSo the RTL's published on this page will describe the HW part of the engine. I don't know, YET, if I'm allowed to upload SW source code. If I am, for sure I will, but if not a proper project page will be set on the next days. I will publish, as mentioned, the soruce code for a NIOS II processor, and that will be the Rendering Engine SW portion.\n\nSo, what I expect is to achieve a simple HW portion of the Rendering Engine, that serves on its original purpose -a Ray Tracing Rendering Engine- but in the near future, I would hope to see the engine to be used for General Purposes. \n\nAnyway It will be my mayor achievment if some day these RTL's are taken as examples in order to learn VHDL and Hardware description and Hardware Design." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jguarin2002 name: raytrac status: Mature svn-updated: Oct 27, 2012 updated: Jul 25, 2011 wishbone-compliant: 0 - category: Crypto core created: May 17, 2012 description: "===== \n Description =====\n\nRC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then start outputting one-byte of random stream for every clock (output_read signals valid output in K). Based on RC4 implementation in wikipedia." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ortegaalfredo name: rc4-prbs status: FPGA proven svn-updated: Jun 2, 2013 updated: Feb 26, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Nov 4, 2010 description: "===== \n Description =====\n\nReal time video stream filter, I have a first version of the filter which is working on FPGA, The filtering operation was simplified due to the real time filtering otherwise the output video will show a delay. A first version of the code and the description will be provided soon, and more people wishing to work on the project are very welcome. Send me an email and we will discuss work planning and schedule." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - kochtana name: real_time_video_stream_filter status: Empty updated: Nov 4, 2010 wishbone-compliant: 0 - category: ECC core created: Jul 21, 2011 description: "===== \n Description =====\n\n\nThis tool working on WinXP is used to generate verilog-RTL for Reed-Solomon Codec.\n- Selectable Decoder/Encoder/Both\n- Symbol width 3,4,5,6,7,8,9,10,11\n- Primitive polynomial\n- Erasure Enable/Disable\n- Configurable Data I/F\n- Automatically available testbench\n- Distributed under the GPL license\n\nIf you need more customize or hi-performance IP, please let us know.\ninfo@syslsi.com" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - issei name: reed_solomon_codec_generator status: FPGA proven svn-updated: Jul 28, 2011 updated: Aug 8, 2012 wishbone-compliant: 0 - category: ECC core created: Jul 5, 2009 description: "===== \n Description =====\n\n\xE2\x80\xA2 Reed Solomon Decoder (204,188), with T=8.\n\xE2\x80\xA2 Input codeword length is 204 bytes and output length is 188 bytes.\n\xE2\x80\xA2 Corrects up to 8 byte errors per input codeword.\n\xE2\x80\xA2 Code generator polynomial: (x + \xCE\xBB) (x + \xCE\xBB^2) (x + \xCE\xBB^3) ... (x + \xCE\xBB^16).\n\xE2\x80\xA2 Field generator polynomial: x^8+ x^4+ x^3+ x^2+1.\n\xE2\x80\xA2 This version of the Reed Solomon core is distributed under the GPL license.\n An optimized and considerably more advanced version, which may be\n customized on request for different code generator polynomials, is\n available under a commercial license.\n\n\n \n\n\n \n \n \n\n===== \n Synthesis Results =====\n\n\xE2\x80\xA2 Design estimated Gate count is 52,400 gates and total memory bits are 12,432 bits.\n\n\xE2\x80\xA2 Synthesis Results on Xilinx Spartan 3A DSP:\n\n o Number of occupied slices: 3,397/23,872 (14%).\n o Best achievable clock is 12.084 ns.\n o Total block RAMs RAMB16BWERs: 11/126 (8%).\n\n\xE2\x80\xA2 Synthesis Results on Altera Stratix III L150F1152C2:\n\n o Logic utilization 5 %.\n o Combinational ALUTs 3,372 / 113,600 (3 %).\n o Memory ALUTs 256 / 56,800 ( o Dedicated logic registers: 2,935 / 113,600 (3 %).\n o Total block memory bits 12,432 / 5,630,976 ( o Best achievable clock is 3.977 ns.\n\n \n\n\n \n \n \n\n===== \n Deliverables =====\n\no Verilog RTL files.\no Simulation test bench.\no MATLAB script to generate test vectors.\n\n \n\n\n \n \n \n\n===== \n About the authors =====\n\nVarkon Semiconductors\nTel: 1-732-447-8611\nWeb Site: varkonsemi.com" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: reed_solomon_decoder status: FPGA proven svn-updated: Apr 11, 2010 updated: Nov 23, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Jun 15, 2010 description: "===== \n Description =====\n\nThis project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems. \nSource code provided in C++ (trunk/cpp-source) and Bluespec(trunk/bluespec-source)." language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - abhiag name: reedsolomon status: FPGA proven svn-updated: Jun 16, 2010 updated: Jun 16, 2010 wishbone-compliant: 0 - category: System on Chip created: Jan 15, 2005 description: "===== \n rfid tag and reader =====\n\nVerilog models of RFID card / reader. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- hash lock\n- blinded anticollision\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- implemented Stephen Weis RFID tag model http://theory.lcs.mit.edu/~cis/theses/weis-masters.pdf \n- it's bad but no good reader model yet (need help)" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - andy0120042004 name: rfid status: Beta svn-updated: Mar 10, 2009 updated: Dec 27, 2011 wishbone-compliant: 0 - category: Communication controller created: Oct 16, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - radou name: rgmii_mac status: Empty updated: Oct 17, 2014 wishbone-compliant: 0 - category: Arithmetic core created: May 16, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: rhp status: Planning svn-updated: Jun 1, 2011 updated: Mar 29, 2012 wishbone-compliant: 0 - category: Crypto core created: Feb 18, 2002 description: "===== \n Description =====\n\nThe NIST has selected cipher Rijndael as AES on October 20, 2000 based on the combination security, performance, efficiency, ease of implementation and flexibility. The algorithm has been designed by Joan Daemen and Vincent Rijmen. Rijndael is a symmetric-key iterated block cipher, length of the block is 128 bits and length of the key can be specified to be 128, 192 bit, 256 bits. \n\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- encryption block (done)\n- decryption block (done) \n\nYou can also download the pdf format here\n \n\n\n \n \n \n\n===== \n Compability =====\n\nThe core complies to FIPS 197. This document can be downloaded here : FIPS 197" language: '' license: unknown maintainers: - yusadana - john - sarwono name: rijndael status: Empty svn-updated: Mar 10, 2009 updated: Dec 4, 2002 wishbone-compliant: 0 - category: Communication controller created: Jan 8, 2013 description: "===== \n Overview =====\n\nRapidIO is a standard protocol defined by the RapidIO Trade Association used to build high-speed embedded networks. It is an open standard and can be downloaded on www.rapidio.org.\n\nThis project was founded 2013 when Bombardier decided to release some of its RapidIO IP-blocks to the general public. It contains basic IP-block to build switches, endpoints and switches with embedded endpoints.\n \n\n\n \n \n \n\n===== \n VHDL IPs =====\n\nRioSwitch.vhd - Contains a RapidIO switch IP. \nIt has been synthesized to Spartan-6.\n\nRioWbBridge.vhd - Contains a RapidIO to Wishbone bridge IP. \nIt has been synthesized to Spartan-6 and Virtex-6.\n\nRioPacketBuffer.vhd - Contains a RapidIO packet queue IP with support for a sliding window and one priority level.\nIt has been synthesized to Spartan-6 and Virtex-6.\n\nRioSerial.vhd - Contains a basic RapidIO LP-serial protocol IP. The LP-serial protocol parts, which are independent of the physical transmission channel, have been isolated from the PCS (Physical Coding Sublayer) to make it easy to tailor to different architectures. High-speed transceivers are usually device specific. This also makes it possible to write a custom made PCS tailored to for example a proprietary transmission channel.\nIt has been synthesized to Spartan-6 and Virtex-6.\n\nsrio_pcs_struct.vhd - Contains a RapidIO PCS IP written to use a Xilinx GTX tranceiver.\nIt has been synthesized to Virtex-6.\n\nRioPcsUart.vhd - Contains a RapidIO PCS IP written to use a standard 8-bit data, no parity, one stop-bit UART. It is similar to PPP using byte-stuffed data to send control characters. It can be used to interface a standard microcontroller with a UART using the software stack below.\nIt has been synthesized to Spartan-6.\n\n \n\n\n \n \n \n\n===== \n C software =====\n\nriostack.c - A software implementation of the transmission independent LP-serial protocol. It can be compiled to either respond to maintenance packets and act as an endpoint or in transparent mode to make it forward all received packets to higher levels of software. The transparent mode can be used to simulate any RapidIO network topology and endpoints in software.\nHas been compiled to both ARM and Freescale devices.\n\nriocodecuart.c - A software implementation matched to the VHDL IP RioPcsUart.vhd to be used in a microcontroller. It serves as a template to write a custom codec that suites the particular processor architecture.\nHas been compiled to both ARM and Freescale devices." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - magro732 - qermit name: rio status: Beta svn-updated: Jan 25, 2015 updated: Mar 1, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Aug 16, 2011 description: "===== \n Description =====\n\nIt is a 32 bit RISC processor with (3,0)register-register architecture with memory access using LD and SD instruction. The design has branch penalty of 1 clock cycle. The architecture is a 5-stage pipelined structure with forwarding implemented to minimize Data Hazards. It has separate Instruction and Data Memory. It has been tested with 10 testcases and total number of clock cycles were calculated for each instruction set. The results conform to the expected count." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gazelle name: risc status: Empty updated: Mar 19, 2012 wishbone-compliant: 0 - category: Processor created: May 7, 2002 description: "===== \n Description =====\n\nThe risc16f84 project is intended to provide a small, easy to use microcontroller in Verilog. The original code was VHDL, but I have done a wonderful translation of it into good clean Verilog code. (Well, I think it is wonderful, anyway.) The VHDL code was called \"CQPIC\" and it was published in 1999 by Sumio Morioka of Japan, in the December 1999 issue of \"Transistor Gijutsu Magazine.\" I did the translation by hand, and then tested the design in actual hardware by running C code on it, and looking for correct behavior. I realize that this is not 100% test coverage, but I have found and fixed several bugs by this method -- including an error in the carry bit logic of the original code! There are four separate versions of the microcontroller presented here. The \"original\" one is called \"risc16f84.v\" and it includes all the logic needed to implement the entire 16f84 chip functionality as published in the original article. \n\n\n\nHowever, I have realized over time, that a person using a microcontroller inside of an FPGA does not have the same constraints (i.e. on port sizes, number of pins, multiple functions needed on each pin, etc.) as the original chip designers, and so I have taken liberty in the other three versions, to simplify the logic by removing items that may not be wanted inside of an FPGA or ASIC implementation. For example, there is a version called \"risc16f84_lite.v\" which has no interface for the EEPROM...\n\n\n\nAnother version, called \"risc16f84_small.v\" further eliminates the multiple interrupt sources present on the original chip (since in a PIC there is only one interrupt vector defined, so interrupt service routines must do some \"checking\" anyway to determine the source of an interrupt - why bother having separate inputs defined? Just make up your own interrupt structure and use it the way you like inside of your chip!)\n\n\n\n Finally, the fourth version, called \"risc16f84_clk2x.v\" further removes the port A and port B interfaces, since you can create as many ports as you like inside of your own chip. Toward this end, \"risc16f84_clk2x.v\" also includes an \"auxiliary\" bus interface, allowing the microcontroller to access 64k bytes of registers, ports and hardware peripherals, all defined within their own address space -- not within the limited register space of the PIC microcontrollers. I have used it to address a screen with 12288 pixels, and each pixel has its own address. It is easy to define addresses for the auxiliary bus components in most PIC code generation tools, so this works out nicely.\n\n\n\nThe code is written in Verilog, and was sythesized into a Xilinx SpartanII XC2S200 chip. Debugging was done in actual hardware, with an HP16500 series logic analyzer, and there are no simulation testbenches for these modules.\n\n\n\n\nThe hardware debugger used to test this core is \n \n\n\n \n \n \n\n===== \n Features =====\n\n- The original \"risc16f84.v\" supports execution with 4 clocks per instruction, as in PIC microcontrollers.\n- The \"risc16f84_clk2x\" version uses only 2 clocks per instruction.\n- Xilinx DPRAM blocks were used to implement the processor register space and program ROM. These RAMs are dual-ported, so I have mapped the other port into the \"auxiliary bus\" space.\n- Debugging is aided by the use of \"rs232_syscon.v\" which is a hardware \"monitor\" that allows read/write of addresses on the auxiliary bus. Since program memory is mapped into the auxiliary bus, programs can be downloaded via rs232_syscon.\n- Since the registers and all useful peripherals are present on the auxiliary bus, single stepping and hardware breakpoints are implemented through the rs232_syscon interface (a serial port connects to a terminal window.)\n- I have been downloading C code through the serial port, in the form of rs232_syscon write commands.\n- A PERL script transforms s-record files into rs232_syscon write commands.\n- The cores are parameterized. \n- The code has good comments.\n- Interrupts are supported and tested in \"risc16f84_clk2x.v\"\n \n\n\n \n \n \n\n===== \n Status =====\n\n- The \"risc16f84_clk2x.v\" core has been coded completely, synthesized and tested for correct operation (and debugged!) inside a Xilinx XC2S200 chip.\n- The \"risc16f84_clk2x.v\" core was tested running C-code at 65.28 MHz (approx. 32 MIPS), and uses 321 Virtex slices. This test is not exhaustive, I only bumped up the clock speed until the program \"froze up.\"\n- The entire debugging environment, including risc16f84_clk2x, rs232_syscon, single stepping and breakpoint logic and registers, consumes about 900 Virtex slices, and runs at frequencies up to 65.28 MHz or so, when implemented inside of a Xilinx XC2S200 FPGA.\n- There is no documentation yet. Please email me if you have specific questions and you cannot figure out how the modules work. The code has some good comments in it.\n- \"risc16f84_clk2x.v\" has been rewritten somewhat. It supports a single edge-triggered interrupt now.\n- The debugging environment has been updated to include support for generating slow interrupts (user controlled bit) and periodic interrupts (narrow pulses.)\n- The entire SoC was compiled using Xilinx WebPack (XST synthesizer) free tools! It works at various clock rates, and has an automatic BAUD rate circuit that resynchronizes when the user changes speeds.\n- A user reported a mathematical error on subtract opcodes. This was verified and fixed. Thanks to Stefan Frank for diligently reporting the bug!\n- New \"README.TXT\" file describes some of the helpful hints and arcane tips for running the design. Enjoy!" language: Verilog license: custom licensetext: "THE WORK (AS DEFINED BELOW) IS PROVIDED UNDER THE TERMS OF THIS CREATIVE COMMONS PUBLIC LICENSE (\"CCPL\" OR \"LICENSE\"). THE WORK IS PROTECTED BY COPYRIGHT AND/OR OTHER APPLICABLE LAW. ANY USE OF THE WORK OTHER THAN AS AUTHORIZED UNDER THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.\n\nBY EXERCISING ANY RIGHTS TO THE WORK PROVIDED HERE, YOU ACCEPT AND AGREE TO BE BOUND BY THE TERMS OF THIS LICENSE. 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Miscellaneous\n\n Each time You Distribute or Publicly Perform the Work or a Collection, the Licensor offers to the recipient a license to the Work on the same terms and conditions as the license granted to You under this License.\n Each time You Distribute or Publicly Perform an Adaptation, Licensor offers to the recipient a license to the original Work on the same terms and conditions as the license granted to You under this License.\n If any provision of this License is invalid or unenforceable under applicable law, it shall not affect the validity or enforceability of the remainder of the terms of this License, and without further action by the parties to this agreement, such provision shall be reformed to the minimum extent necessary to make such provision valid and enforceable.\n No term or provision of this License shall be deemed waived and no breach consented to unless such waiver or consent shall be in writing and signed by the party to be charged with such waiver or consent.\n This License constitutes the entire agreement between the parties with respect to the Work licensed here. There are no understandings, agreements or representations with respect to the Work not specified here. Licensor shall not be bound by any additional provisions that may appear in any communication from You. This License may not be modified without the mutual written agreement of the Licensor and You.\n The rights granted under, and the subject matter referenced, in this License were drafted utilizing the terminology of the Berne Convention for the Protection of Literary and Artistic Works (as amended on September 28, 1979), the Rome Convention of 1961, the WIPO Copyright Treaty of 1996, the WIPO Performances and Phonograms Treaty of 1996 and the Universal Copyright Convention (as revised on July 24, 1971). These rights and subject matter take effect in the relevant jurisdiction in which the License terms are sought to be enforced according to the corresponding provisions of the implementation of those treaty provisions in the applicable national law. If the standard suite of rights granted under applicable copyright law includes additional rights not granted under this License, such additional rights are deemed to be included in the License; this License is not intended to restrict the license of any rights under applicable law.\n" maintainers: - jclaytons name: risc16f84 status: FPGA proven svn-updated: Jun 29, 2014 updated: Jun 29, 2014 wishbone-compliant: 0 - category: Processor created: Jan 17, 2002 description: "===== \n Description =====\n\nA small RISC CPU (written in VHDL) that is compatible with the 12 bit opcode PIC family. Single cycle operation normally, two cycles when the program counter is modified. Clock speeds of over 40Mhz are possible when using the Xilinx Virtex optimizations.\nLicensed under LGPL.\n \n\n\n \n \n \n\n===== \n Legal Stuff =====\n\nThis core is distributed in the hope that it will be useful, but\nWITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n\nYou are responsible for any legal issues arising from the use of this core.\n\nPIC is a trademark of Microchip Technology Inc. \n \n\n\n \n \n \n\n===== \n Features =====\n\nThe core has a single pipeline stage and is run from a single clock, so (ignoring program counter changes) a 40Mhz clock will give 40 MIPS processing speed. Any instruction which modifies the program counter, for example a branch or skip, will result in a pipeline stall and this will only cost one additional clock cycle.\n\nThe CPU architecture chosen is not particularly FPGA friendly, for example multiplexers are generally quite expensive. The maximum combinatorial path delay is also long, so to ease the place and route tool's job the core is written at a low level. It instantiates a number of library macros, for example a 4:1 mux. Two versions of these are given, one is generic VHDL and the second is optimised for Xilinx Virtex series (including Spartan devices). A constraints file locates the datapath macros within the device and ensures an easy fit and high clock speed.\n\n\n\n \n\n\n \n \n \n\n===== \n Performance & Size =====\n\nThe core builds to around 110 Virtex CLBS (depending on synthesis).\n\n>33 Mhz in a Virtex e - 6 \n>40 Mhz in a Virtex e - 8 \n \n\n\n \n \n \n\n===== \n Status =====\n\nComplete.\nTested successfully on hw.\nrel1.1 source zip released. \n \n\n\n \n \n \n\n===== \n Change Log =====\n\n24/02/02\nAdded hex_conv software\n\n12/02/02\nAdded rel1.1 source zip : bug fix\n Used wrong bank select bits in direct addressing \n INDF register returns 0 when indirectly read\n FSR bit 8 always set\n\nAdded rel1.0 source zip : \n Initial release" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mikej name: risc5x status: FPGA proven svn-updated: Mar 10, 2009 updated: Sep 9, 2011 wishbone-compliant: 0 - category: Processor created: Dec 29, 2001 description: "===== \n motivation =====\n\nThis project is my diploma paper i have written to gratuate at the University of Applied Sciences St.Gallen (Switzerland).\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis is a 4 stage 16-Bit RISC processor system on chip designed for a Xilinx Virtex FPGA. RAM and ROM both are blockRAM based. \nAdditionally, it is equiped with a parallel multiplier, a 8-Bit input and a 8-Bit output port. \nThis core wasn't designed for commercial but for educational use. RAM, ROM and the ports are designed with the schematic editor from Xilinx ISE. RAM and ROM are dual ported for an additional access over a pci bridge. The CPU is programmed in VHDL.\n\n \n\n\n \n \n \n\n===== \n Remark =====\n\nThe papers are written in german." language: VHDL license: unknown maintainers: - imme name: risc_core_i status: Planning svn-updated: Mar 10, 2009 updated: Jan 17, 2002 wishbone-compliant: 0 - category: Processor created: Apr 13, 2002 description: "===== \n Description =====\n\n \n\nRISCMCU is based on the features and instruction set of Atmel AVR AT90S1200 RISC Microcontroller.\n\n AT90S1200 vs RISCMCU \n\nSpecification \n\nAT90S1200 \n\nRISCMCU Instructions \n\n89 \n\n92 General P. Registers \n\n32 \n\n16 \n\nProgram ROM \n\n512 words \n\n512 words SRAM \n\nNone \n\n128 bytes Hardware Stack \n\n3 Level Deep \n\n4 Level Deep I/O Ports \n\n2 (15 pins) \n\n3 (24 pins) Addressing Modes 5 7 Speed 4 / 12 MHz 12 MHz 1 8-bit Timer 1 1 External Interrupt 1 1 Implementation CMOS FPGA 2 Others Analog Comparator, Watchdog Reset, EEPROM, Internal Pull-Up Resistor None \n\nNote 1 : Based on the report of Synopsys FPGA Express Note 2 : Altera EPF10K20RC240-4 Device (on Altera UP1 Education Board)\n\n \n\nBlock Diagram \n\n \n\n\n\nDownloads\n\n Description Download Complete VHDL Source Code \n\n RISCMCU_vhdl.tar.gz Documentation - Thesis (PDF, 668KB) \n\n RISCMCU_Thesis.pdf Slides Presentation (PDF, 112KB) \tRISCMCU_Presentation.pdf Simple Calculator ASM File simple_calculator.asm Simple Memory Game ASM File memory_game.asm HEX2MIF C Source Code hex2mif.c \n\n \t\t\t* To download any of the files, please \t\t\tright click on the link and select 'Save Target As'.\n\n \t\t\t\n\nPlease visit CVSWEB - RISCMCU to download more files.\n\n \t Datasheets AVR RISC Microcontroller Instruction Set Atmel AVR AT90S1200 (Complete) Atmel AVR AT90S2313 (Complete) FLEX 10K Embedded Programmable Logic Family University Program Design Laboratory Package \xC2\xA0 Links Atmel AVR RISC Microcontrollers AVR Assembler and AVR Studio Download Page MAX+plus II BASELINE Download Page \n\n Important!!!\n\n\n\n\n\n You will NOT be able to synthesis (compile) the project with MaxPlus II. The project was synthesized with Synopsis FPGA Express 3.4. At that time, Altera was providing free license for it. However, Altera no longer provides free license file. If you are lucky, your university might have purchased it and make it available in the lab. Else, you will need to purchase it yourself.\n\n\n\n\n\n But the good news is, Altera Quartus II is able to synthesis the project and it is FREE! Get it here. You will need to do some minor modifications to modules v_rom and v_ram. Comment out or remove the 'inclock' and 'outclock' lines in port(). Else, Quartus will complaint.\n\n\n\n\n\n Click here to visit the Frequently Ask Questions (FAQ) Section." language: VHDL license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - yapzihe name: riscmcu status: Stable svn-updated: Mar 10, 2009 updated: Sep 17, 2004 wishbone-compliant: 0 - category: Processor created: Aug 1, 2014 description: "===== \n Description =====\n\nThis project is an implementation of a processor compatible with the instruction set of the RISCO architecture.\nA description of the original RISCO ISA is available on http://hdl.handle.net/10183/21530.\nAn assembler and a compiler are available on https://code.google.com/p/risco-llvm/." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - borin name: riscompatible status: Beta svn-updated: Aug 4, 2014 updated: Aug 29, 2014 wishbone-compliant: 0 - category: Processor created: Dec 6, 2006 description: "===== \n Description =====\n\nRISE (Rarest Instruction Set Ever) is a pipelined 16-bit RISC processor with a simple instruction set. One outstanding feature of the instruction set is that all instructions are conditional, i.e. the execution of a instruction may depend on flags in the status register. The processor is equipped with 16 registers: 12 general purpose registers and 4 registers that have are reserved for specific functions (e.g. program counter). The HDL used for this project is VHDL. For further information on the instruction set architecture have a look at this page:\n\nhttp://en.wikiversity.org/wiki/Computer_Architecture_Lab/Winter2006/LechnerWalterStadlerTrinkl/Workplace\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 16-bit RISC CPU\n- 16 registers\n- Leightweight but powerful ISA\n - Conditional instructions\n- Pipelined: 5 stages\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Beginning of development phase" homepage: http://en.wikiversity.org/wiki/Computer_Architecture_Lab/Winter2006/LechnerWalterStadlerTrinkl/Workplace language: VHDL license: unknown maintainers: - jlechner - cwalter - trinklhar - ustadler name: rise status: Beta svn-updated: Feb 9, 2010 updated: Jan 26, 2007 wishbone-compliant: 0 - category: Library created: Sep 2, 2004 description: "===== \n Description =====\n\nThis library has functions for generating good quality random numbers in a VHDL testbench environment. The functions will NOT synthesize.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Based on a combination of 3 Tausworthe generators.\n- Distributions:\n - Uniform (continous)\n - Gaussian (continous)\n - Exponential (continous)\n- For use in test benches\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Version 1.0 released." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - gedra name: rng_lib status: Stable svn-updated: Mar 10, 2009 updated: Oct 14, 2007 wishbone-compliant: 0 - category: Library created: Dec 2, 2005 description: "===== \n General Robot Control library =====\n\nThe aim of this project is to design and implement general control, sensor and actuator ip modules for robot applications. \n The modules will optionally connect to a opb or WishBone bus. Configuration of the individual modules are managed through the bus. A control loop is constructed by connecting the input/output of the individual modules together. This allows for parallel connection of multiple control loops.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- PWM encoder\n - 32 bit OPB interface. Drivers for Microblaze. Supports 2-phase, 1-phase and enable chopping. Programmable frequency and variable PWM width.\n- Quadrature decoder\n - 32 bit OPB interface. Drivers for Microblaze. Outputs position, velocity and accelleration. Velocity and acceleration is output in clocks between each tick. \n- Stepper control \n - 32 bit OPB interface. Drivers for Microblaze. Full-step and Half-step. Programmable step speed.\n- PID\n - 32 OPB interface. Drivers for Microblaze. Up to 32 synchronous/pipelined instances. Sample rate from 0.4Mhz to 15Mhz on Xilinx Spartan3e. Fixed-point artihmetic. \n- PS2 Joypad driver\n - 32 OPB interface. Drivers for Microblaze. Connects to digital and analog Playstation2 compatible Joypads.\n- SPI core\n- None\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Spline module under development.\n- WishBone interface for each module under development.\n- Floating point arithmetic for PID unde development." language: VHDL license: unknown maintainers: - jimali - emjay name: robot_control_library status: Alpha svn-updated: Mar 10, 2009 updated: Feb 14, 2007 wishbone-compliant: 0 - category: System on Chip created: Apr 13, 2011 description: "===== \n Description =====\n\nGeneric AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according to input parameters: master number, slave number, data bits, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools\n \n\n\n \n \n \n\n===== \n Related projects =====\n\nGeneric AHB master stub\nhttp://opencores.org/project,ahb_master\n\nGeneric AHB slave stub\nhttp://opencores.org/project,ahb_slave" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: robust_ahb_matrix status: Alpha svn-updated: Jul 3, 2011 updated: Sep 21, 2013 wishbone-compliant: 0 - category: System on Chip created: Apr 13, 2011 description: "===== \n Description =====\n\nGeneric AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB slave error. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: robust_axi2ahb status: Alpha svn-updated: Jul 3, 2011 updated: Jun 2, 2012 wishbone-compliant: 0 - category: System on Chip created: Mar 28, 2011 description: "===== \n Description =====\n\nGeneric AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error, APB response delay and slave error. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: robust_axi2apb status: Alpha svn-updated: Jul 3, 2011 updated: Apr 19, 2011 wishbone-compliant: 0 - category: System on Chip created: Mar 23, 2011 description: "===== \n Description =====\n\nGeneric AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI interconnects according to input parameters: master number, slave number, AXI IDs, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools\n \n\n\n \n \n \n\n===== \n Related projects =====\n\nGeneric AXI master stub \nhttp://opencores.org/project,axi_master \n\nGeneric AXI slave stub \nhttp://opencores.org/project,axi_slave" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: robust_axi_fabric status: Stable svn-updated: Jul 3, 2011 updated: Oct 16, 2014 wishbone-compliant: 0 - category: DSP core created: Mar 23, 2011 description: "===== \n Description =====\n\nGeneric FIR filter. Builds optimized filter according to number of multipliers, supports serial or parallel architecture. Supports delays in input. Builds Verilog FIR filter according to input parameters: multiplier number, filter order, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: robust_fir status: Stable svn-updated: Jul 3, 2011 updated: Jun 18, 2012 wishbone-compliant: 0 - category: System on Chip created: Mar 29, 2011 description: "===== \n Description =====\n\nGeneric APB register file generator. Creates Verilog source, C header file and HTML documentation, from an Excel worksheet. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools\n \n\n\n \n \n \n\n===== \n Related projects =====\n\nGeneric APB master stub\nhttp://opencores.org/project,apb_mstr\n\nGeneric AXI2APB bridge \nhttp://opencores.org/project,robust_axi2apb" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eyalhoc name: robust_reg status: Mature svn-updated: Jul 3, 2011 updated: Mar 16, 2015 wishbone-compliant: 0 - category: Video controller created: Jun 8, 2006 description: "===== \n Description =====\n\nThe ROSETTA Configurable Dot Matrix Display Controller core provides a modular expandable interface for any dimension displays build from LEDs dot matrix structures. This core can be configured for synthesis and P&R with any number of DM LEDs slices. These slices can be arranged in any number to form linear or plane screens. \n In designs with a big number of slices, the number of pins required for the implementation device selected could collapse. In order to overcome this inconvenience, the output bus has a multiplexed structure, and the size of the display can be expanded using external buffer devices. \n\n In limited size implementations, the display columns could optionally be serviced using the controller chip drivers, if a device with enough driving capability is used. On the other hand, the row lines will always need some external buffering. \n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nFeatures \n- WISHBONE interface in 8,16, 32 or 64-bit data bus modes \n- SystemC, Verilog and VHDL languages \n- Use of Dot Matrix LEDs Display structures. \n- Configurable for single color, RG or RGB LEDs use \n- Operation Modes: Test, Full Text, Full Graphics, Mixed Text & Graphics, Animation \n- Scroll: Horizontal, Vertical and Combined \n- Colors: configurable from monochromatic to any number of colors \n- Variable Buffer size \n- Modular expansion \n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Development of SystemC specification and system level model" language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - rrorroensydney name: rosetta status: Specification done svn-updated: Mar 10, 2009 updated: Jun 12, 2006 wishbone-compliant: 1 - category: Arithmetic core created: Jan 8, 2015 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - chickenjohn name: rotating_led_display status: Empty updated: Jan 8, 2015 wishbone-compliant: 0 - category: Other created: Mar 25, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - rainrhythm name: round_robin_arbiter status: Stable svn-updated: Mar 26, 2010 updated: Mar 26, 2010 wishbone-compliant: 0 - category: Communication controller created: Aug 29, 2010 description: "===== \n Description =====\n\nThis is a small UART to byte uPC interface (compliant with RS232 and RS3232 CI's).\nIdeal to use with soft/hard processors in a FPGA project.\n\nDesigned to sync internal clock of RX path. Independent clock sources (TX/RX).\n \n\n\n \n \n \n\n===== \n uPC Interface =====\n\nTX:\n- TX data;\n- TX request;\n- TX end of send;\n\nRX:\n- RX data;\n- RX data ready (data valid);" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: rs232_interface status: FPGA proven svn-updated: Jul 3, 2012 updated: Apr 29, 2015 wishbone-compliant: 0 - category: System controller created: Sep 25, 2001 description: "===== \n Description =====\n\nrs232_syscon is a synthesizeable soft core that allows debugging of peripherals connected to a Wishbone type of bus. Specifically, it lets the user write and read registers, and send out reset pulses, via an rs232 serial connection to a \"dumb terminal.\" (Such as windows \"hyperterm\"!) It is completely scalable through parameter settings, to accomodate address and data buses of any arbitrary size. Furthermore, the rs232_syscon module can share the Wishbone bus with the master (presumably a processor of some kind). It implements a handshaking protocol with the master to \"request\" the bus. When the master grants access, the rs232_syscon runs bus cycles on its own, to report contents of registers and memory back to the user, in an easy-to-read hexadecimal format. This is very useful when debugging peripherals -- you can set the contents of memory, set up registers, and even use registers to control \"single stepping\" of your target processor. If desired, the rs232_syscon can be the sole master of the Wishbone bus, to perform \"human-speed\" tests on peripherals (set a value, check a result) without having to connect the peripheral to a processor.\n\nThe \"ack_i\" and \"err_i\" signals of the Wishbone bus are used to determine if the bus cycles are correctly executed. The rs232_syscon module uses a \"watchdog\" timer to determine if \"ack_i\" has arrived too late, and if so, it sends an error indicator back to the host terminal. If \"err_i\" occurs, it also sends back a bus error indicator. The timeout value of the watchdog timer is configurable by parameters to whatever length is needed, and the bus cycles are automatically extended for as many clocks as needed until the \"ack_i\" signal is received. If \"ack_i\" is not used, simply tie it high.\n\nThe design team of rs232_syscon welcomes any kind of help and feedback on this core. If you are interested in further development of this project, please contact us.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- This core now supports four basic commands: 'r' (read), 'w' (write), 'f' (fill) and 'i' (initialize = reset).\n- The read/write/fill commands allow a quantity field, to specify multiple writes or reads (using consecutive addresses).\n- There are no technology-dependent elements used in this core.\n- The data bus consists of separate dat_i/dat_o buses.\n- The core runs at clock speeds above 50MHz on a Lattice LFXP2-5E.\n- The interface is currently implemented as a large state-machine (no processor is involved.)\n- The command structure is very simple and \"sparse.\"\n\nIn the future, a version could be implemented using a small microcontroller core with some integrated software, which would probably be more compact and flexible, with a richer command set. But, since we wanted to use this core to _develop_ microcontroller cores -- well, it was a case of \"which came first, the chicken or the egg?\" We had to start somewhere!\n\n \n\n\n \n \n \n\n===== \n Project News =====\n\n- There is a new version of this module which incorporates \"auto_baud_with_tracking\". It is a feature that allows for any FPGA board clock frequency from 1-100 MHz to be used for different BAUD rates. There is no calculation needed, it adjusts automatically!\n- The rs232_syscon module has been used to build and debug a small microcontroller, the \"risc16f84\" project." language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jclaytons name: rs232_syscon status: FPGA proven svn-updated: Jul 14, 2013 updated: Jan 23, 2015 wishbone-compliant: 1 - category: Communication controller created: Jan 13, 2013 description: "===== \n Description =====\n\nTwo wire RS232 communication module capable of 5, 6, 7, 8 bit word communication, Parity bit, Parity bit Polarity, 1 and 2 stop bits. Integrated with transmit and receive buffer controlled through a WishBone interface. Besides the WishBone interface auxiliary signals are provided for Buffer status and can be used for interrupt driven routines." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - TobiasJ name: rs232_with_buffer_and_wb status: Alpha svn-updated: Jan 30, 2013 updated: Sep 11, 2013 wishbone-compliant: 1 - category: ECC core created: Oct 19, 2004 description: "===== \n Reed Solomon (5, 3) Encoder-Decoder in GF(256) =====\n\n- Symbol width : 8-bits.\n- Encodes every 3-byte message into 5-byte codewords.\n- Capable of correcting any single symbol error (even if all the 8-bits are erronous) in a codeword.\n- This core has two operation modes: Encoding and Decoding.\n- In both operation modes, the inputs are taken in byte-by-byte at each clock cyle.\n- While encoding, message is input at three clock cycles and the next two clock cyles are reserved for the two parity symbols of the codeword.\n- While decoding, received vector is taken in at five clock cycles. But the output is first seen at the sixth clock cyle. However, at the sixth clock cycle another received vector can be fed to the decoder. \n \n \n\n\n \n \n \n\n===== \n Features =====\n\n- 24 bits of information is encoded at every 5 clocks:\n - example: Clock Frequency : 50 MHz --> Baud: 240Mbps\n- 32 bits of received vector is decoded every 5 clocks:\n - example: Clock Frequency : 50 MHz --> Baud: 320Mbps\n- Please go to the \"downloads\" link and have look at the ppt file.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- status1\n- status2" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - soneryesil name: rs_5_3_gf256 status: Design done svn-updated: Mar 10, 2009 updated: Jun 20, 2005 wishbone-compliant: 0 - category: ECC core created: Feb 1, 2010 description: "===== \n Description =====\n\nThis core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and parametrizable.\n\n\nMain Features:\n\n\n8-bit input and output data busses\nFully synchronous and pipelined design using a single clock. \nSymbol width of 8 bits\nCorrected byte number signaling\nDetects condition when the number of errors is too high to be corrected\nCan correct 2 symbols.\n\n\nPlease, contact us if you wish to have this IP core modified or adjusted to meet your requirements.\n\n\nThis core is provided by Unicore Systems http://unicore.co.ua. To view our product list of commercial IP cores, please, follow this link" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unicore - aser name: rs_dec_enc status: Stable svn-updated: Feb 2, 2010 updated: Feb 2, 2010 wishbone-compliant: 0 - category: ECC core created: Feb 7, 2006 description: "===== \n Specifications =====\n\n- Hard-decision decoding scheme\n- Codeword length (n) : 31 symbols\n- Message length (k) : 19 symbols\n- Error correction capability (t) : 6 symbols\n- One symbol represents 5 bit\n- Uses GF(2^5) with primitive polynomial p(x) = X^5 + X^2 + 1\n- Generator polynomial, g(x) = a^15 + a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30\n- Uses Verilog description with synthesizable RTL modelling\n- Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- High speed decoding algorithm.\n- Can output corrected received word while input new received word.\n- Synchronous timing.\n- dataoutstart (start of output data block) and dataoutend (end of output data block) signal to synchronize to other core outside the decoder.\n- Have decoding failure flag if error is uncorrectable.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- design has been simulated successfully\n- uploaded v1.0\n- Please do not send me email asking about all aspects of Reed-Solomon encoder-decoder (algorithms, architectures, implementation, simulation problems, etc.), since I do not provide any kind of technical supports. You can still freely download the source code though." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rud_dp name: rs_decoder_31_19_6 status: Stable svn-updated: Mar 10, 2009 updated: Dec 1, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Nov 27, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - xuehualee name: rs_decoding status: Empty updated: Nov 27, 2011 wishbone-compliant: 0 - category: ECC core created: Dec 14, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - farooq21 name: rs_encoder_decoder status: Beta svn-updated: Dec 19, 2010 updated: Dec 14, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Nov 27, 2012 description: "===== \n Description =====\n\nThis code implements a Reed Solomon encoder/decoder for both the parity size of 8 and the 16.\nThe Reed Solomon encoder structure implemented here is the one used in ADSL G.9956 but it is\nalso used in lot of the other emerging communication systems such as wireless 3rd generation \n3GPP standard (Wideband CDMA) and powerline communication standards like Homeplug.\n\nThe code is not documented very well. I found it on the internet and tested it and\nfind that it works very very good. Use and enjoy by saving lot of time implementing this big block.\nThis code can also be used for verilog coding since is written is such as way to be easy\nto port it to the behavioral verilog from the C language.\n\nWARNING: SINCE I DON'T HAVE TIME TO LEARN SVN I AM UPLOADING THE CODE AS A SINGLE ZIP FILE THAT CAN \nBE OPENED WITH winzip OR 7zip. BUT FOR THIS WEBSITE TO LET ME UPLOAD MY CODE WITHOUT SVN \nI HAD TO CHANGE ITS EXTENSION FROM .zip TO .pdf. SO PROCEDURE IS AS FOLLOWS:\n\n1) download file RS_Encoder_Decoder.pdf\n\n2) rename it to RS_Encoder_Decoder.zip.\n\n3) unzip it using winzip or 7zip or winRAR. You will get five .c source files and 5 .h header \nfiles and some data files and a readme.txt with insturctions on how to run the code.\n\n4) Enjoy. \n\nkey words: Reed-Solomon encoder, RS encoder," language: C/C++ license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - programmer2013 name: rs_encoder_decoder_project status: Empty updated: Nov 29, 2012 wishbone-compliant: 0 - category: Crypto core created: Sep 25, 2001 description: "===== \n Description =====\n\nRSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key.\n\nRSA was created by Rivest, Shamir, and Adleman in 1977. \n\nEvery user have a pair of key, public key and private key.\n\nPublic key (e) . You may choose any number for e with these requirements, 1, where \xC3\x86(n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,\xC3\x86(n))=1 (gcd= greatest common divisor).\n\nPrivate key (d). d=(1/e) mod(\xC3\x86(n))\n\nEncyption (C) . C=M\xC2\xAA mod(n), a = e (public key), n=pq\n\nDescryption (D) . D=C\xC2\xB0 mod(n), o = d (private key) \n \n\n\n \n \n \n\n===== \n Specifications =====\n\n- Every user have a pair of key, public key and private key. \n- Modulus n-public is integer positif k-bit which has wide from 512 until 2048 bit. \n- Prime secret numbers p and q are about k/2 bit, p and q are formed use its Program Random Generate. \n- Public key (e) is positif integer h-bit. Usually it\xE2\x80\x99s not more than 32 bits, the possible smallest number is 3. \n- Private key (d) is big number. It\xE2\x80\x99s about \xC3\x86(n)-1. \n \n\n\n \n \n \n\n===== \n Design stages =====\n\n- Make core specifications \n- Design behavioral and structural using Alliance tools \n- Converting to symbolic layout \n- Full verifications \n- Converting to real layout" language: VHDL license: unknown maintainers: - wishnu name: rsa status: Planning svn-updated: Mar 10, 2009 updated: Jun 28, 2012 wishbone-compliant: 0 - category: Crypto core created: Mar 7, 2010 description: "===== \n Description =====\n\nThe project presents an open-source implementaion of the 512 bit RSA algorithm. This is a reduced version of a full FIPS Certified capable RSA Crypto-core.\n\n The full version supports all key sizes (512, 1024, 2048, 4096) and includes a complete testbench. It can reach more than 150 operations per second with a 1024 key size in a Spartan 6 FPGA and more than 200 in a Virtex 6.\n \n The core fits in a XC6SLX25T, which makes it a nice solution for mobile devices needing RSA acceleration.\n \n For more information contact jcastillo@opencores.org\n\nPlease read carefully the documentation. Some cores should be generated calculated prior to use.\n\nThanks to Oleg Rasulov for their contributions." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jcastillo name: rsa_512 status: Stable svn-updated: Jan 12, 2011 updated: Oct 24, 2012 wishbone-compliant: 0 - category: ECC core created: Jun 26, 2004 description: "===== \n Status =====\n\n- RTL done and design verified using testbench.\n- Will upload soon.\n- June 27th 2004, updated. Please click on 'Downloads' (top right on this page).\n - June 29 2004, There was a typo in reed_solomon.v file. The output ports d0, d1, d2, d3 actually refer to q0, q1, q2, q3 (see readme.txt file). Sorry for the confusion. Corrected now. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- User defined generator polynomial. \n - Allows experimentation with diferent generator polynomials for best implementation.\n - Replacable Galois field multiplier submodule for a different primitive polynomial.\n - Can be used for shortened codes.\n - Achieved > 200MHZ ( = 1.6 Gbps) on Altera's Stratix FPGA. \n \n \n \n\n\n \n \n \n\n===== \n Reed Solomon Encoder =====\n\nReed Solomon Encoder synthesizable IP core compatible with G709, DVB1, DVB2 standards. Implements (n, k) code where n-k = 16 ( 8 byte error correction capable code). The verilog is written in such a way as to be easily parameterized for different values of n and k. If there is any interest for parameterization, let me know and I will create a version 2 core. Otherwise the core \"as is\" can be used to implement for example, a (255, 239) or (204, 188) codes. The underlying galois field is GF(2^8) with primitive polynomial, x^8+x^4+x^3+x^2+1." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rajesh_99 name: rsencoder status: Stable svn-updated: Mar 10, 2009 updated: Jul 3, 2012 wishbone-compliant: 0 - category: System controller created: Oct 24, 2013 description: "===== \n Description =====\n\nReal Time Clock with wishbone bus complaint. The RTC can transmit data to CPU as Binary Coded Decimal (BCD) values through wishbone bus. The data include the time by second, minute, hour, date, day, month, and year. It is 24-hour format. The RTC module can work with an external crystal that the frequency is not very fixed, such as 32.768kHz and so on. It also can generate two flexible interrupt requests: alarm and repetitive mode.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- BCD number: second, minute, hour, date, day, month, and year;\n- Determine whether the year is leap year;\n- Year 2000 problem is removed;\n- Either analog crystal oscillator input or digital clock input, and clock input is not fixed;\n- Repetitive interrupt mode, Programmed to provide 6 different interval interrupt requests: once per second, once per minute, once per hour, once a day, once a week, once a month;\n- Alarm interrupt mode, Programmed to generate interrupt request signal when real time clock equals to the time stored beforehand in the register;\n- Written in SystemVerilog, and fully synthesisable." language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - kailassenan - jathinpv name: rtc_systemverilog status: Empty updated: Apr 15, 2015 wishbone-compliant: 1 - category: Crypto core created: Oct 5, 2009 description: "===== \n Description =====\n\nRTEA (from Ruptor's TEA or Repaired TEA) - a symmetric block encryption algorithm used type \"Feistel cipher\", designed by Marcos el Ruptor, expansion TEA. Fixed some vulnerability in the algorithm. Like other variants of the algorithm TEA, the operation based on work with 32-bit numbers. The algorithm is much simpler and more productive XTEA, while, according to the authors and conducted by the developers according to statistical tests, is more resistant to cryptanalysis http://defectoscopy.com/results.html\n\nKey size 128/256 bits\nBlock size 64 bit" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - strijar name: rtea status: Stable svn-updated: Oct 5, 2009 updated: Oct 5, 2009 wishbone-compliant: 0 - category: Processor created: Sep 5, 2013 description: "===== \n Description =====\n\nThe RTF65002 is a 32 bit processor with an instruction set influenced by the 6502 instruction set. It is a 16 register 32 bit word oriented design. The RTF65002 includes 65C816/65C02 emulation modes allowing it to run existing code. In native 32 bit mode the opcodes are redefined in a fashion suitable for 32 bit mode. An attempt has been made to follow the same pattern as the 6502 for opcodes. For instance opcode 69h is an add instruction on the 6502; it's an add instruction on the RTF65002 as well.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 32 bit WISHBONE burst mode compatible bus interface\n- independant instruction and data caches\n- variable length instructions; from one to seven bytes\n- 16 entry 32 bit general purpose register file, plus independant stack pointer\n- 65C02 and 65C816 emulation modes\n- non-overlapped pipeline; minimum CPI is 2" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: rtf65002 status: FPGA proven svn-updated: May 4, 2014 updated: May 4, 2014 wishbone-compliant: 1 - category: System on Chip created: Sep 25, 2011 description: "===== \n Description =====\n\nThis is a complete system-on-a-chip.\n\nDeveloped on a Diligent Spartan3e board, the SOC includes CPU (TG68), bitmap and text displays, PSG, keyboard and more.\n \n\n\n \n \n \n\n===== \n Features =====\n\n52x31 text display\n416 x 262 bitmapped graphics display\nline draw accelerator\n8 sprites\n4 channel ADSR PSG (not working at the moment)\nrandom number generator\nPS2 compatible keyboard interface\nTG68 cpu\nRS232 interface UART\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Overview =====\n\nThe SOC make use of the TG68 cpu core available at OpenCores.org. This fine core implements the MC68000 instruction set.\n\nThe Nexys Epp memory controller available on the Diligent site is used for external communications to the PSRAM and Flash ROM.\n\nAlso used are the rtfTextController and rtfBitmap Controller cores found elsewhere on OpenCores.org.\n\nThe chip a Spartan 3eS1200e is full!\n\nWISHBONE bus is used for core interconnects.\n\n\nMemory:\n\nThere are about a half dozen devices that can act as bus masters for the onboard PSRAM. These are all connected through a memory controller. Devices have a fixed priority arrangement for access to the RAM with burst bitmap video having the highest priority. During developement a 2k RAM and BIOS rom were connected on a private cpu bus to make it easier to get the cpu going.\n\nI/O:\nA PS2 compatible keyboard interface recieves scan codes from the keyboard which is then converted to ascii using a scan-code lookup table in hardware. Ctrl-Alt-Del is wired to the processor's NMI signal to allow the system to be reset.\nA WXGA video sync generator supplies timing to several video cores. The video cores are connected together to form a video pipeline. The switches on the FPGA board may be used to switch on and off several video devices.\n\n\nSoftware:\n\nA modified version Gordo's Tiny Basic 1.2 is used and occupies the last part of the BIOS ROM. The Poke and peek commands can be used to control the devices in the system. Currently added to the tiny basic are a couple of graphics commands: LINE x0,y0,x1,y1. POINT x,y. AND PENCOLOR c. There is also a small ROM monitor. The ROM monitor allows dumping memory, and jumping to code." language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: rtf68ksys status: Alpha svn-updated: Sep 30, 2011 updated: Sep 25, 2011 wishbone-compliant: 1 - category: Processor created: Dec 29, 2012 description: "===== \n Description =====\n\nrtf8088 is a core capable of executing the 8088 instruction set. The core uses a hard-wired state machine approach." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: rtf8088 status: Planning svn-updated: Dec 1, 2013 updated: Dec 30, 2012 wishbone-compliant: 0 - category: Video controller created: Feb 2, 2013 description: "===== \n Description =====\n\nThis core provide hardware cursor / sprite capabilities. It supports alpha blending in the 32k color mode. The cursor characteristics are completely programmable.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- parameterized number of sprites/cursors 1,2,4,6,8 or 14\n- 2kB sprite image cache buffers\n\t- each image cache is capable of holding multiple sprite images\n\t- cache may be accessed like a memory by the processor\n\t- an embedded DMA controller may also be used for sprite reload\n- programmable image offset within cache\n- programmable sprite width,height, and pixel size\n\t- sprite width and height may vary from 1 to 64 as long\n\t as the product doesn't exceed 1024.\n - pixels may be programmed to be 1,2,3 or 4 video clocks\n both height and width are programmable\n- programmable sprite position\n- 8 or 16 bits for color\n\teg 32k color + 1 bit alpha blending indicator (1,5,5,5)\n- fixed display and DMA priority sprite 0 highest, sprite 13 lowest\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe core is currently being tested on an Atlys board and appears to be working." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: rtf_sprite_controller status: Alpha svn-updated: Feb 4, 2013 updated: Feb 4, 2013 wishbone-compliant: 0 - category: Video controller created: Sep 19, 2011 description: "===== \n Description =====\n\nThis core is a low to medium resolution bitmap display controller. It was engineered for use on the\nNexsys2 board, a Spartan3e FPGA board, but is readily adaptable to other environments. The core has\nbeen upgraded for use on the Atlys FPGA board. The latest incarnation of the core is being developed on a Nexys4 board.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- small size\n- supports high, mid and low resolution bitmap display\n- programmable display format (divide by 1,2, or 4).\n- programmable color depth (8,16, or 32 bpp).\n- 32 byte burst fetching\n- memory bandwidth consideration\n- video fifo\n- independent video and bus clocks\n\n- controller2\n--- supports the concept of color planes and can indicate if colors should appear as backdrop or frontdrop\n--- uses non-burst, 128 bit wide memory access\n\n- controller3\n--- supports more color depths: (6,8,9,12,15,16,24, and 32 bpp)\n--- offers more display dividers (1 to 7 times)\n--- uses non-burst, 128 bit wide memory access\n\nWhile small, this controller core has a number of interesting features. It features low resolution\n(low resolution these days) bitmap display. The video clock and scanline may be divided by up to 4 to provide lower resolution displays. For instance a 340 x 192 x 8bpp display can be created using a 1366x768 display mode. Memory usage is then\nabout 64Kb. The design of the controller takes into consideration the amount of memory bandwidth available to\nthe system, using 32 byte burst fetches to fill a fifo. \n\n\n\n \n\n\n \n \n \n\n===== \n Operation =====\n\nThe controller fetches data in 32 byte bursts as the video fifo become empty. The 32 byte\nburst fetches are geared towards allowing other devices in the system to access the same memory. So\nthat the peformance of the entire system isn't adverse. The controller relies on the memory system\nto support burst mode fetchs.\n\nThe controller uses three independent clocks, one each for bus timing and video timing." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: rtfbitmapcontroller status: FPGA proven svn-updated: May 3, 2015 updated: May 3, 2015 wishbone-compliant: 1 - category: Communication controller created: Sep 12, 2011 description: "===== \n Description =====\n\nThis is a simple uart core which includes a baud generator. The core uses a fixed format: 1 start,8 data, 1 stop bit.\n+ baudX8/X16 mode selects in runtime" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - robfinch - AlexRayne name: rtfsimpleuart status: FPGA proven svn-updated: Nov 16, 2013 updated: Nov 16, 2013 wishbone-compliant: 1 - category: Video controller created: Sep 6, 2011 description: "===== \n Description =====\n\nThe latest incarnation of the text controller has a default resolution of 56x31 expecting a 1366x768 screen resolution. The size and number of characters displayed is easily programmable. The controller now uses externally supplied horizontal and vertical sync signals for a reference point. The controller detects the positive edge of the signals. The display memory is 32 bits wide of which 9 bits are used for each of foreground, background colors, and the character code. Character codes and attributes are stored together in the same memory word. The register set for the controller remains the same. There is no longer a separate attribute memory at $FFD1xxxx. Also supported is a transparent color which allows text to be placed ontop of another externally supplied image.\n\nThis is a text mode video controller that supports color. The default resolution is 52x31 expecting a 1680x1050 graphics mode for display. The controller uses an external sync generator which must supply end-of-scanline and end-of-frame signals. Display memory is sixteen bits wide of which nine bits are implemented allowing 512 different characters to be displayed simultaneously.\nCharacter bitmaps are stored in block RAM allowing them to be reprogrammed at run time, these can be pre-initialized in a constraints file.\n\nThe display controller fits into a memory map at addresses $FFD0xxxx, $FFD1xxxx, and $FFD2xxxx, for the text memory, attribute memory, and character bitmaps respectively.\nNote that there are multiple images of the memories within the address range.\nThe display controller register set is at $FFDA00xx." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robfinch name: rtftextcontroller status: FPGA proven svn-updated: Jun 25, 2014 updated: Jun 27, 2014 wishbone-compliant: 1 - category: Other created: Jan 20, 2015 description: "===== \n Description =====\n\nHere i am trying to demonstrate my idea, that Russell's paradox of set theory can be solved by computer simulation in discrete time. It leads to oscillating sets, meaning theese sets automatically become existent and then disappear over time by their definition. Furthermore i try to describe it in such an event driven way, where theoretically the time between the events can be infinitely short..." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - feketebv name: russels_paradox status: Planning svn-updated: Jan 21, 2015 updated: Jan 21, 2015 wishbone-compliant: 0 - category: Communication controller created: Mar 31, 2009 description: "===== \n Overview =====\n\nRXAUI interface uses two 6.25Gbps SERDES lanes to carry 10GE, instead of using four 3.125Gbps SERDES lanes.\nThis enables a high port count lower power multi 10GE SOCs. \n\nThis projects provides the specifications of RXAUI interface and the verilog code for an adapter from \na XAUI to RXAUI interface" language: Verilog license: proprietary maintainers: - tsahidaniel name: rxaui_interface_and_xaui_to_rxaui_interface_adapter status: ASIC and FPGA proven svn-updated: Apr 2, 2009 updated: Oct 22, 2009 wishbone-compliant: 0 - category: Processor created: Jan 3, 2007 description: "===== \n S1 Core briefly... =====\n\nThe S1 Core is a reduced version of the OpenSPARC T1 released by Sun Microsystems. While the T1 is a complete microprocessor with 8 cores (capable of running up to 32 concurrent threads) and includes a crossbar switch, L2 Caches and several other interfaces, the S1 takes only one 64-bit SPARC v9 core (capable of running from 1 up to 4 concurrent threads) and includes a Wishbone Master Interface to connect to the cores available on OpenCores.\n\n\n\n\nFor more details please refer to the Simply RISC website, or to the new OpenSPARC SoC project that contains several updates and bug-fixes." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - fafa1971 - dmitryr name: s1_core status: Stable svn-updated: Oct 2, 2012 updated: Oct 1, 2012 wishbone-compliant: 1 - category: Crypto core created: Jul 19, 2012 description: "===== \n Description =====\n\nSalsa20 stream cipher is built on a pseudorandom function based on 32-bit addition, bitwise addition (XOR) and rotation operations, which maps a 256-bit key, a 64-bit nonce (number used once), and a 64-bit stream position to a 512-bit output. It has advantage that the user can efficiently seek to any position in the output stream.\n \n\n\n \n \n \n\n===== \n Implementation =====\n\nThe target device for implementation was Cyclone 3 from Altera (EP3C120). The motivation for these was to have nonce-based PRSequence generator - proof of concept. It was intended to be used with 120MHz clock. It finally can run up to more than 150MHz, according to TimeQuest reports. It has not been tested in FPGA. Our application did not require performance, so it is not optimized for this purpose. It will give you estimately a bit more than 5 bits of PRS per cycle, in chunks of 512 bits every 86 cycles. It uses about 3% of logic elements and nothing more." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: salsa20 status: Mature svn-updated: Aug 1, 2012 updated: Nov 13, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Apr 10, 2012 description: "===== \n Description =====\n\nThis is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture. This architecture called SAP for Simple-As-Possible computer. It very useful design which introduces most of the basic and fundamental ideas behind computer operation.\n\nThis design could be used for instruction classes for undergraduate classes or specific VHDL classes. This processor is based on the 8080 architecture, therefore, it could be upgraded step by step to integrate further facilities. It is very exciting challenge for the students to do so. Further, they could think about building complete system, i.e. integrating and I/O peripherals to the processor.\n\nThe design is proven for ASIC and FPGA. It was implemented using Xilinx FPGA Spartan-3E starter kit. A full documentation for the code and the used resources are attached within the project.\n\nI hope that you will enjoy it.\n\nPersonally, I recommend you to start building your own design then you can compare to this one as a reference design. We learn from our mistakes.\nI will be glad to receive your feedback and comments, acknowledgments would be great as well." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: sap status: ASIC and FPGA proven svn-updated: Apr 11, 2012 updated: Apr 11, 2012 wishbone-compliant: 0 - category: System on Chip created: Jan 21, 2006 description: "===== \n Embedded MIPS R2000 =====\n\nIt's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting is optional, and pipeline depth is configurable.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n - feature1.1\n -feature1.2\n-feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\nSome bugs was fix.\n\n -> correct bug when intterupt occur during MFLO and MFHI instruction.\n\nNow I'm working on the CP0\n\nstatus 2" language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - igorloi name: sardmips status: Alpha svn-updated: Mar 10, 2009 updated: Feb 9, 2006 wishbone-compliant: 0 - category: Communication controller created: Sep 17, 2002 description: "===== \n Description =====\n\nSimple asynchronous serial controller (aka UART). Includes 4\nbyte receive and a 4 byte transmit FIFO (FIFO size can be easily\nadjusted). External baud rate generator (included). Very small.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Implemented in Verilog\n- Flow Control (CTS/RTS)\n- 1 start bit, 1 stop bit, NO parity\n- 4 byte receive FIFO\n- 4 byte transmit FIFO\n- Fully Synthesisable\n- 102 LUTs in a Spartan II\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis core is fully functional and completed.\nIt was verified in hardware in an XESS XVC800 FPGA prototype\nboard with a Maxim RS232 line driver.\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: sasc status: FPGA proven svn-updated: Mar 10, 2009 updated: Mar 30, 2006 wishbone-compliant: 0 - category: Communication controller created: Nov 26, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - cuifan829 name: sata status: Empty updated: Nov 26, 2011 wishbone-compliant: 0 - category: Communication controller created: Mar 6, 2012 description: "===== \n Description =====\n\nThe SATA core implements the Command, Transport and Link Layers of \nthe SATA protocol and provides a Physical Layer Wrapper for the GTX \ntransceivers. The Physical Layer Wrapper also includes an Out of Band\nSignaling (OOB) controller state machine which deals with initialization\nand synchronization of the SATA link. It can interface with SATA 2\nWinchester style Hard Disks as well as Flash-based Solid State Drives\n\nThe core provides a simple interface to issue READ/WRITE sector commands.\nThe DATA interface is 32-bit FIFO like.\nA 150 MHz input reference clock is needed for the GTX transceivers.\nThe output data is delivered 4 bytes @ 75 MHz (user output clock).\n \nA Xilinx base system with the SATA Core, a DDR interface and a Microblaze\nC test application is also provided under \"trunk/sata2_bus_v1_00_a\"" language: Verilog & VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - rsass - ashwin_mendon - bhuang2 name: sata_controller_core status: FPGA proven svn-updated: May 7, 2013 updated: Nov 12, 2014 wishbone-compliant: 0 - category: Communication controller created: Jul 12, 2012 description: "===== \n Description =====\n\nSATA PHY layer which can be implemented as either a host or device for Xilinx 6 series devices. \n\nA host controller core with AXI interface is available, contact me for more information." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - beandigital name: sata_phy status: Stable svn-updated: Jul 12, 2012 updated: Mar 10, 2014 wishbone-compliant: 0 - category: Processor created: May 30, 2008 description: "===== \n Description =====\n\nThe SAYEH processor (Simple Architecture,Yet Enough Hardware) has been designed for educational and benchmarking purpose. Relying on the material of the computer architecture course provide the necessary background for understanding details of the hardware of SAYEH, so it could be useful IP core for graduate or last year undergraduate students to implement computer architecture materials in a real processor design.\nOriginally SAYEH has been developed in ECE at university of Tehran, IRAN.\n \n\n\n \n \n \n\n===== \n Features =====\n\nSAYEH has a register file that is used for data processing instructions, also has a 16-bit data bus, 16-bit address bus and 16-bit instruction set architecture with simple arithmetic ,logic and communicative instructions.\nhttp://haghdoost.persiangig.com/sayeh/architecture.gif (SAYEH Architecture)\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Latest version of Verilog description files uploaded. \n- necessary information and documentation gathered from computer students in University of Tehran." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - haghdoost - saboteur name: sayeh_processor status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 17, 2008 wishbone-compliant: 0 - category: Other created: Oct 8, 2004 description: "===== \n Features =====\n\n- Full source code\n- PDF documentation\n- Written using lex and yacc tools\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe sc2v translator is a software tool that translates a SystemC RT description into a Verilog equivalent one.\nThe sc2v translator is based on lex and yacc tools. \nYou need lex and yacc installed in order to compile sc2v.\n\n\nThis work is given by Universidad Rey Juan Carlos (Spain)\nwww.gdhwsw.urjc.es\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Version 0.5\n- TODO: See README File\n\n- LOOKING FOR CONTRIBUTORS" language: Verilog license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - jcastillo - phuerta name: sc2v status: Stable svn-updated: Mar 10, 2009 updated: Apr 9, 2010 wishbone-compliant: 0 - category: Other created: Aug 5, 2008 description: "===== \n Description =====\n\nA scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speeds with up to hundreds of request lines, and it grants in just a few clock cycles. The arbiter's interface has individual request and grant lines for each requesting device, as well as a binary encoded grant that can be used to control a bus multiplexer.\n\nThe basic structure is a tree of small arbiters connected to form a larger arbiter. The tree structure yields linear size scaling and logarithmic delay scaling with respect to the number of request lines. Most of the implementation is in instantiating and interconnecting the arbiter tree. The actual logic boils down to a simple two-input arbiter.\n\nI started this project because I could not find a general purpose arbiter implementation with a configurable number of inputs that scales well. There is not much code for the arbiter implementation. Test benches and a demo instantiation are included. There are also some extras that are not particularly related to the arbiter. I just figured that they would be better off here than anywhere else. It might be better to combine this project with a larger, library type of project, but I did not see such a project in Verilog on OpenCores.\n\nThe code is provided under the ISC license, which is a BSD-style license. Everyone is welcome to use and contribute." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - kendallc name: scalable_arbiter status: FPGA proven svn-updated: Nov 16, 2009 updated: Jan 8, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Oct 14, 2010 description: "===== \n Description =====\n\nThe project consists of a module for scalar multiplication of rational points on an elliptic curve defined over a finite Galois field GF (2 ^ 163), which can be used in various cryptographic schemes.\n\nDeveloped by Macrypt Research Group, University of Los Llanos (Colombia)\nhttp://macrypt.unillanos.edu.\nContact: macrypt@unillanos.edu.co" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jfcastano name: scalar_multiplication status: Empty updated: Oct 27, 2010 wishbone-compliant: 0 - category: Communication controller created: Jul 19, 2010 description: "===== \n Description =====\n\n\n\n\nThis is a scan based serial communication block designed to safely and easily move data onto and off of a chip with a minimal number of pins. Performance is not a priority, however, we have found it to be sufficiently fast most any student project. It has been used, successfully, on many tapeouts.\n\nIncluded is an on-chip synthesizble scan block and an off-chip testbench to interact with it.\n\n\n\n\nThe on-chip scan block has six pad signals that go off-chip, and a configurable number of on-chip data input and output signals. Data signals from on-chip, going off-chip, can be latched into the scan chain and scanned out. Data signals going from off-chip to on-chip can be scanned into the chip, then stored into a latch that drives the output of the module. The buffering latch prevents data that is coming on-chip to not toggle randomly while the scan chain is active.\n\nDue to the buffering latches, complex internal interfaces can be emulated using the scan chain. For instance, an SRAM could be connected to a clock, chip select, write enable, 64-bit data-in, and 64-bit data-out, all of which are connected to the scan chain. The scan chain would need to be used a few times for each \"cycle\" of the SRAM. For instance, each time the clock signal toggles the scan chain would need to be completely reloaded. Although this process is slow, it works reliably.\n\nThe scan chain is implemented with a simple Perl-based script called deperlify to make the scan chain easily reconfigurable (a copy is included). A single configuration file generates a synthesizble scan block (for on-chip) and a testbench to test it, which allows rapid changes with minimal errors. The testbench has a number of tasks to easily access the on-chip structures.\n\nThis code was originally developed by David Fick at the University of Michigan VLSI Design/Automation Lab." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - Quanticles name: scan_based_serial_communication status: Stable svn-updated: Apr 9, 2013 updated: Jul 22, 2010 wishbone-compliant: 0 - category: Processor created: Sep 12, 2011 description: "===== \n Description =====\n\nThe SCARTS processor is small and flexible processor, which has been specifically designed for embedded systems with real-time requirements. The deterministic architecture (all instructions execute in a single cycle) and the support of conditional instructions significantly simplify the task of WCET analysis. For SW development there is a toolchain based on the GNU Binutils/GCC/GDB. Furthermore there is a port of the Red Hat Newlib, a C standard library for embedded systems.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\n RISC processor\n \n 122 instructions, all single cycle\n Most instructions conditional\n \n \n4 stage pipeline\n16-bit architecture\nData path extensible to 32 bit\n \n Almost the same ISA\n Higher performance, large address space\n Area increase about 70%\n \n16 registers (14 general purpose registers)\n16 interrupts, 16 traps\n4 framepointer\nExtensible with hardware accelerators" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jlechner - mwalter name: scarts status: Beta svn-updated: Oct 13, 2011 updated: Apr 4, 2012 wishbone-compliant: 0 - category: DSP core created: Jul 19, 2012 description: "===== \n Description =====\n\nThis is a structural modeling for IIR digital filters. It is developed in SystemC, however, it includes Matlab script and Simulink model as well. The developed code describes several structures for IIR filters, such as Transposed-form I, Transposed-form II, and Direct-form II. The implemented structures are well defined in the attached manual. Further, the detailed implementation is illustrated on the later file." language: SystemC license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: sciir status: Beta svn-updated: Jul 20, 2012 updated: Jul 20, 2012 wishbone-compliant: 0 - category: System controller created: Sep 29, 2008 description: "===== \n Description =====\n\nThis proyect is designed to adapt either a host system, or a perypherical controller system to a scsi bus.\nAlso the chip is a DMA controller for a host, in cluding a SRAM controller and a 32 to 8 bits converter for transmit data between a processor and the SCSI bus.\nIt is formed by 7 submodules that have specific functions that will be explain deeply later in this document.\nIt can operate in anyone of three posible states : disconected, connected as a target or connected as an Initiator.\n\nThe following is a summary of the SCSI protocol between host(initiator) and a target(controller):\n\n- The host selects a SCSI controller\n- The controller requests a command from the host specifying the task to be performed. example read disk\n- The controller interprets the command and execute it by reading data from the disk and the requesting the host accept the data.\n- When al data has been transfered, the controller requests that the host aacept the status byte.\n- After the host accepts the status form the controller, the controller disconnects from the bus leaving it free for the next operation.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Implement full SCSI Features:\n - Arbitration\n - Disconect\n - Reconect\n - Parity\n- Synchronous Data Transfers un to 4MB/sec\n- Can be use as Host adapter or peripheral adapter\n- Compliance with ANSI SCSI X3T9.2 specifications\n- compatible with most microprocessors through an 8 bit data bus.\n- SRAM Controller\n- 24 bit data counter.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- suspended\n \n\n\n \n \n \n\n===== \n Signal Descriptions- SCSI interface =====\n\nThe SCSI chip has two different kinds of signals, SCSI bus signals and Processor DMA signals:\n\n- SCSI interface:\n - I/O : controls the direction of data movement on the SCSI bus with respect to the initiator. When asserted, data is input to the initiator. I/O is an input signal when the SCSI chip is operating as an initiator, and output signal when is operating as a target.\n - MSG_N: is asserted during the message phase, is an input when the chip is operating as an initiator and an output when operating as a target.\n - C_N/D : is asserted when there is a control information on the SCSI data bus and de-asserted for data. is an input when the chip is operating as an initiator and an output when operating as a target.\n - BSY_N : is asserted by the SCSI chip as an output when attempting to arbitrate for the SCSI bus or when connected as a target. When the chip is conected as an initiator, BSY_N operates as an input.\n - SEL_N : The SCSI chip assert it as an out put when trying to select or reselect another SCSI device. The SCSI receives SEL_N as an input when its being selected.\n - DBP_N : SCSI bus parity bit.\n - DB_N : SCSI bus data bits 0-7\n - ATN_N : signals that the initiator has a message to transfer. Is an output signal when the chip is operating as an initiator and an input when connected as a target.\n - ACK_N : acknowledges a REQ/ACK data transfer handshake. Is an output signal when the chip is operating as an initiator and an input when connected as a target.\n - REQ_N : requests an REQ/ACK data transfer. is an input signal whe the chip is operating as an initiator and an output when operating as a target.\n\n- Processor interface:\n - CLK: 10MHz square wave clock.\n - DRQ_N/DRQ : interfaces with an external DMA controller and forms the DRQ/DACK handshake for data byte transfers. interfaces with an external buffer. This signal is open drain.\n - DACK_N/RCS_N : interfaces with external DMA controller. when asserted, all bus transfers are to or from the data register regardless of the contents of the address register. Interfaces with an external buffer. When is asserted , WE_N and RE_N are enable as outputs.\n - INTRQ : signals a local microprocesor or host that a SCSI chip command has terminated or the SCSI interface needs service.\n - D : 0-7 Local data bus.\n - A0 : is used to access an internal register during the indirect addressing mode operation. A=0 the address of the desired registeris loaded in to the address register during a write cycle.A = 1 the register selected by the address register is accessed\n - CS_N : when is asserted , WE_N and RE_N are enable as input signals for accesing registers within the chip.\n - WE_N : is an input signal and enables writing to an internal register when used with CS_N. is an output signal and enables writing to the external buffer whenused with RCS_N. is a tri-state signal.\n - RE_N : is an input signal and enables reading to an internal register when used with CS_N. is an output signal and enables reading to the external buffer whenused with RCS_N. is a tri-state signal.\n - ALE : With the trailing edge of ALE, the address on the local data bus is latched into the address register.\n - MR_N : when asserted places the SCSI chip into a disconnect state. All SCSI signals are placed in a passive state." language: Verilog license: unknown maintainers: - chikibu name: scsi_chip status: Alpha svn-updated: Mar 10, 2009 updated: Oct 8, 2008 wishbone-compliant: 0 - category: Communication controller created: Sep 1, 2013 description: "===== \n Description =====\n\nThe Wishbone SD Card Controller IP Core is MMC/SD communication controller designed to be\nused in a System-on-Chip. The IP core provides a simple interface for any CPU with Wishbone\nbus. The communication between the MMC/SD card controller and MMC/SD card is performed\naccording to the MMC/SD protocol.\n\n \n\n\n \n \n \n\n===== \n Introduction =====\n\nThis core is based on the \"sd card controller\" project from \nhttp://opencores.org/project,sdcard_mass_storage_controller \nbut has been largely rewritten. A lot of effort has been put \nforth to make the core more generic and easily usable \nwith OSs like Linux.\n- data transfer commands are not fixed\n- data transfer block size is configurable\n- multiple block transfer support\n- R2 responses (136 bit) support\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe MMC/SD card controller provides following features:\n\n- 1- or 4-bit MMC/SD mode (does not support SPI mode),\n- 32-bit Wishbone interface,\n- DMA engine for data transfers,\n- Interrupt generation on completion of data and command transactions,\n- Configurable data transfer block size,\n- Support for any command code (including multiple data block tranfser),\n- Support for R1, R1b, R2(136-bit), R3, R6 and R7 responses.\n \n\n\n \n \n \n\n===== \n Documentation =====\n\nThe documentation is located in the doc/ directory of the svn repository.\n \n\n\n \n \n \n\n===== \n Examples =====\n\nA sample ORPSoC project that make use of this core is located at:\n\nhttps://github.com/mczerski/orpsoc-de0_nano\n\nThe project is based on de0_nano board with custom made expansion board\nwith SD Card connector.\n\nThere is also u-boot project port for this board located at:\n\nhttps://github.com/mczerski/u-boot\n\nThis u-boot project contains driver for Wishbone SD Card Controller IP Core\nand can be configured for de0_nano board (with custom made expansion board).\n\nAlso in the plan is the driver for Linux. The initial work can be found at:\n\nhttps://github.com/mczerski/linux - de0_nano branch\n\nthe driver is named ocsdc and is located in drivers/mmc/host directory.\n \n\n\n \n \n \n\n===== \n TODO =====\n\n- top level testbench cleanup (sd_controller_top_tb.sv)\n- rx/tx fifo treshold to do block transfers rather than many single word transfers\n- maybe one fifo rather than two fifos (rx and tx) would suffice since the transfer \n\tbetween card and controller is always half-duplex\n- read only and card detect signals support\n- timeout watchdog for data transfers" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rozpruwacz - jclaytons name: sd_card_controller status: FPGA proven svn-updated: Sep 10, 2013 updated: Sep 10, 2013 wishbone-compliant: 1 - category: Communication controller created: Mar 27, 2009 description: "===== \n Introduction =====\n\nThe \"sd card controller\" is a Secure Digital Card Host Controller, which main focus is to provide fast and simple interface to SD/SDHC cards. One of the main goal with this project is that the controller should be usable as a system disk contain a file system. Therefore the core has been developed with features a system with operative system will benefit from. \nThe design also include a simplified model of a SD-card to test against.\n \n\n\n\n\nhttp://www.opencores.org/?do=project&who=sdcard_mass_storage_controller&page=overview\n2009-05-20\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe core is a combined SD/SDHC controller, for Secure Digital-card. \n\nTwo designs is available, one full-feature core utilizing DMA and one smaller for PIO.\n\nThe idea with the full-feature design is that it should provide as much performance as possible. Therefore it's build to stall the CPU as little as possible and offload it some computations, this is archived by:\n\n Error and flow control performed mainly in hardware i.e user specify when sending a command what kind of error check he wants to be performed. Result is then set in the response registers also can be set to generate interrupt.\n Command generation for writing/reading block of data is performed in hardware\n Buffer descriptors is used to to queue read/write data transmissions (Less delay between data transmissions) \n DMA for minimal CPU interruption as possible. \n \n\n \nThe small design utilize the Versatile FIFO, together with 4 control register for operation.\n \n\n\n \n \n \n\n===== \n Features =====\n\nFull-feature core\n\n\n 32-bit Wishbone Interface\n DMA\n Buffer Descriptor \n Compliant with SD Host Controller Spec version 2.0 \n Support SD 4-bit mode \n Interrupt-on completion of Data and Command transmission \n Write/Read FIFO with variable size \n Internal implementation of CRC16 for data lines and CRC7 for command line \n \n\n\n\nSmall-FIFO core\n\n\n 8-bit Wishbone Interface\n PIO\n Compliant with SD Host Controller Spec version 2.0 \n Support SD 4-bit mode \n Simple SW interface, 4 FIFO + 4 Registers \n \n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Limitations =====\n\nData block length fixed to 512 Byte\nNo SD 1-bit mode\nNo SPI mode\nNo Hot Insertion (i.e. inserting a card when the bus is operating)\nNo multiple block operations/pre erase" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tac2 name: sdcard_mass_storage_controller status: FPGA proven svn-updated: Oct 15, 2010 updated: May 3, 2013 wishbone-compliant: 1 - category: Communication controller created: Oct 19, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - rkastl name: sdhc-sc-core status: Mature svn-updated: Jan 7, 2011 updated: Jan 4, 2011 wishbone-compliant: 0 - category: Memory core created: Jan 3, 2012 description: "===== \n Description =====\n\nFeature:\n\xE2\x80\xA2 8/16/32 Configurable SDRAM data width\n\xE2\x80\xA2 Wish Bone compatible\n\xE2\x80\xA2 Application clock and SDRAM clock can be async\n\xE2\x80\xA2 Programmable column address\n\xE2\x80\xA2 Support for industry-standard SDRAM devices and modules\n\xE2\x80\xA2 Supports all standard SDRAM functions\n\xE2\x80\xA2 Fully Synchronous; All signals registered on positive edge of system clock\n\xE2\x80\xA2 One chip-select signals\n\xE2\x80\xA2 Support SDRAM with four bank\n\xE2\x80\xA2 Programmable CAS latency\n\xE2\x80\xA2 Data mask signals for partial write operations\n\xE2\x80\xA2 Bank management architecture, which minimizes latency\n\xE2\x80\xA2 Automatic controlled refresh\n\xE2\x80\xA2 Static synchronous design\n\xE2\x80\xA2 Fully synthesizable\n\n \n\n\n \n \n \n\n===== \n Functional Block Diagram =====\n\n\n \n\n\n \n \n \n\n===== \n FPGA bench Mark =====\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nStable RTL ver 0.1 is available\n \n\n\n \n \n \n\n===== \n Frequently Asked Question =====\n\n1. Design and implementation language used in the IP\n Design implementation is done Verilog and System verilog language\n\n2. What are the SDRAM Bus width are supported by the IP?\n This IP Supports 8/16/32 Bit interface\n\n3. What are the Application Bus width are supported by the IP?\n This IP Supports only 32 bit Application Bus width\n\n4. Can Application clock and SDRAM clock be Asynchronous to each other?\n Yes, IP support both Synchronous and Asynchronous Application clock and SDRAM clock\n\n5.Is the application layer is compatible to wish-bone standard?.\n Yes, Application Layer is wishbone compatible.\n\n6.Is SDRAM cores is also available with custom interface?\n Yes. SDRAM core is separately available with automated test-bench.\n\n7.Test bench scripts are compatible to which tool?\n Verification scripts are compatible to model simulator" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - dinesha name: sdr_ctrl status: Stable svn-updated: Jun 17, 2013 updated: Jun 17, 2014 wishbone-compliant: 1 - category: System controller created: Sep 25, 2001 description: "===== \n Description =====\n\nThe Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications.\n\nBy default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such as Samsung KM432S2030CT and Fujitsu MB81F643242B. Easy modifications allows the core to work with different capacity SDRAMs. Most of the critical parameters are defines in a global include file allowing easy reconfigurability of the core.\n\nThe core handles much of the low level functions such as address multiplexing, refresh generation and busy status generation. In addtion, the non-trivial powerup initialization sequence is also handled transparently to the host. Flexible refresh generation permits burst refresh, normal refresh or everything in between. The SDRAM mode-register can also be reprogrammed on the fly by the host, although the core intializes the MRS with a default value. This value can be compile-time adjustable.\n\nThe present design only supports 1 transfer per access. An access is a host's request for a read or a write to the SDRAM. A transfer is any data size from 1 byte, 1 word (16bit) or 1 long-word (32 bit). As soon as a multi-longword (i.e. burst) data transfer protocol for the OR1K is adopted, variants of the SDRAM controller supporting it will be offered.\n\nThe core also includes a set of synthesiable \"test\" modules. When enabled for compilation, these test modules becomes a host to the SDRAM controller and issues a series of read/write test sequences to the SDRAM. This allows designers working on FPGA/CPLD platforms to turn the SDRAM controller core into a \"stand-alone\" SDRAM tester.\n\nThe core has been sucessfully tested with a Samsung KM416S1120D SDRAM on Altera Flex10K20 FPGA and :Lattice isp3256 CPLD devices (using the built-in tester).\n \n\n\n \n \n \n\n===== \n IMAGE: intefacing block diagram.gif =====\n\nFILE: intefacing block diagram.gif\nDESCRIPTION: Picture 1: Interfacing block diagram\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Initial stable version avaible for down load : Use tag \"sdram_8Mb_2Mx32_020200\" \n- Fully parameterized version to be available. Use tag \"sdram_param\" \n- Working documentation (72 KB) is available in Adobe PDF format." language: Verilog license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - jlee name: sdram status: Alpha svn-updated: Mar 10, 2009 updated: Oct 15, 2001 wishbone-compliant: 0 - category: Memory core created: Sep 11, 2009 description: "===== \n Description =====\n\nDDR SDRAM controller core targeted at the mt46v32m16 chip on the Spartan3e Starter Board. The testbench synthesizes and runs on the targeted hardware. Additionally I've integrated this controller core into an SoC design consisting of a T80 soft cpu with a VGA controller, Flash controller and UART.\n\nThe design is more or less frozen, unless I change out soft CPUs and need to integrate again. Further changes will be driven by bug discoveries/reports." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lynn0p name: sdram_controller status: Beta svn-updated: Oct 11, 2009 updated: Sep 16, 2012 wishbone-compliant: 0 - category: Crypto core created: Jun 24, 2013 description: "===== \n Description =====\n\nRuns at 199.788MHz on Xilinx's 28nm Kintex 7 speed grade 3 device. Processing speed: 1.598 Gbits per second." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - feketebv name: securehash256bits status: Alpha svn-updated: Jan 14, 2014 updated: Apr 5, 2014 wishbone-compliant: 0 - category: Other created: Aug 17, 2009 description: "===== \n Description =====\n\nThis is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap penalties, and is configurable between local (smith-waterman) and global (needleman-wunsch) alignment algorithms by setting an internal register. All code is in Verilog." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - fentonc name: seqalign status: Alpha svn-updated: Aug 17, 2009 updated: Aug 17, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Mar 28, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Tina1990 name: serdes status: Empty updated: Mar 28, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Oct 24, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mghicho name: serial-transmitter-receiver status: Empty updated: Nov 5, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Nov 19, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - water_flq name: serial_adder status: Empty updated: Nov 20, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Apr 1, 2003 description: "===== \n Description =====\n\nThe serial_divide_uu is a Verilog coded module that performs binary division. It is fully parameterized, and works in a serial fashion. The number of clock cycles required to complete a divide operation is equal to the number of bits in the quotient plus one.\n\nThis module has been tested and debugged in actual hardware on a Xilinx XC2S200E FPGA. It was used to divide pulse width by period in a pulse-width-modulation measurement application (ADXL202E 2-axis MEMS accelerometers.)\n\nThe widths of the signals are configurable by parameters, as follows:\n\nM_PP = Bit width of the dividend\nN_PP = Bit width of the divisor\nR_PP = Remainder bits desired\nS_PP = Skipped quotient bits\n\nThe skipped quotient bits parameter provides a way to prevent the divider from calculating the full M_PP+R_PP output bits, in case some of the leading bits are already known to be zero. This is the case, for example, when dividing two quantities to obtain a result that is a fraction between 0 and 1 (as when measuring PWM signals). In that case the integer portion of the quotient is always zero, and therefore it need not be calculated.\n\nFor those who have the luxury of many clock cycles to use up, this module can provide division results of arbitrary precision.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Fully parameterized Verilog code, tested and debugged\n- No testbench\n- Calculates roughly one bit of output per clock cycle.\n- Parameter \"HELD_OUTPUT_PP\" allows user to trade off extra flip-flops for the ability to hold the stable output of the previous divide, during the next divide operation.\n- Useful for DSP systems.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Try it out, this module works. \n- Code is very well commented, with a description of operation in the header, which suffices for documentation. \n- Thanks to David Sala for writing and submitting a VHDL testbench and VHDL version of this code. \n\n\n \n\n\n \n \n \n\n===== \n VHDL code & testbench =====\n\nDavid Sala has gracious translated this module into VHDL code, and provided a testbench for it. This should improve this project and make it accessible and useful to more people. Thanks David!" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jclaytons name: serial_div_uu status: Stable svn-updated: Aug 19, 2009 updated: Mar 10, 2013 wishbone-compliant: 0 - category: Communication controller created: May 8, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - manasa41 name: serial_peripheral_interface status: Empty updated: May 8, 2013 wishbone-compliant: 0 - category: Prototype board created: Sep 25, 2001 description: "===== \n Description =====\n\nOpenCores Reference Platform 2 (OCRP-2) is full-size length add-in PCI board. It includes two FPGA chips, video D/A and A/D converters, SDRAM memory, FLASH memory, PLD chip, USB, EIA232 and Ethernet PHY chips. It is designed for a debugging and verification process for several of our cores. See a block diagram for details. \n\nOne special function of this board is to provide a method for a remote test of cores. The board will be used via web based interface. It will be possible to download design to the board and use a JAVA based logic analyzer and signal generator to debug a particular core. This interface will be similar to Hewlett Packard's 16550 Logic Analyzer which is possible to be used remotely via X session. \n\nSecond possible use is to use it as a stand alone board. FPGAs are loaded via PC's printer port with centronics cable and external power supply must be provided. \n\nIt is designed to be used as a base platform to port Linux, RTEMS and eCos operating systems to OpenRISC architecture and to write device drivers for our peripheral cores. \n \n\n\n \n \n \n\n===== \n IMAGE: sfpga_block.gif =====\n\nFILE: sfpga_block.gif\nDESCRIPTION: Picture 1: Block diagaram\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n\npreliminary design schematic is available as Adobe PDF document ~125 kb\nor as Protel schematics ~100 kb\ncurrently working on PCI interface and FPGAs configuration schematics\nthe design files will be updated in the following days\n\n \n\n\n \n \n \n\n===== \n Acknowledgments =====\n\n\nthanks to all those who showed interest in the design so far, providing also support with new ideeas and links to component datasheets;\nspecial thanks to woodyj@bitstream.net for his guidelines and hints regarding the Ethernet design part;\nspecial thanks to wamnet@gte.net for his kind support with hints and tips in designing with Protel99." language: schematic license: unknown maintainers: - olupas name: sfpga status: Planning svn-updated: Mar 10, 2009 updated: Oct 15, 2001 wishbone-compliant: 0 - alternate-download: https://github.com/errordeveloper/sftb/archive/master.zip category: Testing / Verification created: Jul 4, 2011 description: "===== \n Source Code =====\n\nI should push the git repo into OC SVN once all features are implemented.\n\nAt the moment it is hosted on GitHub ( https://github.com/errordeveloper/sftb ).\n\nPlease `git clone git://github.com/errordeveloper/sftb` or download a snapshot\nin zip ( https://github.com/errordeveloper/sftb/zipball/master ) or tar\n( https://github.com/errordeveloper/sftb/tarball/master ).\n\nThere is minimum of documentation in the source code (README.md) and\nI am planning to write more, also see my blog ( http://new-synth.info/tagged/SFTB )\nfor the updates on this project.\n\nHope you will find this useful!" homepage: https://github.com/errordeveloper/sftb language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - errordeveloper name: sftb status: Alpha updated: Jul 4, 2011 wishbone-compliant: 0 - category: Communication controller created: Feb 8, 2012 description: "===== \n Description =====\n\nGeneric SGMII / 1000X module that can be connected to any transceiver technology.\nThis core has been verified with 88E1111 Phy\n- Autonegotiation\n- Rx & Tx in 1000Mbps mode\n- Slow bit rate ~ 10Mbps\nI don't have adequate tools to verify at full speed. \nI appreciate any effort to verify and report bugs. \nEveryone is welcome to try this core. \nI can be contacted at jefflieu@fpga-ipcores.com for other license/support/bring-up issue. Btw, if you think it's useful to you, you can show your appreciation by donating to Paypal account: jefflieu@fpga-ipcores.com" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - jefflieu name: sgmii status: Design done svn-updated: Nov 18, 2012 updated: Aug 1, 2014 wishbone-compliant: 0 - alternate-download: https://github.com/vishpbharadwaj/SHA3-VHDL/archive/master.zip category: Crypto core created: Sep 12, 2014 description: "===== \n Description =====\n\nThis project is the hardware implementation of SHA-3 (keccak) Hash function. SHA-3, originally known as Keccak, is a cryptographic hash function and is the winner of the NIST hash function competition. Because of the successful attacks on MD5, SHA-0 and theoretical attacks on SHA-1, NIST perceived a need for an alternative, dissimilar cryptographic hash, which became SHA-3. This is the implementation of High speed core.\n\nKeccak is a family of hash functions that is based on the sponge construction, and hence is a sponge function family. In Keccak, the underlying function is a permutation chosen in a set of seven Keccak-f permutations, denoted Keccak-f[b], where b \xE2\x88\x88 {25, 50, 100, 200, 400, 800, 1600} is the width of the permutation. The width of the permutation is also the width of the state in the sponge construction.\n\nCurrently the project files is on GitHub at https://github.com/vishpbharadwaj/SHA3-VHDL \n\nThe reference links are given below\n\nhttp://keccak.noekeon.org/specs_summary.html \n\nhttp://en.wikipedia.org/wiki/SHA3 \n\nhttp://keccak.noekeon.org/Keccak-implementation-3.2.pdf\n \n\n\n \n \n \n\n===== \n License =====\n\nThis project is licensed under LGPL license, version 3.0(LGPL-3.0)\n\nhttp://opensource.org/licenses/LGPL-3.0" homepage: https://github.com/vishpbharadwaj/SHA3-VHDL language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vishp name: sha-3 status: FPGA proven updated: Nov 28, 2014 wishbone-compliant: 0 - category: Crypto core created: Oct 1, 2002 description: "===== \n Description =====\n\nVerilog Implementation of SHA1 Secure Hash Algorithm\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Initial Release" language: Verilog license: custom licensetext: "The information and description contained herein is the\nproperty of Paul Hartke. \n\nPermission is granted for any reuse of this information\nand description as long as this copyright notice is\npreserved. Modifications may be made as long as this\nnotice is preserved.\nThis code is made available \"as is\". There is no warranty,\nso use it at your own risk.\nDocumentation? \"Use the source, Luke!\"\n" maintainers: - phartke - leon name: sha1 status: Alpha svn-updated: Mar 10, 2009 updated: Jul 8, 2004 wishbone-compliant: 0 - category: Crypto core created: Mar 6, 2013 description: "===== \n Description =====\n\n\n \n\n===== \n Organization =====" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: sha256 status: FPGA proven svn-updated: Apr 16, 2013 updated: Apr 16, 2013 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nVHDL implementation of the SHA-256 hashing algorithm. This project includes .do files for performing a simulation on ModelSim." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: sha256core status: FPGA proven svn-updated: Aug 8, 2013 updated: Aug 8, 2013 wishbone-compliant: 0 - category: Crypto core created: Nov 9, 2012 description: "===== \n Description =====\n\nSHA-3, originally known as Keccak [1], is a cryptographic hash function selected as the winner \nof the NIST hash function competition [2]. Because of the successful attacks on MD5, SHA-0 and\ntheoretical attacks on SHA-1, NIST perceived a need for an alternative, dissimilar cryptographic\nhash, which became SHA-3 [3].\n\nNIST requires the candidate algorithms to support at least four different output lengths {224,256,384,512}\nwith associated security levels [4]. \xE2\x80\x9CSHA-3 512\xE2\x80\x9D, in which output length is 512-bit, \nhas the highest security level among all SHA-3 variants.\n\nThis project has implemented \xE2\x80\x9CSHA-3 512\xE2\x80\x9D hash function.\n\nThis project has implemented two cores, one (high-throughput) core designed to work in\nhigh clock frequency (150 MHz) dedicated to ASIC or expensive FPGA (Virtex 6),\nanother (low-throughput) core designed to work in low clock frequency (100 MHz)\ndedicated to cheap FPGA (Spartan 3). Because in many systems the clock frequency is\nfixed for the entire chip, so even if the hash core can reach a high frequency it has to be\nclocked at a lower frequency [5].\n\nThe code is FPGA-vendor independent, having been fully optimized, using only one\nclock domain, not using any latch.\n\n[1] Guido Bertoni, Joan Daemen, Micha\xC3\xABl Peeters and Gilles Van Assche,\n \xE2\x80\x9CThe Keccak sponge function family: Specifications summary\xE2\x80\x9D, \n http://keccak.noekeon.org/specs_summary.html\n\n[2] \xE2\x80\x9CNIST Selects Winner of Secure Hash Algorithm (SHA-3) Competition\xE2\x80\x9D, \n NIST. Oct. 2012. \n http://www.nist.gov/itl/csd/sha-100212.cfm\n\n[3] \xE2\x80\x9CSHA-3\xE2\x80\x9D, \n Wikipedia, the free encyclopedia, \n http://en.wikipedia.org/wiki/SHA3\n\n[4] \xE2\x80\x9CAnnouncing request for candidate algorithm nominations for a new cryptographic hash algorithm (SHA-3) family\xE2\x80\x9D, \n Federal Register Notices 72 (2007), no. 212, 62212\xE2\x80\x9362220.\n http://csrc.nist.gov/groups/ST/hash/index.html\n\n[5] Keccak implementation overview, version 3.2,\n http://keccak.noekeon.org/Keccak-implementation-3.2.pdf\n \n\n\n \n \n \n\n===== \n Document =====\n\nDocument version 0.1\n \n\n\n \n \n \n\n===== \n Synthesis result =====\n\nThe synthesis software is Xilinx ISE version 14.4. \n\n\n\n\n\nThe low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900).\n\n\n\n\nNumber of Slices: 2,321 \nNumber of Slice Flip Flops: 2,346 \nNumber of 4 input LUTs: 4,499 \nNumber of bonded IOBs: 552 \nNumber of GCLKs: 1 \nMaximum Frequency: 117.3 MHz \n\n\n\n\nThe high throughput core has been synthesized targeting an expensive Virtex 6 (XC6VLX240T-1FF1156).\n\n\n\n\nNumber of Slice Registers: 2,220 \nNumber of Slice LUTs: 9,895 \nNumber of fully used LUT-FF pairs:1,673 \nNumber of bonded IOBs: 585 \nNumber of BUFG/BUFGCTRLs: 1 \nMaximum Frequency: 188.9 MHz \n\n \n\n\n \n \n \n\n===== \n Throughput =====\n\nThe low throughput core: 2.4 G bit / second if clock frequency is 100 MHz.\n\n\n\n\n\nThe high throughput core: 7.2 G bit / second if clock frequency is 150 MHz.\n\n\n\n \n\n\n \n \n \n\n===== \n License =====\n\nThis project is licensed under the Apache License, version 2." language: Verilog license: Apache License Version 2.0 licenselink: http://opensource.org/licenses/Apache-2.0 maintainers: [] name: sha3 status: FPGA proven svn-updated: Jan 29, 2013 updated: May 27, 2014 wishbone-compliant: 0 - category: Crypto core created: May 20, 2004 description: "===== \n Description =====\n\nThis is a collection of SHA(Secure Hash Algorithm) cores. These include SHA-1, SHA-2 algorithms.\n These cores are non-pipelined version of SHA, and have simple interfaces with the host side. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Support SHA-1(160), SHA-2(256/384/512)\n- Use a simple 32-bit I/O bus interface\n- High performance\n- Share hardware between different SHA processing\n- Can operate up to 200MHz at 0.18um Standard cell design\n- Written in VerilogHDL\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Initial release\n \n\n\n \n \n \n\n===== \n TODO =====\n\n- Combine SHA1/SHA2 in a single core\n- Make it smaller and faster!" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - marsgod name: sha_core status: Design done svn-updated: Mar 10, 2009 updated: Dec 17, 2012 wishbone-compliant: 0 - category: Other created: Oct 16, 2012 description: "===== \n Description =====\n\nPublic domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.\nThe resource consumption is very low (24-bit version of the DAC consumed 5% of slices in xc3s200).\n \n\n\n \n \n \n\n===== \n Detailed description =====\n\nThis project implements 2nd order DAC, which I have created when \nI needed to add the voice output to one of my FPGA based systems.\n\nThe converter generates 1-bit digital signal on the dout output.\nYou need to connect a simple RC lowpass filter to convert it into\nthe analog signal.\n\nThere are directories containing two different implementations:\n\n\tdsm2\n\tallows to obtain higher clock frequency, and therefore \n higher oversampling ratio, but number of rising and falling\n slopes in time unit depends on signal value. Therefore\n you may experience nonlinear distortions if those two slopes\n are not symmetrical.\n\tdsm3\n The output of the DAC is updated once every three clock pulses.\n If there is a '1' on the DAC output, the sequence '110' is generated\n on the dout output. If there is a '0' on the DAC output, the sequence\n '100' is generated. Therefore we always have one rising slope and one \n falling slope generated in each DAC cycle.\n Unfortunately this implementation accepts lower clock frequencies,\n so the oversampling ratio is lower\n\n\nAdditionally in each directory there are two equivalent implementations.\nThe first one (dac_dsm2v.vhd, dac_dsm3v.vhd) uses the variables in the process\n(which maybe not acceptable for some synthesis tools).\nThe second one (dac_dsm2.vhd, dac_dsm3.vhd) is slightly less readable,\nbut should be easier to synthesize.\nThe top entity (dac_dsm2_top.vhd, dac_dsm3_top.vhd) instantiates the DAC for synthesis\n(however before synthesis you should set the number of bits, setting\nthe default value of the \"nbits\" generic).\n\nFor the dac_dsm2_top.vhd with Xilinx ISE 9.2 i've got the following results:\nSpeed oriented synthesis for device xc3s200, package ft256, speed -5 resulted with\n100MHz clock at 4% slice utilization (so you can get even 1000 oversampling ratio\nfor 100kHz sampling frequency).\nSynthesis of 24-bit version of the DAC resulted for the same chip in 5% slice\nutilization and also 100MHz fclk max.\n\nTo check DAC performance without putting it into real hardware, you can\nrun \"make\" command in the appropriate directory (it requires free tools:\nghdl, python and pylab). You'll see the spectra of the output signal \n(before low pass filtering) consisting of three sinusoids.\n\nThe first version of this DAC was published in the alt.sources group\nas \"VHDL source for Sigma-Delta DAC converter with dual loop\".\nThis post is archived in the Google groups and\nin the funet archive.\n\nAll sources are published as PUBLIC DOMAIN." language: VHDL license: Public domain maintainers: - wzab name: sigma_delta_dac_dual_loop status: Mature svn-updated: Oct 16, 2012 updated: May 1, 2014 wishbone-compliant: 0 - category: Arithmetic core created: Mar 6, 2013 description: "===== \n Description =====\n\nA divider that calculates the quotient and remainder of a division operation in multiple clock cycles. The dividend, divisor, quotient and remainder are all 32-bit signed integers. By taking the advantage of a shifter that can shift more than one bit (up to 9 bits) during each cycle of computation, it takes less cycles to finish than a radix-2 nonrestoring divider." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - m99 name: signed_integer_divider status: FPGA proven svn-updated: Mar 6, 2013 updated: Mar 8, 2013 wishbone-compliant: 0 - category: Crypto core created: Aug 5, 2014 description: "===== \n Description =====\n\nThe code presented here implements the bit-serialized SIMON block cipher. Please check the following publication for the details of the implementation: A. Aysu, E. Gulcan, P. Schaumont, \"SIMON Says, Break Area Records of Block Ciphers on FPGAs,\", IEEE Embedded Systems Letters, 6(2):37-40, April 2014" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - aydinay name: simon_core status: FPGA proven svn-updated: Aug 6, 2014 updated: Aug 6, 2014 wishbone-compliant: 0 - category: System on Chip created: Nov 28, 2005 description: "===== \n Description =====\n\nSimpCon is a specification for a simple and efficient system-on-chip (SoC) interconnect. SimpCon provides single cycle commands and provisions for pipelining of read and write connections. SimpCon is public domain and freely available.\n\nTranslation to and from Wishbone, the opencores standard interface, are provided.\n\nDocumentation is in the CVS at http://www.opencores.org/cvsweb.cgi/~checkout~/simpcon/doc/simpcon.pdf\n\nA paper published at the Austrochip on SimpCon is available from:\nhttp://www.jopdesign.com/doc/simpcon_austrochip2007.pdf\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Synchronous interface\n- Master/Slave connection\n- Piplined transactions\n- Low resource usage\n- Simple to implement\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- First draft document written\n- Master implemented for JOP in Cyclone and Spartan-3\n- Slave for SRAM access (read pipeline level 2)\n- JOP IO devices connected as SimpCon slaves\n- Wishbone/SimpCon bridge available" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - martin name: simpcon status: FPGA proven svn-updated: Jun 1, 2009 updated: Nov 13, 2007 wishbone-compliant: 0 - category: System on Chip created: Sep 4, 2012 description: "===== \n Description =====\n\nThe Simple Bus Architecture (SBA) is an architecture made up software tools and intellectual property cores (IP Cores) interconnected by buses set through simple and clear rules, that allow the implementation of an embedded system (SoC); additionally, basic templates are provided to achieve a rapid design. Its structure gives it an inherent educative value. The VHDL code that implements this architecture is highly portable. \n\nThe master core developed as special state machine, has the ability to perform basic data flow and processing, similar to microprocessor but without the high consumption of logic resources of it.\n\nThe SBA is an application and simplified version of the Wishbone specification. The SBA implements the minimum essential subset of Wishbone signals interface, and can be easily connected with simple Wishbone IP Cores. The SBA defines three types of cores: masters, slaves and auxiliaries. Several slaves IP Cores were developed following the SBA architecture, many of them to implement virtual instruments." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mrisco name: simple_bus_architecture status: Empty updated: Jan 4, 2014 wishbone-compliant: 0 - category: Other created: Jan 3, 2005 description: "===== \n Simple FM Receiver =====\n\nSimple implementation of FM Receiver to demodulate square wave signal modulated\nin FM. This design uses PLL to demodulate FM modulated signal.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Synthesizable\n - This design can be synthesize using Xilinx 6.3i\n - This design can be simulated and synthesized using http://asim.lip6.fr/recherche/alliance/ (Alliance 5.0)\n- Simple\n - Use it to understand PLL to see how FM Receiver works.\n - Good for introduction in design process.\n - Modular design, can be use for other design." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - arif_endro name: simple_fm_receiver status: FPGA proven svn-updated: Jun 27, 2010 updated: Mar 19, 2010 wishbone-compliant: 0 - category: Other created: Dec 2, 2002 description: "===== \n Description =====\n\nSimple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface).\nVery simple, very small.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Up to 8 GPIO pins per core\n- Each GPIO pin individually programmable as either input or output\n- Static synchronous design\n- Fully synthesisable\n- 11 LUTs in a Spartan-II, 43 LCELLs in an ACEX\n \n\n\n \n \n \n\n===== \n Status =====\n\nDesign is finished and available in Verilog from OpenCores CVS." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rherveille name: simple_gpio status: FPGA proven svn-updated: Mar 10, 2009 updated: Sep 7, 2009 wishbone-compliant: 1 - category: Other created: Dec 2, 2002 description: "===== \n Description =====\n\nSimple programmable interrupt controller. It supports up to 8 interrupt sources. Polarity and sensitivity (either edge or level) is programmable per interrupt source. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances.\nVery simple, very small.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Up to 8 interrupt sources\n- Sensitivity (edge/level) programmable per interrupt source\n- Polarity programmable per source\n- Static synchronous design\n- Fully synthesisable\n- 48 LUTs in a Spartan-II, 83 LCELLs in an ACEX\n \n\n\n \n \n \n\n===== \n Status =====\n\nDesign is finished and available in Verilog from OpenCores CVS." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rherveille name: simple_pic status: FPGA proven svn-updated: Mar 10, 2009 updated: Mar 4, 2008 wishbone-compliant: 1 - category: Communication controller created: Dec 16, 2002 description: "===== \n Description =====\n\nEnhanced version of the Serial Peripheral Interface available on Motorola's MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation.\nAs with the SPI found in MC68HC11 processors the core features programmable clock phase (CPHA) and clock polarity (CPOL). The core features an 8bit wishbone interface.\nVery simple, very small.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Compatible with Motorola's SPI specifications\n- Enhanced Motorola MC68HC11 Serial Peripheral Interface\n- 4 entries deep read FIFO\n- 4 entries deep write FIFO\n- Interrupt generation after 1, 2, 3, or 4 transfered bytes\n- 8 bit WISHBONE RevB.3 Classic interface\n- Operates from a wide range of input clock frequencies\n- Static synchronous design\n- Fully synthesizable\n- 130LUTs in a Spartan-II, 230 LCELLs in an ACEX\n \n\n\n \n \n \n\n===== \n Status =====\n\nDesign is finished and available in Verilog from OpenCores CVS." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rherveille name: simple_spi status: FPGA proven svn-updated: Mar 13, 2009 updated: Jul 15, 2014 wishbone-compliant: 1 - category: Arithmetic core created: May 1, 2011 description: '' language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hossam_fadeel name: simple_traffic_light_controller status: Empty updated: May 4, 2011 wishbone-compliant: 0 - category: Communication controller created: Apr 17, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: simplespimaster status: Empty updated: Jul 24, 2013 wishbone-compliant: 0 - category: Crypto core created: Sep 19, 2012 description: "===== \n Description =====\n\nSimple to use SHA-2 algorithm\n\nIs a VHDL implementation of SHA-224/256 core.\nMajor project choice is semplicity: just feed core with message a chunk per clock and wait for result.\n\nItalian (sorry) documentation included." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - shadow7853 name: simpletousesha2 status: Design done svn-updated: Sep 19, 2012 updated: Sep 19, 2012 wishbone-compliant: 0 - category: Memory core created: Nov 18, 2008 description: "===== \n Description =====\n\nThe simu_mem project provides functional simulation models of commercially available RAMs. \n\nAdvantages of the simu_mem models\n=================================\n\n1. Consumes few simulator memory if only few memory locations are accessed because it internally uses a linked list.\n2. Simulates quickly because it does not contain timing information. Fast simulator startup time because of the linked list.\n3. Usable for any data and address bus width.\n4. Works at any clock frequency.\n5. Programmed in VHDL.\n\nWhen the simu_mem models will not be useful\n===========================================\n1. When it has to be synthesized.\n2. When a timing model is required. Ask your RAM vendor for a timing model.\n3. When your design is in Verilog.\n\nWhere are the simulation models?\n================================\n\nThe RAM simulation models are located in rtl/vhdl/. They were tested only with the Modelsim simulator.\n\nHow were the models tested?\n===========================\n\nA testbench exists for ZBT RAMs. sim/rtl_sim/bin/sim.sh will execute the simulation. In order to run this test you must replace bench/verilog/samsung/k7n643645m_R03.v with the original simulation file from Samsung. You can find it on the Samsung semiconductor home\npage under High Speed SRAM / NtRAM / K7N643645M.\n\n \n\n\n \n \n \n\n===== \n Supported RAM Types =====\n\n- asynchronous static SRAMs\n- synchronous static RAMs (\"Zero Bus Turnaround\" RAM, ZBT RAM)\n \n\n\n \n \n \n\n===== \n Status =====\n\n- new" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mgeng name: simu_mem status: Design done svn-updated: Oct 28, 2009 updated: Nov 18, 2008 wishbone-compliant: 0 - category: Arithmetic core created: Nov 5, 2010 description: "===== \n Description =====\n\nSine and cosine table that can be synthesized. Pure VHDL, no other tools or \nsilicon vendor macros. Pipeline delay can be selected from combinatorial \nto 10 stages at compile time via a generic. \n\nPhase input and sin/cos output widths are automatically determined by the \nconnected bus. 16 bit phase/18 bit amplitude runs at 230 MHz in Spartan6-3\nwithout any optimization efforts. (Just setting 250 MHz as the goal)\n\nAlso features a programmable pipeline register entity for most basic VHDL types.\nPipeline delay can be set from 0 to MAXINT clocks \n\nAlso a library for conversion between reals and integer/fractional signed and unsigned.\n\nThe test bed can log the generated sinewaves to a file for inspection with matlab." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - dk4xp name: sincos status: Design done svn-updated: Apr 8, 2011 updated: Feb 26, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Apr 23, 2004 description: "===== \n Before You Read =====\n\nThis is a brief overview of the article about single-clock unsigned integer division algorithm. For comparison and estimation of proposed algorithms please refer to the full article... (see PDF file from downloads).\n \n\n\n \n \n \n\n===== \n Overview =====\n\nNow two division algorithms are wide spread in computing: restoring and non-restoring algorithms. They consider that both algorithms may be used in sequential calculation scheme, when one digit of the result is achieved during one clock. However there are no principle objections against getting all digits of the quotient and the remainder during one clock. So the author tried to develop such kind of algorithm.\n \n\n\n \n \n \n\n===== \n Links =====\n\nThese cores are developed and provided by ASIC reseach department Leader of DeverSYS Corp., Vladimir V.Erokhin. More useful fundamental (and not only) FREE IP Cores can be found at DeverSYS web www.deversys.com.\n \n\n\n \n \n \n\n===== \n Methodology (brief) =====\n\nRestoring algorithm is seemed to be sequential in nature because during remainder restoring there is positive feedback (A=A \xE2\x80\x93 B + B at the same cycle). To avoid the feedback it is necessary to insert register for intermediate result storing. \nThus, non-restoring algorithm was chosen as basic for one-clock division algorithm.\n\n\n\nRecursive approach was chosen due to it provides compact and transparent description. It is easy to see that synthesis result of the description is sequence of adders." language: VHDL license: unknown maintainers: - vladvas name: single_clock_divider status: Stable svn-updated: Mar 10, 2009 updated: Sep 28, 2011 wishbone-compliant: 0 - category: Memory core created: Jan 7, 2003 description: "===== \n Description =====\n\nThe main purpose of this project was two-fold. The first purpose was to implement a client-server test architecture based on Bergeron's work in VHDL. The main advantage to this verification method is greater stress-test ability and removes the need to create test script language to test the DUT. \nThe second purpose was to bench-mark the running speed of the ASRAM implemented as three different architectures.\n1. Linked-list\n2. Bit-vector \n3. regular std_logic_vector implementation.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Demonstrates client-server testbench architecture in VHDL.\n- bit-vector array memory core\n- standard-logic array memory core\n- dynamic linked-list memory core.\n \n\n\n \n \n \n\n===== \n Status =====\n\nCompleted." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rpaley_yid - mgeng name: single_port status: Stable svn-updated: Mar 10, 2009 updated: Dec 27, 2010 wishbone-compliant: 0 - category: Other created: Mar 4, 2011 description: "===== \n description =====\n\nthis document is placed on arsdmthe license\nAssociation pour la Recherche Syst\xC3\xA9matique et le D\xC3\xA9veloppement de Mat\xC3\xA9riels et Techniques pour les Handicap\xC3\xA9s et l'Environnement\nfor a free use (that is where you or someone else don't win money with this use) this is as latest gpl you can find on : http://www.gnu.org/licenses/license-list.html\nwith addition of you have to respect notices\nfor else uses (commercial) you have to support arsdmthe with work on arsdmthe projects, products or money contact : arsdmthe@gmail.com\n\nthis project is about a way to make non-binary computing\ncells in place of one electron use photons (led, oled, nano crystal, ...)s\n(this way look the less expensive, there are else)\nto be smart : with ofet-amoled it will keep data even on power loss\nalso it can be highly secure : loading of color maps can take place before it really start !" language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - geobsd name: smart-non-binary-computing status: Empty updated: Apr 28, 2013 wishbone-compliant: 0 - category: Communication controller created: May 9, 2003 description: "===== \n Description =====\n\nThe System Management Bus (SMBus) is a two-wire interface through which simple system and power management related chips can communicate with the rest of a system. SMBus provides a control bus for system and power management related tasks. The SMBus is a multi-master bus, meaning that more than one device capable of controlling the bus can be connected to it. This core is based on the SMBus 2.0 specification, and utilizes its address resolution protocol using an 128-bit unique device identifier (UDID).\n \n\n\n \n \n \n\n===== \n Features =====\n\n- SMBUS 2.0 Compliant\n- 128-bit UDID\n- Hardware packet error checking (PEC)\n- Supports all SMBus ARP commands\n- SMBus slave address is assignable\n- Supports both SMBus Reset commands.\n- SMBus arbiter allowing host/slave communication\n- SMBus Clock synchronization/Clock Stretching\n- WISHBONE B.3 SOC bus compatible\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Writing of initial specification is underway" language: '' license: unknown maintainers: - erichawkins_200 name: smbus_if status: Empty svn-updated: Mar 10, 2009 updated: Jan 22, 2004 wishbone-compliant: 1 - category: Communication controller created: Mar 19, 2009 description: "===== \n Overview =====\n\nThe Serial Media Independent Interface, SMMI, is a low pin count version of the MII normally used between ethernet MAC and PHY.\n\n\n\nThe Serial Media Independent Interface (SMII) is designed to satisfy the following requirements:\n\nConvey complete MII information between a 10/100 PHY and MAC with two pins per port\nallow multi port MAC/PHY communications with one system clock\nOperate in both half and full duplex\nper packet switching between 10 Mbit and 100 Mbit data rates\nallow direct MAC to MAC communication\n\n\n\n\nSMII is composed of two signals per port, global synchronization signal, and a global 125 MHz reference clock.\n\n\n\n\n\n\nAll signals are synchronous to the clock.\n\n\n\n\n\n\nName\nFrom\nTo\nUse\n\n\nRX\nPHY\nMAC\nReceive data and control\n\n\nTX\nMAC\nPHY\nTransmit data and control\n\n\nSYNC\nMAC\nPHY\nSynchronization\n\n\nCLOCK\nSystem\nMAC & PHY\nSynchronization\n\n\n \n\n\n \n \n \n\n===== =====\n\n\n \n\n\n \n \n \n\n===== \n Typical application =====\n\nThe picture above shows a typical application with an external quad Ethernet PHY that connects to four Ethernet MACs inside a FPGA.\n\n\n\n\n\n\nThis example uses a total of 10 signal to implement this function.\n\n\n\n \n\n\n \n \n \n\n===== \n Resource usage =====\n\n\n\nTarget\nsmii_sync\nsmii_rxtx\n\n\nACTEL ProASIC3\n10 slices\n117 slices\n\n\nALTERA Cyclone III\nCombinatorial functions 2 DFFs 10\nCombinatorial functions 52DFFs 36\n\n \n \n\n\n \n \n \n\n===== \n Status =====\n\n\n2009 March 13 initial design commited to repository.Limited testing performed on OpenRISC hardware platform" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - unneback name: smii status: Beta svn-updated: Apr 28, 2009 updated: Mar 19, 2009 wishbone-compliant: 0 - category: Other created: Jul 20, 2014 description: "===== \n PLEASE NOTE =====\n\nThis work is managed via git: https://github.com/feddischson/soc_maker and synchronized to this SVN repository.\n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\nDUE TO A OPENCORES SVN SERVER BUG, THE SYNCHRONIZATION FAILS FOR REVISION 11 (AND EVERYTHING LATER).\nTHIS MEANS, THAT THE CURRENT SVN REPOSITORY IS NOT UP TO DATE.\n\nPLEASE USE https://github.com/feddischson/soc_maker UNTIL THIS ISSUE IS FIXED AND TRACK THE ISSUE HERE: http://opencores.org/forum,Other,0,5524\n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe System-on-Chip (SoC) Maker is a tool to design and create SoCs in a simple way, written in Ruby.\n\n\n PLEASE NOTE: THIS SOFTWARE IS IN DEVELOPMENT AND HIGHLY EXPERIMENTAL!! \n\n\n\n\n \n\n\n \n \n \n\n===== \n Target Platform =====\n\nThis application is developed and tested under Linux, but there are no OS dependencies. \nTherefore, it is intended and it should be possible to use it on a windows host, but this needs to be tested first.\n\n \n\n\n \n \n \n\n===== \n Current Features =====\n\n- All configuration files are YAML based see http://en.wikipedia.org/wiki/YAML)\n- Hierarchical systems can be designed\n- Usage of an IP core library\n- A CLI for an easy interaction \n- Ruby interface to interact with the soc_maker on a lower level\n- VHDL output\n- instance parameterization (vhdl-generics/verilog-parameters)\n- global/static parameterization (vhdl-packages/verilog-includes)\n \n\n\n \n \n \n\n===== \n Planed Features =====\n\n- Graphical User Interface (GUI) \n- Import wizzard: should scan IP core sources and suggest configuration\n- Verilog output\n- Plugin interface\n- Synthesis and Simulation support plugins\n- More cores\n \n\n\n \n \n \n\n===== \n TODOs =====\n\n- User-Guide (with YAML API documentation)\n- API version check\n \n\n\n \n \n \n\n===== \n Status =====\n\nA first \"Hellow World\" SOC has been created, simulated, synthesized and tested \non a Spartan-3AN starter kit board. \nThe system consists of an OpenRISC CPU, some on-chip memory and a UART core\n(see ./examples/or1200_test).\n\nFurthermore, some dummy cores have been assembled to a hierarchical system, \nwhere a SOC contains a few cores and a sub-SOC.\n\nThe following cores are integrated into the SOC-Maker core library and can be used:\n- the Advanced Debug System (http://opencores.org/project,adv_debug_sys )\n- the OR1200 OpenRISC processor (http://opencores.org/or1k/Main_Page )\n- the ram_wb from the openrisc project (http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb )\n- the UART16550 module (http://opencores.org/project,uart16550 )\n- a wishbone bus connection from the min-soc project (http://www.minsoc.com )\n \n\n\n \n \n \n\n===== \n Motivation =====\n\nThe motivation of this project is the need of an open-source application\nto create system-on-chips easily and fast on a higher level than vhdl or verilog.\nBy creating a generic application, it can support a wide range of \nprocessors, cores, controllers and bus-topologies. \nBy using the SoC-Maker, it should be easy for a system-designer to assemble \nmultiple IP-cores together with a low effort and without low-level knowledges.\nFurthermore, pre-defined SoCs can be published and extended. This makes it \ninteresting for IP-core developers. An existing SoC created with the\nSoc-Maker can be easily extended by a custom IP core which is then tested \nand used.\nNot only memory-mapped systems are a target application, also signal-processing\nsystems are interesting, where signal-processing blocks are concatenated.\n\nOne useful example is an Open-RISC based SoC, where it would be nice, if\ncore and system-developers can easily create a SoC with an\nOpen-RISC CPU. The need of a detailed knowledge of the Open-RISC, the Wishbone \nbus and so on is not needed anymore.\n\nA second example is a any kind of wireless receiver, where signals are filtered, mixed,\ndecimated and further processed. All the signal processing can be put \ntogether into a subsystem with \nparameters (mixer-resolution, decimation-rate and son on). On a higher level, this\nsub-system can then be used in a typical memory-mapped SoC together with other \nIP-cores and sub-systems.\n \n\n\n \n \n \n\n===== \n The Goal =====\n\nThe goal in one sentence: the SoC-Maker should make it possible to parameterize and assemble \none or multiple IP-cores into one IP-core on a high level.\n\n\nIP-core\nIP stands for Intellectual Property and the definition can be found on wikipedia: \nhttp://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core\n\n\nParameterization\nParameterization of IP-cores says, that the user can configure and setup all\nrequired parameters of an IP-core.\n\n\nAssembly\nAssembly in this context means, that the IP-cores are connected in a pre-defined\nor user-defined way, that the final IP-core works as required by the \nuser.\n\n\nOne or Multiple IP cores\nThe minimum number of IP-cores, which are used in such a system is one. Of course,\nthe common case is that more than one IP-core is used to create one final\nIP-core.\n\n\nInto one IP core\nThe assembly into one IP-core can be seen in different ways: on the one hand, \nthis final IP-core can be seen as a System-on-Chip. On the other-hand, it can \nbe defined as a subsystem with additional parameters. This parameters are then\npassed to the single IP-cores. The subsystem, which is one big IP-core, can then\nbe used in other systems or sub-systems.\n\n\nThe High Level\nThe high level says, that the user must not work on code or RTL level.\nFurthermore, the high-level can can be different: one way could be\na graphical user interface. A second way might be an easy to read ASCII file \nwritten for example in XML, YAML or JSON.\n \n\n\n \n \n \n\n===== \n Requirements =====\n\n- The user is able to organize IP cores and interfaces in a library, which includes \n * adding existing IP cores / interfaces\n * removing IP cores / interfaces\n * displaying IP cores (which are in the library)\n * adding IP cores to the target-SOC\n\n- There should be a library functionallity: the library should hold\n * core definitions\n * interface definitions\n\n\n- There should exist a core definition for each core. The definition should define the following data\n * all source files, which are required for synthesis only\n * all source files, which are required for simulation only\n * all source files, for synthesis and simulation\n * top-level source file\n * top-level port and parameters\n * parameter configuration and validation\n * an option to download/check out files from a repository (svn, git ...)\n\n\n- There should exist an interface specification for each interface used in the library\n * The interface specification defines, how the IP cores are connected\n * Allow versioning\n * Allow a wide range of topologies\n\n- There should be a SOC definition\n The SOC definition defines, which IP cores are used\n by the target-SOC, how they are connected and how the IP cores\n are parameterized.\n\n- IP-core configuration\n It must be possible to configure an IP core. The configurable parameters\n are defined in the IP-core definition and set in the SOC definition.\n The parameters are then used to instantiate the IP-core during the HDL generation\n\n- Toplevel-Generation\n The SoC maker should auto-generate a toplevel in VHDL or Verilog.\n Both HDL languages should be supported for generation.\n\n- Configuration Files\n All configuration should be stored in YAML files, this includes\n * SOC definition\n * Core definition\n * Interface specification\n * SoC maker configuration\n\n \n\n\n \n \n \n\n===== \n Author =====\n\nChristian Haettich,\nfeddischson [ at ] opencores.org\n \n\n\n \n \n \n\n===== \n License =====\n\nCopyright (C) 2014 Christian Haettich - feddischson [ at ] opencores.org\n\nThis program is free software: you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation, either version 3 of the License, or\n(at your option) any later version.\n\nThis program is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\nGNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License\nalong with this program. If not, see http://www.gnu.org/licenses/." language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - feddischson name: soc_maker status: Planning svn-updated: Aug 17, 2014 updated: Sep 11, 2014 wishbone-compliant: 0 - category: Testing / Verification created: Mar 23, 2014 description: "===== \n Description =====\n\nSocExplorer is an open source generic System On Chip testing software/framework. We write this software for the development and the validation of our instrument, the Low Frequency Receiver(LFR) for the Solar Orbiter mission. This instrument is based on an actel FPGA hosting a LEON3FT processor and some peripherals. To make it more collaborative, we use a plugin based system, the main executable is SocExplorer then all the functionality are provided by plugins. Like this everybody can provide his set of plugins to handle a new SOC or just a new peripheral. SocExplorer uses PythonQt to allow user to automate some tasks such as loading some plugins, configuring them and talking with his device. SocExplorer is provided under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.\n\nMore detail here\n\nYou can install RPM packages from here they have been tested on Fedora 20." language: C/C++ license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ajeandet name: socexplorer status: Empty updated: Jun 28, 2014 wishbone-compliant: 0 - category: Testing / Verification created: Mar 9, 2010 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jt_eaton name: socgen status: FPGA proven svn-updated: Apr 28, 2015 updated: Dec 30, 2012 wishbone-compliant: 1 - category: Communication controller created: Jul 13, 2010 description: "===== \n Description =====\n\nThis IP implements the 1-wire communication protocol (http://en.wikipedia.org/wiki/1-Wire).\nA more detailed documentation is provided in \"doc/sockit_owm.odt\".\n\nRTL features:\n- small RTL, should fit into a CPLD\n- Avalon MM bus, Wishbone compatible with a simple adapter\n- timed reset, presence, write/read bit transfers\n- overdrive\n- power supply (strong pull-up)\n\nSOPC Builder integration\n\nNios II EDS integration:\n- port of the 1-wire open domain kit version 3.10b\n- interrup driven or polling driver\n- uCOS-II support (only partialy tested)\n\n\nThe source code and documentation are available on github:\nhttps://github.com/jeras/sockit_owm" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - iztok name: sockit_owm status: FPGA proven svn-updated: Jun 26, 2011 updated: Feb 16, 2011 wishbone-compliant: 1 - category: System on Chip created: Apr 21, 2009 description: "===== \n System-on-Chip Wire (SoCWire) =====\n\nSoCWire has been developed by IDA, Technical University Braunschweig. It is a Network-on-Chip (NoC) approach based on the ESA SpaceWire interface standard to support dynamic reconfigurable System-on-Chip (SoC). SoCWire has been developed to provide a robust communication architecture for the harsh space environment and to support dynamic partial reconfiguration in future space applications.\n\nSoCWire provides:\n\xE2\x80\xA2\tReconfigurable point-to-point communication\n\xE2\x80\xA2\tHigh speed data rate\n\xE2\x80\xA2\tHot-plug ability to support dynamic reconfigurable modules\n\xE2\x80\xA2\tLink error detection and recovery in hardware\n\xE2\x80\xA2\tEasy implementation in dynamic partial reconfigurable systems. \n\xE2\x80\xA2\tScalable data word width (8-8192)\n\xE2\x80\xA2\tConfigurable Switch with 2 to 32 ports\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n SoCWire Network-on-Chip (NoC) =====\n\n\n \n\n\n \n \n \n\n===== \n Software License =====\n\nThe source files are free software; you can redistribute it and/or modify it under the restriction that UNDER NO CIRCUMTANCES this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE. This implies modification and/or derivative work of this Software.\n \n\n\n \n \n \n\n===== \n Documentation =====\n\nSoCWire User Manual (draft)" language: VHDL license: unknown maintainers: - bjoerno - holgerm name: socwire status: Design done svn-updated: Feb 1, 2012 updated: Jun 25, 2010 wishbone-compliant: 0 - category: Communication controller created: Aug 5, 2010 description: "===== \n Description =====\n\nSoftUSB is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\n\n\n\nSupports full (12Mbps) and low (1.5Mbps) speed operation\nTwo downstream ports with shared bandwidth\nIntegrated PHY\nDirectly interfaces to common USB transceivers such as the MIC2550A\nHybrid architecture featuring the Navr\xC3\xA9 AVR compatible processor (8-bit RISC) to implement the complex parts of OHCI in C software.\nTwo asynchronous clock domains: system clock and 48MHz USB\nAVR program and OHCI descriptors and data are stored in shared (system addressable) on-chip dual-port RAM\n\n\nSoftUSB is work in progress, for the latest information or to contribute to the development please see the Milkymist-devel mailing list and the #milkymist channel on the Freenode IRC network. In particular, testers are wanted for the Navr\xC3\xA9 softcore.\n \n\n\n \n \n \n\n===== \n More information =====\n\n\nCSR bus specifications" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: softusb status: Alpha svn-updated: Aug 24, 2010 updated: Apr 19, 2013 wishbone-compliant: 1 - category: System on Module created: May 7, 2012 description: "===== \n Description =====\n\nSystem-on-Module based on an ARM SoC in combination with an ALTERA FPGA. Focus for this module is connectivity, flexibility\nand a high performance/price ratio.\n \n\n\n \n \n \n\n===== \n Form factor =====\n\nThe form factor for this module is 200 pin SO-DIMM.\n \n\n\n \n \n \n\n===== \n Connectivity =====\n\nModule has a rich flavor of connectivity available.\n\nThe ARM SoC from Micrel contains a manageable 4+1 port 10/100 Mbps\nswitch. The switch has built-in Fast Ethernet PHY for this. Two port can optionally support 100FX.\nThe swicth can be used in scenarios with 1 WAN port and 4 LAN ports.\n\nConnected over the KSZ8095P PCI bus is a USB hub with 5 hi-speed USB2.0 compliant ports. Device contains\nPHY for these channels. \n\nFrom the FPGA four full duplex SERDES channels are available. These are fully configurable and can optionally\nsupport PCI express.\n \n\n\n \n \n \n\n===== \n Flexibilty =====\n\nA total of 48 IO signals are available on the edge connector. Out of these 22 signals have configurable IO levels.\n\nThe on board ALTERA FPGA can be used for a wide variety of functions including:\nperipherals (UARTs, I2C, SPI, I2S, AC'97, LPC ...)\ncoprocessor (connected over PCI sharing main memory with ARM CPU)\nDSP functions (FFT, IIR and FIR filter ...)\nCrypto (MD5, AES, 3DES ...)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback name: som_arm9_cycloneivgx status: Planning svn-updated: Jun 4, 2012 updated: May 29, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Nov 11, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - culurciello name: sos1 status: Empty updated: Nov 12, 2011 wishbone-compliant: 0 - category: Communication controller created: Apr 8, 2005 description: "===== \n Features =====\n\n- SpaceWire CODEC\n- testbench and stimuli to cover the exception conditions described in the standard\n- WISHBONE wrapper (optional)\n- Triple Modulo Redundant (optional)\n- Error Detection and Correction for TX and RX FIFOs (optional)\n- makefile for simulation and synthesis (vmake utility)\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nTentative release of the following documentation:\n\n- Architectural Requirement Specification (ARS)\n- Architectural Verification Plan (AVP)\n- Architectural Design Report (ADR)\n- Architectural Verification Report (AVR)\n\nIn accordance with ECCS-Q-60-02.\nTailoring may be added at network level, but character, exchange and packet level will remain as is defined in the ECSS-E-ST-50-12C.\n\nTentative first draft for ARS is on December 2011 (hopefully!)\n \n\n\n \n \n \n\n===== \n Description =====\n\nSpaceWire (SpW) grown organically from the needs of on-board processing applications. It's a network of spacecraft/aerocraft with Routers. \n\nInstead of customization in builting system on a project-by-project basis resulting in long development at high cost and risk, SpaceWire focused on the definition of an network architecture for payload data systems. Processing units, mass-memory units and down-link telemetry systems developed for one mission can be readily used on another mission, reducing the cost of development, improving reliability. \n (SpaceWire is currently being installed on several NASA and European Space Agency (ESA) spaceships to support onboard communications during space missions.\n---27 January, 2003)\n\nSpaceWire standard has taken into consideration two existing standards, IEEE 1355-1995 and ANSI/TIA/EIA-644.\n \nFor official publication, please visit \n\nhttp://spacewire.esa.int/\n\nor\n\nhttp://www.ecss.nl/ (registration required)\n\nto download ECSS-E-ST-50-12C \"SpaceWire - Links, nodes, routers and networks\" by ECSS (31 July 2008)\n\nFor IEEE1355, you could visit\nhttp://grouper.ieee.org/groups/1355/\n\"IEEE 1355-1995 Heterogeneous InterConnect (Low cost, low latency, scalable serial interconnect for parallel system construction).\"" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - btltz - abasili name: spacewire status: Planning svn-updated: Mar 10, 2009 updated: Oct 17, 2011 wishbone-compliant: 1 - category: Communication controller created: Jun 6, 2010 description: "===== \n Description =====\n\nSpaceWire Light is a SpaceWire encoder-decoder with FIFO interface.\nIt is synthesizable for FPGA targets (up to 200 Mbit on Spartan-3).\nAn optional AMBA bus interface can be used to implement the core in\nLEON3-based designs.\n\n \n\n\n \n \n \n\n===== \n Overview =====\n\nThe goal is to provide a complete, reliable, fast implementation\nof a SpaceWire encoder-decoder according to ECSS-E-50-12C.\nThe core is \"light\" in the sense that it does not provide additional\nfeatures such as RMAP, routing etc.\n\n\n\n\n\n\n\nSpaceWire Light supports two application interfaces. One interface\nprovides FIFO-style access to RX/TX buffers in the core (spwstream).\nThis interface can be easily integrated into most digital designs.\n\n\n\n\n\n\n\nAlternatively, an AMBA bus interface (spwamba) may be used to integrate\nSpaceWire Light into a LEON3 embedded system. This interface supports\nDMA-based data transfers. The code for the AMBA interface depends on GRLIB,\na VHDL library from Aeroflex Gaisler. The source of GRLIB must be downloaded\nseparately from http://www.gaisler.com/.\n\n\n\n\n\n\n\nSee the manual for detailed information:\nManual.pdf.\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis core is complete and fully functional.\nIt has been tested on Xilinx Spartan-3 and Virtex-5 FPGA boards, with a SpaceWire link connected to a commercial SpaceWire product.\n\n\n\n\n \n\n\n \n \n \n\n===== \n Applications =====\n\nSpaceWire Light is used for VIBANASS, an image-based navigation sensor system\ndeveloped by Kayser-Threde, co-funded by the German Aerospace Center." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - jorisvr name: spacewire_light status: Design done svn-updated: May 4, 2013 updated: Nov 1, 2013 wishbone-compliant: 0 - category: System on Chip created: Mar 30, 2010 description: "===== \n Status =====\n\nProject is alive of 17th May 2010. Please try, find bugs, report and develop. We have enormous amount of TODO (see the bugtracker) so each developer is welcome.\n \n\n\n \n \n \n\n===== \n Description =====\n\nOpenSPARC-based SoC is a project aimed to create a SoC based on OpenSPARC cores (T1 and T2) with OpenCores and other open-source peripherals added, and having Linux/OpenSolaris running on it.\n \n\n\n \n \n \n\n===== \n Achievements =====\n\nMain success now is a OS2WB module that bridges the T1 core and FPU to Whishbone bus. With the other obvious components (DRAM, flash, UART) it is able to boot Ubuntu Linux 2.6.22 normally and 2.6.30 core in rescue mode. \nThe integer register file (IRF) was redesigned for FPGA, so the four-thread T1 core was shrunk by 25% of logic and 15% of registers. Now it will be possible to build double core system on the Stratix-IV board with small changes in OS2WB.\nThere is also a whole project source for the Altera StratixIV kit, you will just need to generate standard memories, PLL and DDR3 controller. Documentation will be added soon, meanwhile do not hesitate to ask.\n \n\n\n \n \n \n\n===== \n Nearest aims =====\n\nAs a first step, we will build the single-core OpenSPARC T1-based SoC including:\n - full or reduced OpenSPARC T1 CPU core\n - OpenSPARC FPU\n - bridge to connect the CPU and FPU to the Whisbone bus\n - Nor flash controller\n - UART\n - OpenCores Ethernet controller\n - bridges from Whishbone to Altera and Xilinx DRAM controllers\n\nNow operating system is Linux 2.6.22 (Ubuntu), we have compiled the 2.6.30 core to support the Ethernet, it is able to boot in rescue mode already. We have cross-toolchain and working on the x86 machines.\n\nDevelopers wanted - contact maintainers." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - dmitryr - fafa1971 name: sparc64soc status: Alpha svn-updated: Oct 8, 2010 updated: Oct 13, 2011 wishbone-compliant: 0 - category: Processor created: Jun 14, 2012 description: "===== \n Description =====\n\nThe SPARC V8 instruction set has a well-defined opcode space and model for coprocessor instructions; this includes 25 bits of instruction space for data-processing instructions, as well as predefined instructions for loads/stores to/from coprocessor registers, and branch-on-coprocessor condition codes. The goal of this project is to make a synthesizable SPARC V8 compatible core with a well-documented internal interface to a coprocessor. The intention is to facilitate a close coupling of custom logic to the CPU core, while minimizing the redesign necessary in the CPU.\n\nFirst FPGA implementation will likely be on a Xilinx Zynq 7020, unless something with a more compelling $/gate ratio than the Zedboard comes out soon. As such, initial implementations of the processor are likely to use the AXI bus as the system interface, as this is the interface to most of the hardwired components in the Zynq (memory controller, on-chip-SRAM, etc). Once the core itself is ironed out, a Wishbone compatible variant will be made.\n\nUPDATE: \nThe high-level specifications are due to be completed mid-September. Work on the HDL will commence shortly thereafter, but expect progress to be slow." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - nvo name: sparcv8coprocessor status: Empty updated: Aug 30, 2012 wishbone-compliant: 0 - category: Prototype board created: Mar 17, 2013 description: "===== \n Overview =====\n\nThis article describe the PCI express card with Xilinx Spartan 6 that i have made.\nThe download section contains test applications in Xilinx ISE for the PCI express and DDR3 functions (All worked at first).\nI am still not an expert so what would be more interesting (Processor core, intensive applications like running Linux ) is still a on wish list . PCB's are available as well as source project in Altium Designer.\n \n\n\n \n \n \n\n===== \n Images =====\n\njavascript:alert('');\njavascript:alert('');\njavascript:alert('');\njavascript:alert('');\njavascript:alert('');\njavascript:alert('');\n \n\n\n \n \n \n\n===== \n Part list =====\n\n*All resistor and capacitor are 0603 if size not specified\n*All resistor are either 0402 or 0603 size\n*All capacitor are either 0402 or 0603 or 1206\n*All components may be found on Mouser(1st choice) or Digikey , except FPGA and DDR3 Digikey only.\n*DNF : means Do not fit (for example NCP303-LSN29 is not required for correct operation)\n\nIC1\tFPGA Xilinx XC6SLX45T-4FGG484C\nIC2\tVCCINT regulator ST1S31 (ST1S31PUR)\nIC3\tVDD15 regulator ST1S31 (ST1S31PUR)\nIC4\tRAM terminator VDD075 regulator LP2996 (LP2996MRX/NOPB)\nIC5\tVCC33 DC jack regulator LD1085 (LD1085D2T33R)\nIC6\tW25Q128 128Mbit Winbond flash memory (W25Q128FVEIG)\nIC7\tIDT ICS844071 SATA PLL (844071AGLF)\nIC8\t1Gbit Micron DDR3 DRAM MT41J64M16 (MT41J64M16JT-15E:G TR)\nIC9\tEverlight Photolink module PLR135_T7\nIC10\tEverlight Photolink module PLT135_T7\nIC11\tNCP303-LSN29 DNF\n\nQ1 \tSATA 25Mhz Abracon ASEM or ASEMB 3.2x2.5x0.85\nQ2\tUser 50Mhz Abracon ASEM or ASEMB 3.2x2.5x0.85\n\nP1\tPCIE card edge connector\nH1,H2\tdouble row 40pin 2.0mm header connector\nJ1\tDC jack 3.5mm (Maybe found on Ebay..)\nH3\t14pin right angle 2.54mm JTAG connector\nD1-D3\tled 0603\nD0\tled 0603\nSD1,SD2\t500873-0806 Molex Transflash push-push\nSATA1,SATA2\t5607-4200-SH 3M SATA Connector SMT RA\n\nL1\tInductor 2.2uH 4A Murata 2020 (LQH5BPN2R2NT0L)\nL2\tInductor 3.3uH 1.1A 0806 Taiyo Yudan(CKP20163R3M-T)\n\nR1\tVCCINT_GND 15K\nR2\tVCCINT_PLUS 7.5K\nR3\tVDD15_GND 18K\nR4\tVDD15_PLUS 15.8K\nR5,R6\t100R output of sata crystal\nR7\tDO NOT FIT (can be 100R/0402 parallele resistor on pcie clock pair, but not nescessary)\nR8\t330R DONE to VCC33\nR9\t4K7 PROGRAM_B to VCC33\nR10\t10K CMPCS_B to VCC33\nR11\t4K7 INIT_B to VCC33\nR12-R14\t680R led resistor 0402\nR15\t240R 1% 0402 DRAM ZQ\nR16\t50R GTP RCAL 0402\nR17-R18 4K7 0402 DDR CKE and Reset to GND\nR19\t10K SPI SS to VCC33 0402\nR20\tSwap enable 0R 0603\nR21,R22 SD2 unused pins 22K 0402\nR23\t680R power led 0402\nR24,R25 SD1 unused pins 22K 0402\nR26,R27 pullup flash HOLD,WP 0402 10K\nR28\tIO_DDR_TERM calibration resistor 100R 0402\nR29\tDDR_CS tied to Gnd 0R 0402\n\nC1\tCapacitor1206 VCC33 to VCCINT switch input 100uF\nC2\tCapacitor1206 VCC33 to VDD15 switch input 100uF\nC3,C3b\tCapacitor1206 VCCINT switch 100uF\nC4\tCapacitor1206 VDD15 switch 100uF\nC5,C6\tLP2996 100uF VDD075 output decoupl.\nC7\tLP2996 VREF decoupl. 10nF\nC8\tLP2996 VDD15 ref input decoupl. 10nF\nC9\t47uF 0805 VCC33 to LP2996 power input\nC10,C11\t50uF 1206 input to LD1085 regulator\nC12,C13 100uF 1206 output of LD1085\nC14 \t100nF output of SATA crystal\nC15,C16\tSATA REFCLK diff pair Capacitor0402 100nF\nC17-C20 SATA1 RX/TX capacitor 0402 10nF\nC21-C24\tSATA2 RX/TX capacitor 0402 10nF\nC25-C28 PCIE RX/TX capacitor 0402 100nF\nC29\t1nF NCP303\n\nC30-C31 decoupling TOS RX/TX 100nF\nC32 decoupling flash memory 100nF\nC33 decoupling Q2 user 50Mhz oscillator(0402 size)\nC34 decoupling Q1 sata 25Mhz oscillator(0402 size)\nC35 decoupling SATA PLL ICS844071 (0603 size)\n\nC40-C42 100nF VDD075 decoupling RAM\nC45-C46 100nF VDD075 decoupling FPGA\nC50-C56\t1uF GTP decoupling\nC60-C65 1uF VDD15 decoupling FPGA\nC70-C74\t1uF VCCINT decoupling\nC80-C93 1uF VCCAUX/VCCO/VCC33 FPGA decoupling\nC100-C109 1uF VDD15 decoupling RAM\n\nC120 decoupling SD2 100nF 0402\nC121 decoupling SD1 100nF 0402\n\n \n\n\n \n \n \n\n===== \n Article =====\n\nI have designed and built a PCI express extension card with Spartan 6 FPGA.\nI was very attracted in testing Microprocessor cores in FPGA and also PC extension cards.\nSo i needed a board with RAM, non volatile memory (SDHC memory cards) and FPGA.\n\nWhen i saw the selling price of this kind of cards, i decided to build mine. Also it was a good exercise to conduct the fabrication of this card from schematic and PCB up to assembling.\n\nMany features where new to me:\n-High speed differential pair\n-Length matching and resistor terminations for DDR3\n-big FPGA chips (DDR3 and FPGA)\n\nSo i have read carefully the design recommendation from the Manufacturers (Xilinx for FPGA and Micron for the DDR3). I got documented also on the Freescale IMX35 processor reference design . All recommended to carefully control PCB impedance , differential pair length matching, DDR3 signals length matching and termination resistors on high speed signals.\n\nI had a new tool for PCB design (Altium designer) that made the task a lot easy or at least possible .\n\nAnyway some problems came arise concerning the price of fine PCB manufacture:\n\nFirst i designed a 8 layer PCB that accomplished impedance parameter of 50ohm on single ended signals and of course 100ohm on differential pairs. Moreover , the DDR signals where well separated each other with 2.5 x trace width that is recommended by Xilinx. But the PCB parameters where expensive to manufacture (traces of 0.1mm / vias of 0.4mm / 8 layers ) was 500USD cost for 10pcs.\n\nI decided then to reduce cost , with only 4 layer (DDR traces where now shielded with only the top and bottom layer which are ground and power planes but with some discontinuity). Moreover i enlarged minimum trace width to become 0.15mm and via size to become 0.5mm.\nWith these parameters , impedance rule of 50R/100R is not really respected, also clearance between DDR signals is no 2.5 x trace width but only 2x trace width. Anyway , differential pair length matching is still stricly observed , also DDR length matching is also stricly observed with a total length of 26mm +- 0.2mm for all signals .\nWith these PCB parameters , the manufacture cost dropped to 120USD including a gold finish for all the contacts.\n\nFinally , i received the PCB samples (they where of admirable perfect qualtity, i think the manufacturer have far better manufacture tolerance that it say) , assembled a board in 1 day and tested\n1- The FPGA configuration and flash memory : Works perfectly in 1x and 2x SPI bus but no 4x bus , i currently don't konw why.\n2- PCI express . Works perfectly . The Xilinx core generator automatically produce a sample core application that is a PCI express device of type 'RAM controller\".\n3- DDR3 : Works . Tests at 300Mhz clock (The core uses internally 2x this frequency using a PLL to double it).\n\nNow many other things should be tested :\n-SATA host and device connectors\n-SDHC memory cards\n-DDR3 and PCIE with a real intensive application . Like for example Linux why not!\n\nThe card is at my knowledge one of the first design not from a commercial company, and i propose the PCB for anyone interested. And also the Altium designer project source (PCB and schematic) in download section.\n\nin case the PCB would be re - made , it would be a good idea to add a termination resistor on DRAM CLK differential pair. Yes it is not currently done, but it works! It could be still possible to solder it on the vias under the RAM chip.\n\n\n\n \n\n\n \n \n \n\n===== \n DDR3 extensive test with Microblaze FPGA processor =====\n\nI have learned what's required to setup microblaze on this board (processor running on Xilinx FPGA).\nMany documentation can be found from Xilinx but also from AVNET .\nA EDK licence is also required (Webpack free licence does not currently cover the full use of Xilinx SDK and Platform studio). By chance , they is a 30 day free evaluation licence for these products).\n\n\nSetting up Microblaze is fairly fast and straightforward, nearly all project generation is automated with option wizards where you specify what's is on the target board. The result is a SDK project with commands like \"Download microblaze to FPGA\" and \"Run or Debug application project\". All of that is done with the JTAG cable connected.\n\n\nI have specifically ran the DDR3 test application included with EDK basic application which extensively test the Memory by writing all the 128Mbyte memory locations then read and compare with expected value previously written. This test is performed with many flavor (Write constant value 0xFFFFFFFF,Write constant value 0x00000000,Write constant value 0xAAAA5555,Write incremented serie 1,2,3,..,0x0200000,Write inverse address as value,Write a rotated serie of 00..1..00 or 11..0..11.\n\nHere is the a portion of the C application and the result shows that DDR3 on this card is working correctly .\nEach run of writing and reading the 128Mbyte take approx 30s. The microblaze processor is clocked at 100Mhz.\n\nint main()\n{\n int i;\n\n init_platform();\n\n print(\"--Starting Memory Test Application--\\n\\r\");\n print(\"NOTE: This application runs with D-Cache disabled.\");\n print(\"As a result, cacheline requests will not be generated\\n\\r\");\n\n for (i = 0; i test_memory_range(&memory_ranges[i]);\n }\n\n print(\"--Memory Test Application Complete--\\n\\r\");\n\n cleanup_platform();\n\n return 2;\n}\n\n\n--Starting Memory Test Application--\nNOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated\nTesting memory region: mcb_ddr3\n Memory Controller: axi_s6_ddrx\n Base Address: 0xc0000000\n Size: 0x08000000 bytes \n memtest words: 0x02000000 words \n 0xFFFFFFFF test: PASSED!\n 0x00000000 test: PASSED!\n incr test: PASSED!\n inverse addr test: PASSED!\n 0xAAAA5555 test: PASSED!\n walk ones: PASSED!\n walk zeros: PASSED!\n--Memory Test Application Complete-\n\n\n \n\n\n \n \n \n\n===== \n Running Linux on the board =====\n\nI have compiled a Petalinux kernel for this board.\nSee download section for instruction of how to do that.\n\nThe compilation results include a image.elf that is a Linux with and embedded RAM filesystem.\nIt is possible to setup various configurations based on Linux.\n\nIt is planned an expansion board with Ethernet, USB host , Serial and maybe VGA output.\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Credit =====\n\nPCB manufacturer for this card can be contacted at maisuid@gmail.com . dont hesitate to submit him your project for quote.\n \n\n\n \n \n \n\n===== \n Project update =====\n\n07-2014 . 3 new boards where built\n\n\n\n\n\nAll worked properly without problem. \nThe feature tested where :\n-FPGA, JTAG and Power supply\n-Flash memory\n-IO connectors, board leds and oscillator\n-PCI express\n-DDR3 (when installed)\n\n\n\n\n\nExample Linux / Windows drivers for PCIe where added to the download . An XPS design without Microblaze processor (only PCIe to peripherals bus) was added. Example PCIe drivers for Windows and Linux are proposed in Xilinx xapp1052. A \"no driver\" approach is possible with Jungo windriver under Windows and with open/mmap (on PCIe BAR resource) under Linux." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - chipmaker78 name: spartan6_pcie status: Beta svn-updated: Jul 28, 2014 updated: Aug 2, 2014 wishbone-compliant: 0 - category: Communication controller created: Apr 12, 2004 description: "===== \n Description =====\n\nThe SPDIF interface (Standard IEC958 \"Digital audio interface\") allows transmission of digital audio signals between devices in a digital format. The goal of this project is to allow a controller/cpu with Wishbone interface to transmit and receive digital audio.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Separate transmitter and receiver\n- Dual sample buffer architecture with configurable buffer size\n- Access to channel status and subframe bits\n- Supports both 16bit and 32bit data bus\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- SPDIF Interface V1.1 has been released." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gedra name: spdif_interface status: FPGA proven svn-updated: Mar 10, 2009 updated: Oct 14, 2007 wishbone-compliant: 1 - category: Processor created: Apr 11, 2014 description: "===== \n Description =====\n\nSpec 16 is a simple 5 stage pipelined 16-bit processor. In alpha testing." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: spec16_processor status: Empty updated: Dec 17, 2014 wishbone-compliant: 0 - category: Communication controller created: Jun 12, 2002 description: "===== \n Description =====\n\nSPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others.\nThis core is SPI/Microwire compliant master serial communication controller with additional functionality.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Full duplex synchronous serial data transfer\n- Variable length of transfer word up to 32 bits\n- MSB or LSB first data transfer\n- Rx and Tx on both rising or falling edge of serial clock independently\n- 8 slave select lines\n- Fully static synchronous design with one clock domain\n- Technology independent Verilog \n- Fully synthesizable\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested in FPGA" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - simons name: spi status: FPGA proven svn-updated: Mar 10, 2009 updated: Jun 29, 2013 wishbone-compliant: 1 - category: Arithmetic core created: Nov 2, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ulises_fpga name: spi_atmega168 status: Empty updated: Nov 2, 2012 wishbone-compliant: 0 - category: Communication controller created: Feb 8, 2005 description: "===== \n Description =====\n\nThe SD/MMC Bootloader is a CPLD design that manages configuration and bootstrapping of FPGAs. It is able to retrieve the required data from SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA configuration process. SD cards as well as MMCs are operated in SPI mode which is part of both standards thus eliminating the need for dedicated implementations. The SD/MMC Bootloader fits both. Beyond configuration, this core supports a bootstrapping strategy where multiple images are stored on one single memory card.\n\n\n\n\n\nFor example consider a system completely based on SRAM. The bootloader provides the initial configuration data from the first image to the FPGA. This image contains a design which pulls the next image from the memory card and transfers this data to SRAM. In the third step the final FPGA design is loaded from the third image.\n\n\n\n\n\nThese images are clustered in sets which can be selected by external switches for example. Several configuration sets can be stored on one memory card allowing you to provide a number of applications which are downloaded quickly to the FPGA.\n\n\n\n\n\nThe schematic rev. C shows how the core can be used with an FPGA board. I use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300 board. SV2 fits the \"SERIAL MODE\" connector on this board but you will have to add a separate wire from R6 to attach INIT. Please check the proper use of the pull-up resistors for your specific board.\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n\nConfiguration mode: configures SRAM based FPGAs via slave serial mode (Xilinx and Altera)\nData mode: provides stored data over a simple synchronous serial interface\nBroad compatability using SPI mode\nSecureDigital cards using dedicated initialization command\nMultiMediaCards (see below)\nOperation triggerd by power-up or card insertion\nMultiple configuration sets stored on single memory card\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe SD/MMC Bootloader has been successfully implemented in an Altera MAX3064 device. Configuration target in a three stage process was a Xilinx Spartan-IIE XC2S300E. The CPLD design requires 50 out of 64 macro cells.\n\n\n\nDesign Documentation is finished.\nSchematic rev. C is available.\n\n\n \n\n\n \n \n \n\n===== \n Tools =====\n\nThe following tools are integrated and are required for this project:\n\n\n\nThe GHDL simulator\n\n\n\n\nDownloading the configuration data to the card is a straight forward process. The images have to be written starting at dedicated locations. For the provided toplevel designs, these locations are multiples of 256 K. I.e. 0, 0x40000, 0x80000 and so forth.\n\n\n\n\n\ndd (part of the GNU coreutils) serves this purpose:\n\n\n $ dd if=ram_loader.bin of=/dev/sdX bs=512\n $ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512\n $ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024\n\n\n\n\nThe name of the device node depends on how the card reader is attached to the kernel. For Linux systems this is most often something like /dev/sdX with X ranging from a-z. Please note that it is essential to use the device without any trailing numbers as they refer to partitions leading to wrong offsets for data written to the card.\n\n\n\n\n\nAll this works perfectly for my Spartan IIe device as this FPGA expects the configuration data as it is delivered from the card: Consecutive bytes each with its most significant bit first. Altera devices like the FLEX family are different here. They expect the bytes with least significant bit first. Therefore, the configuration data has to be swapped bitwise before it is written to the card.\n\n\n\n \n\n\n \n \n \n\n===== \n Download =====\n\nThe latest release of the SD/MMC Bootloader project is version 3.2, rev. C.\n\n\n\n\nGet this and all previous versions of the design files from SVN: Download repository.\n\n\n\n\nPlease keep in mind that trunk/ is work in progress and might contain smaller or bigger problems.\n\n\n\n\nYou should also check the Tracker for known bugs and see if they affect your work.\n\n\n\n \n\n\n \n \n \n\n===== \n References =====\n\n\nSanDisk SD Card Product Manual\nSanDisk MMC Product Manual\nToshiba SD Card Specification\n\n\n \n\n\n \n \n \n\n===== \n Compatability =====\n\nThese cards have been tested with the SD/MMC Bootloader:\n\n\n\nHama 64 MB SD\nSanDisk 128 MB SD\nSanDisk 64 MB MMC\nPanasonic 32 MB SD\n\n\n\n\nSome MMC might fail with this core as not all cards support CMD18 (READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific model. In case your MMC does not implement CMD18 you might want to have a look at the FPGA MMC-Card Config project." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - arniml name: spi_boot status: FPGA proven svn-updated: Apr 1, 2009 updated: Aug 19, 2009 wishbone-compliant: 0 - category: Communication controller created: Dec 8, 2009 description: "===== \n Description =====\n\nModified SPI Master Core by Simon Srot. This core is designed for use with the Spatan 3E, 3A, and 3AN starter kits, for interfacing with the onboard Linear Technology Analog to Digital and Digital to Analog convertors." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - williamgibb name: spi_core_dsp_s3ean_kits status: Alpha svn-updated: Dec 13, 2009 updated: Dec 13, 2009 wishbone-compliant: 0 - category: Other created: Nov 11, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - paliativo name: spi_hub status: Empty updated: Nov 11, 2011 wishbone-compliant: 0 - category: Communication controller created: May 16, 2011 description: "===== \n Development Status =====\n\n\nPlease if you are using this core, report if the marked bugs (CPHA='1', bit alignment) are solved for your toolchain. \nYou can send me e-mail to jdoin@opencores.org\nI have confirmation from people using Xilinx ISE 13.1, 12.4 and 12.1 with WebPack, Altium + ISE 12.3, Synopsys and Altera tools. \nI would like to know if the VHDL style used in this core works for your toolchain, and if not, what seems to be the problem. \nMy goal is to find a description style that is as friendly as possible to synthesis tools. \n\n\n\nThe scope screens below show a CPOL=1, CPHA=1 spi transaction. Debug signals show the slave internal state and slave flow control signals for the read/write ports. The spi_master and spi_slave cores are verified in FPGA hardware at 100MHz (50MHz spi clock) with 0 ns of SCK-to-MOSI delay and less than 2ns of SCK-to-MISO delay.\n\nIn the example, the slave is used with wren_i permanently tied to HIGH. The parallel input data is sampled from di_i at start of transmission, until the first SPI SCK edge. For continuous transfers, the data at di_i is sampled again every falling edge on state 1.\n\n\xC2\xA0\xC2\xA0\n\xC2\xA0\xC2\xA0\n\xC2\xA0\xC2\xA0\n\n\nThe scope screens below show 2 examples of continuous transfers: for CPOL=1, CPHA=0 and CPOL=0, CPHA=0 spi modes. The words are loaded when 'di_req' line goes to '1'. Data is presented to the port di_i and wren_i is pulsed to write the data word.\xC2\xA0\n\n\nIn the screen on the right, the 1st 'di_req' data request (requesting data for the second word) is ignored by the slave parallel interface driver, and MISO is cleared (others => '0') for that word. The 3rd word is loaded normally ('wren' is strobed in time for the transfer).\n\n\xC2\xA0\xC2\xA0\n\xC2\xA0\xC2\xA0\n \n\n \n\n\n \n \n \n\n===== \n Related Links =====\n\nThe following OpenCores projects are related to this:\n- Multiple Switch Debouncer in VHDL: http://opencores.org/project,debouncer_vhdl , used in the FPGA verification project.\n\n\nTo get the latest version: http://opencores.org/download,spi_master_slave\nTo see the scope screenshots: http://opencores.org/project,spi_master_slave,downloads\nSee all scope photos in the 'trunk/syn' folder at the SVN: http://opencores.org/websvn,filedetails?repname=spi_master_slave&path=%2Fspi_master_slave%2Ftrunk%2Fsyn%2Fspi_master_scope_photos.zip\n\n\n\nIf you have issues you like to be addressed, place a request in the bugtracker: http://opencores.org/project,spi_master_slave,bugtracker , or send me an e-mail at jdoin@opencores.org\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis project started from the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing.\nThe resulting cores generate small and efficient circuits, that operate from very slow SPI clocks up to over 50MHz SPI clocks.\n\nThe project contains 2 independent cores: SPI_MASTER and SPI_SLAVE.\nBoth cores are written in VHDL, with fully pipelined RTL architecture and separate clock domains for the SPI bus clock and parallel I/O interface.\n\nThe design is originally targeted to a Spartan-6 device, but is written in fully synthesizable, technology-independent VHDL.\nThe circuits preserve FPGA clock resources by directly using the system high speed clock for all flops, with clock enables (CE) to clock registers.\nThe master and slave cores were verified in hardware using the Digilent Atlys board (Spartan-6 @100MHz) with spi clocks from 500kHz to 50MHz SPI clock, with perfect phasing and very robust operation.\n\nIf you find these cores useful, please let me know: jdoin@opencores.org\n\nIf you find the LGPL license to be unfit for your purposes, please let me know and we can change the license for another open-source hardware license that can be integrated in your application.\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- VHDL core, fully synchronous, designed with classic RTL pipelined architecture, with a single high-speed global clock\n- Very small and efficient SPI interface\n- Parameterizable at instantiation by generics: (N, CPOL, CPHA, PREFETCH, SPI_2X_CLK_DIV)\n-> SPI modes (CPOL, CPHA): supports modes 0,1,2,3\n-> Word width (N): from 8 bits to synthesis limit (accepts any word length)\n-> Lookahead input data request (PREFETCH): pipelined data request for back-to-back data transmission\n-> SPI 2x clock divider value from the high-speed system clock\n- Very economic: no FIFO, just a registered parallel output buffer for received data\n- Parallel read/write similar to synchronous RAM ports\n- Independent clock domains for the serial bus and parallel read/write ports with async domain transfer pipelines\n- Can be used to control generic SPI devices (master), or as interface to MCUs (slave)\n- Vendor-independent, fully LUT/FF design, uses no Xilinx-specific structures, IOBs or shift registers\n- Synthesizes to +210MHz in a Spartan-6 lowest grade, using only CLB logic\n- Verified in silicon, with a 100MHz clock, using SPI frequencies from 500kHz up to 50MHz in a Spartan-6 XC6SLX45-2\n- Very small: 41 slices for 2 ports (a master interface + a slave interface) with 32bits of word length" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jdoin name: spi_master_slave status: FPGA proven svn-updated: Sep 19, 2011 updated: Jul 25, 2014 wishbone-compliant: 0 - category: Communication controller created: Nov 19, 2007 description: "===== \n Description =====\n\nThe OPB SPI Core connects a FPGA to a DSP or Microprocessor as Slave-Device. This means all transfers are initiated by the Master an the FPGA-System only responds to read or write request.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- OPB-Clock and SPI-Clock are complete independent\n- SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX- FIFO Overrunn occure.\n- variable transfer length 2..32\n- Automatic CRC-Generation for Transmit and Receive Data (only 8,32Bit Shift-Register Width)\n \n\n\n \n \n \n\n===== \n Status =====\n\n- simulation tests done\n- Hardware tests on a Virtex-4 ML401 Board (LX25) done \n- CRC-Code Real World Test in progress" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dkoethe name: spi_slave status: FPGA proven svn-updated: Mar 12, 2009 updated: May 15, 2008 wishbone-compliant: 0 - category: Communication controller created: Mar 12, 2014 description: "===== \n Description =====\n\nThis Project provides SPI Mode-3 Master & Slave modules in Verilog HDL.\nThe data width is 8 bits. It is synthesized for Xilinx Spartan 3E, & can be clocked upto 225MHz. Maximum SPI Clock (sck) Frequency is 112MHz, which is derived from Main Clock. The scaling factors for SCK from master clock can be 2, 4, 8 & 16, which can also be reduced further.\n\nSPI Master Module is coded in FSM (finite state machine)\nThe slave module is designed simply like a shift register.\n\nThe interface signals are SCLK (or SCK), MOSI, MISO and SS. SCK is the SPI Clock which is generated by the master device. MOSI is the data output of master which is the data input of slave device. MISO is slave data output which is data input of master. SS is the Slave Select active low signal which enables the slave device in the bus to be active.\n\nTO DOWNLOAD CODE: http://opencores.org/websvn,listing,spi_verilog_master_slave" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - santhg name: spi_verilog_master_slave status: Empty svn-updated: Mar 31, 2014 updated: Mar 6, 2015 wishbone-compliant: 0 - category: Communication controller created: Jun 14, 2009 description: "===== =====\n\nthis core represents an minimalistic SPI receiver for ADC like AD747x.\none have:\n - tunable sequence len, loaded data slice of sequence, \n - shut-down short sequense generation\n - ability continued sequence mode - without frame entry/completing\n - ready output for locking received data\n - shifht clock output provide ability to build parallel vector receivers by\n adding needed shift registers\nSyntesis on QuartusII 8.1 Web for EP1C3 16bit sequense with 10 loaded bit ocupies 31 cells" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - AlexRayne name: spiadc status: Stable svn-updated: Jun 15, 2009 updated: Jun 23, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Dec 14, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - kommuk name: spicontroller status: Empty updated: Dec 24, 2010 wishbone-compliant: 0 - category: Communication controller created: Nov 1, 2013 description: "===== \n Description =====\n\nThis project provides a full function SPI master interface. It provides for a FIFO buffered transmit and receive data path. Further, a ninth bit in the transmit data controls whether the SPI input data (MISO)is saved into the receive FIFO. This allows this SPI interface module to easily support serial memory devices, whose outputs during command and address loads are undefined, and devices like serial ADCs, whose output data is valid on each transfer cycle. In addition, the module automatically asserts and deasserts the slave select line. Slave select is asserted when data is written to the output FIFO/register, and slave select is deasserted when there's no more data in the transmit FIFO.\n\nA built-in clock generator supports clock rates of 1/2 of the system clock down to 1/256 of the system clock. The shift direct is programmable. This SPI master module also supports all four SPI operating modes. A change-of-state detector is included to automatically change the control signals (mode, clock rate, and shift direction) between transfer cycles.\n\nA limitation of the module is that one system clock cycle is required to change the mode, shift direction, and baud rate selections. Once a transfer cycle begins, the master can change these values but their effect will not take place until one cycle after the de-assertion of slave select, i.e. the end of the current SPI transfer cycle.\n\nThis module has been used in a Xilinx XC3S50A-4VQ100I FPGA which implemented a system-on-chip using this module, the P16C5x processor core, and several other modules found here at opencores.org: M16C5x, SSP_Slv, SSP_UART, and DPSFmnCE.\n \n\n\n \n \n \n\n===== \n Synthesis/PAR =====\n\nThe following tables define the synthesis and PAR results for the SPIxIF SPI Master Interface module. It is not intended to be used as a stand-alone implementation, but as a peripheral function for soft processor or system-on-chip solutions.\n\n\n\n ModulePartition\n Slices\n Slice Reg\n LUTs\n LUTRAM\n BRAM\n MULT18X18\n BUFG\n DCM\n\n\n\n [-] SPIxIF\n \n 68/68\n 40/40\n 103/103\n 0/0\n 0/0\n 0/0\n 1/1\n 0/0\n\n\n\n\nThe timing constraints used to achieve the best results with the -4 speed grade of the XC3S50A FPGA are shown in the following table:\n\n\nTiming Constraints\n\n\n Met\n Constraint\n Check\n Worst Case Slack\n Best Case Achievable\n Timing Errors\n Timing Score\n\n\n\n Yes\n TS_Clk = PERIOD TIMEGRP \"Clk\" 5.200 ns HIGH 50%\n SETUP/HOLD\n 0.020ns/1.231ns\n 5.180ns\n 0/0\n 0/0\n\n\n\n\n\n\nWith the lower speed grade part of the XC3S50A-4VQ100I, the SPIxIF can support operation at just under 200 MHz. Thus, when integrated with other components to form a soft processor or system-on-chip, the module provided in this project will not be a driving factor in the overall speed rating of the encapsulating project.\n\n\n\n\n\n\n\n Synthesis/PAR Results - XC3S50A-4VQ100I FPGA\n \n Attribute\n Used\n Avail\n %\n \n \n Number of Slice Flip Flops\n 50\n 1408\n 2%\n \n \n Number of 4 input LUTs\n 103\n 1408\n 7%\n \n \n \n \n \n Number of occupied Slices\n 68\n 704\n 9%\n \n \n Number of Slices related logic\n 68\n 68\n 100%\n \n \n Number of Slices unrelated logic\n 0\n 68\n 0%\n \n \n \n \n \n Total Number of 4 input LUTs\n 103\n 1408\n 7%\n \n \n Number used as logic\n 103\n \n \n \n \n Number used as a route-thru\n 0\n \n \n \n \n Number used as Shift registers\n 0\n \n \n \n \n \n \n \n Number of bonded IOBs\n \n \n \n \n \n Number of bonded pads\n 32\n 68\n 47%\n \n \n IOB Flip Flops\n 32\n \n \n \n \n \n \n Number of BUFGMUXs\n 1\n 24\n 4%\n \n \n Number of DCMs\n 0\n 2\n 0%\n \n \n Number of RAMB16BWEs\n 0\n 3\n 0%\n \n\n\n\n \n\nBest Case Achievable: 5.180ns (0.020ns Setup, 1.231ns Hold)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelA name: spicxif status: FPGA proven svn-updated: Nov 1, 2013 updated: Nov 2, 2013 wishbone-compliant: 0 - category: Communication controller created: Aug 5, 2010 description: "===== \n Description =====\n\nAn implementation of serial Linear Technologies LTC2624 Quad 12bit DAC using SPI 32bit data transfer method. The core is FPGA proven, works on Spartan-3E Starter Kit.\n\nIf someone would like to improve the project (i.e. add WishBone support, etc), please contact project maintainers." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - socrates - armandas name: spidac status: FPGA proven svn-updated: Aug 6, 2010 updated: Aug 6, 2010 wishbone-compliant: 0 - category: Communication controller created: Nov 21, 2006 description: "===== \n Description =====\n\nThis project implements a controller for standard SPI flash ROMs (e.g. ST M25Pxx, Atmel AT25Fxxxx, etc.).\nFor a design using an (embedded) microcontroller it is often a requirement to store user or configuration information. For this purpose the configuration ROM of the FPGA is a first-choice candidate because it is already there and usually has some space left. By using the VHDL module introduced in this project the microcontroller firmware is greatly simplyfied by moving the complexity of accessing the SPI flash to the hardware.\nThis core is a spin-off from the \"DIY Calculator Hardware\" project (URL: http://diycalculator.pcl.at)\nand is maintained by Johannes Hausensteiner (johannes.hausensteiner@pcl.at)\n \n\n\n \n \n \n\n===== \n Features =====\n\nThe communication to the SPI flash is done through commands which are of different length, with or without parameters, expecting or not responses. The following commands are implemented:\n- WREN: Write Enable; before you can write to the flash it is necessary to send this command\n- WRDI: Write Disable; does what it says\n- RDSR: Read Status Register; the flash chip employs a status register which tells about the chip's state such as write protect, busy, etc.\n- WRSR: Write Status Register; write a new value to the status register\n- READ: read data; reads an arbitrary number of bytes beginning from a supplied address\n- FAST_READ: similar to the READ command, but possibly uses a faster clock\n- PP: Page Program; the flash chip is organised in sectors and pages; an arbitrary number of bytes but a maximum of one page size can be written to the flash\n- SE: Sector Erase; before data can be programmed into the flash it must be erased. It is only possible to erase sectors as a whole.\n- BE: Bulk Erase; erase the whole chip\n- RES: Read Signature; each flash chip contains a signature, which is characteristic for the type of chip\n\nThe SPI Flash Controller acts as a microprocessor peripheral. Communication is done via several registers:\n- Tx data register (write, base plus 0)\n- Rx data register (read, base plus 0)\n- command register (write, base plus 1)\n- status register (read, base plus 1)\n- address mid register (write, base plus 2)\n- address low register (write, base plus 3)\n\nNote that the address is composed from three bytes. In this implementation the highest byte (= the sector number) is fixed to the topmost sector. Remember that FPGA configuration is stored at the beginning of the flash (starting with address $000000).\n\nFor detailed information see the state diagram (SPI_state-diagram.jpg) and the register description (spi-registers.txt) in the doc sub directory of the project in CVS.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 0.1 25.Sep.2006 JH new, flash sector number is hard coded to 0x0f\n- 0.1 21.Nov.2006 JH no changes, submitted to OpenCores.org" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - johanneshau name: spiflashcontroller status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 17, 2014 wishbone-compliant: 0 - category: Communication controller created: Dec 21, 2009 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - siva12 name: spigpio status: Alpha svn-updated: Dec 22, 2009 updated: Dec 21, 2009 wishbone-compliant: 0 - category: Communication controller created: Apr 11, 2008 description: "===== \n Description =====\n\nSD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple Fifo interface. Provides transfer speeds up to 24Mbps.\nIf combined with the fpgaConfig project: http://opencores.org/project,fpgaconfig\nthen it is possible to configure an FPGA from SD memory. If the FPGA configuration includes this core (spiMaster) and a softcore processor, then the processor can copy a software image from SD memory into RAM, and then execute from RAM. Thus a complete FPGA softcore processor can be implemented with just an FPGA, DRAM, and SD card.\nSee fpgaConfig used in a complete project at:\nhttp://opencores.org/project,openriscdevboard\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Simple interface to SD cards up to 2GB\n- SD Initialization\n- SD 512 byte block write\n- SD 512 byte block read\n- Data access up to 24Mbps\n- 8-bit Wishbone slave interface\n- Separate Wishbone and core logic clocks\n- Simulation files\n- 900 logic cells in Altera Cyclone2\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nTested in FPGA.\nThe following mods and additions could be useful:\n- Interrupt line.\n- Card detect.\n- Master wishbone interface would be nice, so that DMA transfers to memory could be performed.\n- SD/MMC memory card simulation model needs improvement. The model does not parse the commands from the core, and does not provide any storage.\n- Multiple SPI chip select support.\n- Larger Fifos to allow simultaneous processor and core Fifo access.\n \n\n\n \n \n \n\n===== \n News =====\n\nRelease 1.2 now available. New version modifies read timing which was marginal for some SD cards." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - sfielding name: spimaster status: FPGA proven svn-updated: Mar 10, 2009 updated: Nov 24, 2014 wishbone-compliant: 1 - category: Communication controller created: Dec 7, 2009 description: "===== \n Description =====\n\nspislave is a minimalist spislave IP core that provides the basic framework for the implementation of custom spislave devices. The core provides a means to write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. A full Icarus Verilog test bench is available. Test it for yourself, using the free Icarus Verilog simulator and the free GTKWave wave form viewer.Download and install Icarus Verilog. - Download and install GTKWave. - Download the project files. - For executing the testbench just run the Makefile on the bench folder.In GTKWave, use \"Search >> Signal Search Tree\" to view more waves.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Standalone. No microprocessor required. For master side we need an microntroller\n- Create your own custom spislave peripheral.\n- Easily configurable for different input clock frequencies.\n- Full Icarus Verilog test bench.\n- This is to be tested with Our Zkit-51( 8 bit microcon board),a lcd(16x2) and Xilinx Spartan 3A FPGA board\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested in Zkit - 51 (8 bit microcontroller board) with Xilinx Spartan 3A FPGA board. \n- Tested in simulation.\n- Tested waveform in GTK wave." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - siva12 name: spislave status: Stable svn-updated: Dec 19, 2009 updated: Mar 3, 2010 wishbone-compliant: 0 - category: Communication controller created: Feb 17, 2015 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jeaander name: sport status: Planning svn-updated: Mar 11, 2015 updated: Feb 17, 2015 wishbone-compliant: 0 - category: Other created: May 9, 2013 description: "===== \n Description =====\n\nThis module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - gryzor - maruiz name: sqmusic status: Design done svn-updated: Jul 3, 2013 updated: May 15, 2013 wishbone-compliant: 0 - category: Library created: Dec 22, 2009 description: "===== \n Description =====\n\nThe srdy-drdy library provides a group of components all built around a common data-transfer protocol. This protocol is used in datapath applications and provides bidirectional flow control.\n\nComponents in the library provide basic timing closure, clock domain crossing, basic and advanced buffering, and some arbitration and specialized components. The components in the library have been used in multiple successful tape-outs and FPGA designs." language: Verilog license: unknown maintainers: - ghutchis name: srdydrdy_lib status: ASIC and FPGA proven svn-updated: May 11, 2012 updated: Apr 20, 2013 wishbone-compliant: 0 - category: Communication controller created: Sep 8, 2010 description: "===== \n Description =====\n\nINTRODUCTION\n---------------\nThe Serial RapidIO Endpoint solution comprises a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) and Transport Layer interface. This IP solution is a netlist for RapidIO interconnect that supports x1, x4 and x8 lane widths. It comes with a configurable buffer design, reference clock module, reset module, and register manager reference design, which allows complete flexibility in selecting primitives. This solution is fully verified and supports both Verilog and VHDL design environments.\n\nFeatures\n---------\n\xE2\x80\xA2 Designed to RapidIO Interconnect Specification v2.2\n\xE2\x80\xA2 Supports x1, x4 and x8 operation with the ability to train down to x1 from x8.\n\xE2\x80\xA2 Supports speeds of 1.25, 2.5, 3.125, 5.0 and 10.0 Gbaud.\n\nLogical Layer\n-------------\n\xE2\x80\xA2 Supports a peak, unidirectional bandwidth of 32 Gbps when operating at 250 MHz.\n\xE2\x80\xA2 Concurrent Initiator and Target operations.\n\xE2\x80\xA2 Doorbell and Message support.\n\xE2\x80\xA2 128-bit internal data path.\n\xE2\x80\xA2 Dedicated port for maintenance transactions.\n\xE2\x80\xA2 Simple handshaking mechanism to control data flow.\n\xE2\x80\xA2 Programmable source ID on all outgoing packets.\n\xE2\x80\xA2 Optional large system support for 16-bit Device IDs.\n\nBuffer\n------\n\xE2\x80\xA2 Independently configurable TX and RX Buffer depths of 8, 16, 32 or 64 packets.\n\xE2\x80\xA2 Support for independent clocks.\n\xE2\x80\xA2 Optional TX Flow Control support.\n\nPhysical Layer\n--------------\n\xE2\x80\xA2 Supports critical request flow.\n\xE2\x80\xA2 Optional support of priority-based, retransmit suppression.\n\xE2\x80\xA2 Support for multicast events.\n\xE2\x80\xA2 Supports removal of corrupted packets for error detection and initiates automatic error recovery.\n\xE2\x80\xA2 Design verified using the RapidIO Trade Association Bus Functional Model.\n\xE2\x80\xA2 For sub-features, use only as necessary." language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - kailassenan name: srio status: Empty updated: Nov 10, 2012 wishbone-compliant: 0 - category: Memory core created: Jan 2, 2008 description: "===== \n Status =====\n\n- Simulated and ( 16 and 32 ) programmed into a Spartan 3 FPGA\n- Synthesised with ISE 10.1 \n\n- looking at a generic srl fifo now ise can handle such\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nSynchronous FIFO's based upon the SRL feature found in Xilinx FPGA's.\n\nBuilt to be small. \n\nIn a Spartan 3, the 8 bit wide , 16 bit deep FIFO utilises\n19 Luts\nof which 8 are used as SRL, 11 as Logic.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nPure VHDL, no instantiated components, all inferred\nsmall size" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - amulcock name: srl_fifo status: Stable svn-updated: Mar 10, 2009 updated: Feb 28, 2011 wishbone-compliant: 0 - category: Communication controller created: Sep 17, 2002 description: "===== \n Description =====\n\nSimple PCM Interface. Allows to interface to such popular devices\nlike TI DSPs (via McBSP bus) in PCM mode. Of course many more\napplications. Very small and simple core.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Implemented in Verilog\n- Frame Start position adjustable\n- full 16 bit frames\n- 1 Receive holding register\n- 1 Transmit holding Register\n- Fully Synthesisable\n- Can handle PCM streams at any rate, 128KHz to 100MHz.\n- 38 LUTs in a Spartan II\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis core is fully functional and completed. It was tested on\na XESS XCV800 board interfacing to a proprietary device with\na TI DSP, exchanging PCM streams in both directions.\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: ss_pcm status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 10, 2004 wishbone-compliant: 0 - category: Processor created: Jan 2, 2014 description: "===== \n Description =====\n\nSummary\nSSBCC.9x8 is a free Small Stack-Based Computer Compiler with a 9-bit opcode, 8-bit data core. It creates vendor-independent, high-speed, low fabric utilization micro controllers for FPGAs. It has been used in Spartan-3A, Spartan-6, Virtex-6, and Artix-7 FPGAs and has been built for Altera, Lattice, and other Xilinx devices. It is faster and usually smaller than vendor provided processors.\nThe compiler takes an architecture file that describes the micro controller memory spaces, inputs and outputs, and peripherals and which specifies the HDL language and source assembly. It generates a single HDL module implementing the entire micro controller. No user-written HDL is required to instantiate I/Os, program memory, etc.\nSSBCC has been used for the following projects:\n\noperate a media translator from a parallel camera interface to an OMAP GPMC interface, detect and report bus errors and hardware errors, and act as an SPI slave to the OMAP\noperate two UART interfaces and multiple PWM controlled 2-lead bi-color LEDs\noperate and monitor the Artix-7 fabric in a Zynq system using AXI4-Lite master and slave buses, I2C buses for timing-critical voltage measurements\n\nStatus\nThe computer compiler, the assembler, and several peripherals have been been working since early 2012.\nThe only external tool required is Python\xC2\xA02.7.\nDownloads\nSnapshots of the project can be downloaded from opencores. The code is maintained at https://github.com/sinclairrf/SSBCC.\nQuestions can be e-mailed to ssbcc at sinclairrf dot com" language: Verilog license: custom licensetext: "Redistribution and use in source and binary forms are permitted provided that\nthe above copyright notice and this paragraph are duplicated in all such forms\nand that any documentation, advertising materials, and other materials related\nto such distribution and use acknowledge that the software was developed by\nSinclair R.F., Inc. The name of Sinclair R.F., Inc. may not be used to endorse\nor promote products derived from this software without specific prior written\npermission. The software may not be used in any way that harms Sinclair R.F.,\nInc.\n\nTHIS SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,\nINCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND\nFITNESS FOR A PARTICULAR PURPOSE.\n" maintainers: - sinclairrf name: ssbcc status: FPGA proven svn-updated: Mar 9, 2015 updated: Feb 5, 2014 wishbone-compliant: 0 - category: Communication controller created: Nov 1, 2013 description: "===== \n Description =====\n\nThis project provides a slave interface for a Synchronous Serial Peripheral (SSP) as found on NXP LPC21xx microprocessors. The implementation provided here supports a 16-bit frame size. Of the 16 bits defined in the serial interface, the first three bits function as a register address, the fourth bit is a read/write control bit, and the remaining 12 bits function as read/write data.\n\nThis format is used in several commercial products to interface a LPC2138/LPC2148, or other processor equipped with an SSP or SPI master interface, to an FPGA. It enables the expansion of the LPC2138/LPC2148 with custom interfaces hosted in a variety of FPGAs. Within the FPGA, a parallel is formed using the register address, read/write control signal, and the data signals.\n\nThe master transmits a synchronous serial frame to this SSP_Slv module (MSB first). It returns the first four bits to the master, and creates a read/write pulse to the slave logic during the last rising edge of the 16-bit frame. It also samples the addressed register on the fourth clock of the frame. It generates a read pulse to the internal logic after capturing the data from the addressed register. This read pulse can be used to advance FIFOs, etc.\n\nThe interface logic is driven from the SSP/SPI SCK, and the slave select signal resets the interface state machine. Asserting slave select releases the reset signal of the module, and de-asserting slave select asserts the module's reset signal. Because the SSP_Slv is clocked by SCK, clock domain crossing logic and synchronizing registers are used where necessary to simplify connecting to peripherals operating on another clock domain.\n \n\n\n \n \n \n\n===== \n Updates =====\n\nFound an issue with the use of MSB (bit 15, RA[2]) during the first SSP transfer cycle. The register's previous asynchronous reset signal, SSP_Rst, was extended by a bit period and therefore prevented the register from being loaded from MOSI on the rising edge of SCK. Changed the register's reset signal to Rst_SSP, the module's reset signal, which is deasserted on the assertion of SSEL. This corrects change the issue.\n \n\n\n \n \n \n\n===== \n Synthesis/PAR Results =====\n\nThe following tables define the synthesis and PAR results for the SSP slave module. It is not intended to be used as a stand-alone implementation, but as an interface for serial peripherals in an FPGA.\n\n\n\n ModulePartition\n Slices\n Slice Reg\n LUTs\n LUTRAM\n BRAM\n MULT18X18\n BUFG\n DCM\n\n\n\n [-] SSP_Slv\n \n 52/52\n 54/54\n 31/31\n 0/0\n 0/0\n 0/0\n 1/1\n 0/0\n\n\n\n\nThe timing constraints used to achieve the best results with the -4 speed grade of the XC3S50A FPGA are shown in the following table:\n\n\nTiming Constraints\n\n\n Met\n Constraint\n Check\n Worst Case Slack\n Best Case Achievable\n Timing Errors\n Timing Score\n\n\n\n Yes\n Autotimespec constraint for clock net SCK_BUFGP\n SETUP/HOLD\n N/A ns/1.035ns\n 4.413ns\n 0/0\n 0/0\n\n\n\n\n\n\nWith the lower speed grade part of the XC3S50A-4VQ100I, the SSP_Slv can support operation at over 200 MHz. Thus, when integrated with other components to form a soft processor or system-on-chip, the module provided in this project will not be a driving factor in the overall speed rating of the encapsulating project.\n\n\n\n\n\n\n\n Synthesis/PAR Results - XC3S50A-4VQ100I FPGA\n \n Attribute\n Used\n Avail\n %\n \n \n Number of Slice Flip Flops\n 54\n 1408\n 3%\n \n \n Number of 4 input LUTs\n 31\n 1408\n 2%\n \n \n \n \n \n Number of occupied Slices\n 52\n 704\n 7%\n \n \n Number of Slices related logic\n 52\n 52\n 100%\n \n \n Number of Slices unrelated logic\n 0\n 52\n 0%\n \n \n \n \n \n Total Number of 4 input LUTs\n 31\n 1408\n 2%\n \n \n Number used as logic\n 31\n \n \n \n \n Number used as a route-thru\n 0\n \n \n \n \n Number used as Shift registers\n 0\n \n \n \n \n \n \n \n Number of bonded IOBs\n \n \n \n \n \n Number of bonded pads\n 39\n 68\n 57%\n \n \n IOB Flip Flops\n N/A\n \n \n \n \n \n \n Number of BUFGMUXs\n 1\n 24\n 4%\n \n \n Number of DCMs\n 0\n 2\n 0%\n \n \n Number of RAMB16BWEs\n 0\n 3\n 0%\n \n\n\n\n \n\nBest Case Achievable: 4.413ns (N/A ns Setup, 1.035ns Hold)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelA name: ssp_slv status: FPGA proven svn-updated: Apr 26, 2014 updated: Apr 26, 2014 wishbone-compliant: 0 - category: Communication controller created: Nov 1, 2013 description: "===== \n Description =====\n\nThis project provides a full-function UART. The UART provides direct support for a two-wire or a four-wire RS-232 style full-duplex serial interface, but it also provides direct support for a half-duplex RS-485 serial interface. In the RS-232 mode, automatic flow control can be enabled, and the UART will assert RTS when data is available to transmit and wait for CTS to be returned before the transmitter is enabled. In the RS-485 mode, the drive enable of the RS-485 driver is asserted and deasserted automatically.\n\nIn both operating modes, the UART supports the use of receive timeouts, RTO. In the RS-485 mode, the RTO function will also inhibit the transmitter until the timeout is asserted. This feature allows easy use of the UART with industrial automation protocols such as Modbus RTU and Profibus that specify minimum inter-packet gaps. The RTO unit of the UART provides a means by which the inter-packet gap can be programmed in multiples of the serial frame size. In other words, the UART RTO unit is programmed in character times to delay, and the programmed frame size is used in the implementation of the delay. For example, if a the serial format is set as 8E1, i.e. Profibus, then the serial frame is 11 bits in length: start, 8 data, 1 parity, and 1 stop. An inter-packet delay of 3 character times is set for the RTO count, so the total delay from the trailing edge of the last received character's stop bit to the leading edge of the start bit of the next transmit character is 33 bit times. This UART automatically sets the frame size to 11 and then uses a counter to generate count down pulses to a second counter which is set for 3. The result is an accurate 33 bit time delay.\n\nThe UART also allows independently set FIFO depths for the transmit and receive FIFOs. Interrupts based on various FIFO depth thresholds can also be set so that the interrupt rate can be controlled by the application. Interrupts can be enabled for various conditions: Receive Timeout, Receive FIFO Half Full, Transmit FIFO Half Empty, and Transmit FIFO Empty. The values used for generating FIFO half full interrupts are actually programmable. External user-supplied logic is required to map the interrupt requests onto the interrupt service bus of the application in which the UART is being used; the UART interrupt status registers are available over the communications interface, but are also outputs of the module.\n\nFull documentation of the UART is available in the descriptions provided in SSP_UART module header and those of the functional sub-modules which are used to construct it. A detailed specification and user's guide is included in the Docs section of the SVN repository. Finally, rudimentary testbenches for the SSP_UART and critical sub-modules are also included.\n \n\n\n \n \n \n\n===== \n Updates =====\n\nUpdated comments and removed dead code.\n \n\n\n \n \n \n\n===== \n Synthesis/PAR Results =====\n\nThe SSP_UART is used in a number of commercial projects. (A demonstration of its use in a system-on-chip project is contained in the M16C5x project elsewhere on opencores.org.) As indicated above, it is a full function UART with capabilities similar to those of a 16C550 UART, but extended with independently configurable FIFO depths for transmit and receive, an interface specifically designed so that it can function as Synchronous Serial Peripheral to an NXP LPC 21xx ARM microcontroller, and additional test and monitoring capabilities.\n\nThe synthesis/PAR results for the UART provided in this section provide only typical results with regards to size and speed. These characteristics of the SSP_UART are very much dependent on the synthesis and PAR settings of the application/system-on-chip in which the module is being instantiated. For the particular values shown below, the FIFO depths are set to 64 bytes for both the transmit and receive signal paths. Furthermore, the FIFOs are implemented using the DPSFmcCE module, also found here on opencores.org, which uses distributed RAM in a dual-port configuration. If there are sufficient block RAM resources, and LUTs are in short supply, the DPSFmnCE FIFOs can be replaced with block RAM FIFOs. The BRSFmnCE project here on opencores.org is an example of a compatible FIFO implementation that uses block RAMs rather than distrubuted LUT RAM for the FIFO memory.\n\nModule Level UtilizationModule Level UtilizationSat Nov 2 11:56:38 2013ModulePartitionSlicesSlice RegLUTsLUTRAMBRAMMULT18X18BUFGDCM[-] SSP_UART/217/47781/255195/5430/1360/00/02/20/0\xC2\xA0\xC2\xA0BRG16/1617/1724/240/00/00/00/00/0\xC2\xA0\xC2\xA0[-] INT6/244/235/110/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0FE14/44/41/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0FE22/23/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RE13/33/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RE23/33/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RE33/33/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0RE43/33/31/10/00/00/00/00/0\xC2\xA0\xC2\xA0RCV43/4334/3459/590/00/00/00/00/0\xC2\xA0\xC2\xA0RED14/44/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0RED24/44/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0RED35/54/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0RED44/44/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0RED54/44/42/20/00/00/00/00/0\xC2\xA0\xC2\xA0RF155/5520/2093/9372/720/00/00/00/0\xC2\xA0\xC2\xA0TF149/4920/2085/8564/640/00/00/00/0\xC2\xA0\xC2\xA0TMR21/2117/1727/270/00/00/00/00/0\xC2\xA0\xC2\xA0XMT31/3123/2339/390/00/00/00/00/0\n\nTiming Constraints\n\n\n Met\n Constraint\n CheckWorst Case Slack\n Best Case Achievable\n Timing Errors\n Timing Score\n\n\n Yes\n Autotimespec constraint for clock net Clk_BUFGP\n SETUP/HOLD\n N/A / 0.726ns\n 5.547ns\n N/A / 0\n 0/0\n\n\n Yes\n Autotimespec constraint for clock net SSP_SCK_BUFGP\n SETUP/HOLD\n N/A / 1.244ns\n 5.415ns\n N/A / 0\n 0/0\n\n\n\nXilinx Design Summary\n\n\n\nM16C5x Project Status (11/02/2013 - 10:20:16)\n\nProject File:\nM16C5x.ise\nCurrent State:\nPlaced and Routed\n\n\nModule Name:\nSSP_UART\nErrors:\n\xC2\xA0\n\n\nTarget Device:\nxc3s50a-4vq100\nWarnings:\n\xC2\xA0\n\n\nProduct Version:\nISE 10.1.03 - Foundation\nRouting Results:\n\nAll Signals Completely Routed\n\n\nDesign Goal:\nBalanced\nTiming Constraints:\n\nAll Constraints Met\n\n\nDesign Strategy:\nXilinx Default (unlocked)\nFinal Timing Score:\n0\xC2\xA0\n\n\n\n\n\n\xC2\xA0\nM16C5x Partition Summary [-]\nNo partition information was found.\n\n\n\n\n\xC2\xA0\nDevice Utilization Summary [-]\n\nLogic UtilizationUsedAvailableUtilizationNote(s)\n\nNumber of Slice Flip Flops\n255\n1,408\n18%\n\xC2\xA0\n\nNumber of 4 input LUTs\n542\n1,408\n38%\n\xC2\xA0\n\n\nLogic Distribution \xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\n\nNumber of occupied Slices\n352\n704\n50%\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number of Slices containing only related logic\n352\n352\n100%\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number of Slices containing unrelated logic\n0\n352\n0%\n\xC2\xA0\n\nTotal Number of 4 input LUTs\n543\n1,408\n38%\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used as logic\n406\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used as a route-thru\n1\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\n\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0Number used for Dual Port RAMs\n136\n\xC2\xA0\n\xC2\xA0\n\xC2\xA0\n\nNumber of bonded IOBs\nNumber of bonded \n44\n68\n64%\n\xC2\xA0\n\nNumber of BUFGMUXs\n2\n24\n8%\n\xC2\xA0\n\n\n\n\n\n\xC2\xA0\nPerformance Summary [-]\n\nFinal Timing Score:\n0\nPinout Data:\nPinout Report\n\n\nRouting Results:\n\nAll Signals Completely Routed\nClock Data:\nClock Report\n\n\nTiming Constraints:\n\nAll Constraints Met\n\xC2\xA0\n\xC2\xA0\n\n\n\n\n\xC2\xA0\nDetailed Reports [-]\nReport NameStatusGenerated\nErrorsWarningsInfos\nSynthesis ReportCurrentSat Nov 2 10:18:44 2013059 Warnings (5 new, 56 filtered)7 Infos (2 new, 0 filtered)\nTranslation ReportCurrentSat Nov 2 10:18:51 2013000\nMap ReportCurrentSat Nov 2 10:19:08 2013069 Warnings (0 new, 0 filtered)5 Infos (0 new, 0 filtered)\nPlace and Route ReportCurrentSat Nov 2 10:19:29 2013\xC2\xA0\xC2\xA0\xC2\xA0\nStatic Timing Report\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\nBitgen Report\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\xC2\xA0\n\n\n\nDate Generated: 11/02/2013 - 10:20:16" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - MichaelA name: ssp_uart status: FPGA proven svn-updated: Apr 26, 2014 updated: Apr 26, 2014 wishbone-compliant: 0 - category: Memory core created: Sep 25, 2001 description: "===== \n Description =====\n\nThe 'SSRAM interface core' is a collection of designs for easy integration of synchronous srams (ZBT srams) in your designs.\n \n\n\n \n \n \n\n===== \n Core description =====\n\nCurrently 2 designs have been implemented. ssram_conn and cs_ssram.\nThe entity ssram_conn provides a standard interface to the ssram. It provides the pipeline correction and all IO structures needed for high speed bidirectional data transfers (including full FPGA IO-cell usage).\nThe entity cs_ssram uses the standard interface to turn the ssram into a cycle shared memory. Because ZBTs feature zero bus latency there is no impact on throughput. Thus providing a low-cost alternative to dual-ported rams.\n\nThe design uses attributes to preserve all tri-state enables. Standard compiler strategy is to optimize redundant logic resulting in a single output/tristate enable signal. For maximum performance all output enables have to be preserved. Xilinx and Altera devices (and others probably too) can use their high speed paths to the IO-blocks only if every IO-block has its own output-enable. For ASIC implementations it results in the lowest Tco and Tsu possible.\nThe attributes used are for Leonardo Spectrum. Please tell me what attributes should be used for other compilers (like synplicity). \n \n\n\n \n \n \n\n===== \n Implementations =====\n\n- Standard interface for pipelined ZBTs \n- Dual ported memory using cycle shared ssram\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Designs are available in VHDL from OpenCores CVS via cvsweb or via cvsget \n- ToDo: \n - Modify the standard interface so it supports pipelined and flow-through ZBTs \n - Modify the standard interface for multi-compiler attributes. \n - Modify the cycle shared implementation so it can handle more than 2 sources (tri-ported, quad-ported etc. memories) \n \n \n\n\n \n \n \n\n===== \n Synthesis =====\n\nUsing the slowest Altera APEX20KE device 66MHz is possible." language: VHDL license: unknown maintainers: - rherveille name: ssram status: Beta svn-updated: Mar 10, 2009 updated: Oct 14, 2001 wishbone-compliant: 0 - category: Other created: Sep 8, 2010 description: "===== \n Description =====\n\nA simple module to get the most of your on board heartbeat LED. Change or add more sequences easily in parameters file." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mitko name: statled status: FPGA proven svn-updated: Sep 9, 2010 updated: Sep 14, 2010 wishbone-compliant: 0 - category: Communication controller created: Apr 23, 2004 description: "===== \n Description =====\n\nA very simple project for controlling any standard 4 or 6 wire stepper motor. Only difference between 4 and 6 wire mode is the MOSFET driver circuit (6 wire steppers are considerably simpler...)\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Simple VHDL for beginners; well documented\n- NPL project file for immediate evaluation in Xilinx ISE/Webpack tools\n- Quickly get a stepper motor running for testing or prototyping\n- Questions/Comments: http://www.franks-development.com\n\n \n\n\n \n \n \n\n===== \n Project Contents =====\n\n- StepperMotor.npl, project file for Xilinx ISE/Webpack\n- StepperMotorDrive.vhd, source code\n- StepperMotorDrive.ucf, constraints file for pin assignments, etc.\n- StepperMotorWiring.bmp, schematic for connecting motors. Given MOSFETS with sufficiently low Vgs-on, can be driven directly from logic." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - franksdevel name: steppermotordrive status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 17, 2005 wishbone-compliant: 0 - category: Processor created: Mar 16, 2011 description: '' language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - zero_gravity name: storm_core status: FPGA proven svn-updated: May 29, 2013 updated: Mar 8, 2014 wishbone-compliant: 1 - category: System on Chip created: Feb 17, 2012 description: "===== \n Description =====\n\nWelcome to the STORM SoC project!\n\nThis is an FPGA/evaluation board-independent, complete system on chip implementation based on the STORM CORE processor.\nMost of the SoC's components were designed by myself, but the are also some IPs used, which are available here at oppencores.\nAll components are connected via an 32-bit, pipelined Wishbone bus fabric.\n\nThe boot ROM features a pre-installed bootloader, which allows easy program downloading to RAM or to an attached I\xC2\xB2C EEPROM.\nIt is also capable of booting program files directly from the EEPROM.\nCompatible programs files can be generated by using the provided WinARM-compatible makefiles.\nIncluded IO driver libraries allow fast and easy program setup.\nA tutorial shows how to extend the hardware platform with own IP cores.\nSTORM SoC Datasheet and Implementation Guide\n\nThe SVN of the STORM SoC does not contain the sources of the core itself.\nThey need to be downloaded separately at the STORM Core Processor project page.\n\n\nSTORM SoC features (basic configuration):\n\nFPGA independent microcontoller-like system on chip based on the STORM CORE Processor\nOpcode and function compatible to ARM's 32-bit instruction set processor series (ARMv2)\n1kb D- and 1kb I-cache (full associative)\n32-bit pipelined Wishbone bus system\nClock manager (PLL) and reset generator\nWinARM compatible makefiles\nPre-defined IO driver libraries (C files)\nInternal 32kb SRAM\nInternal 8kb boot ROM with pre-installed bootloader\nSupports booting from UART, RAM and attached I\xC2\xB2C EEPROM\n32-bit system timer\nVector-interrupt-controller (LPC native)\nGeneral purspose IO pins (8xIN, 8xOUT)\nI\xC2\xB2C and SPI controller\nSimple mini UART\n8 PWM outputs\nEasy-to-extend hardware platform\nDemo program included\nTutorial for system setup and modification\n...\n\nImplementation results of STORM SoC basic configuration:\n\nTarget board: Altera/Terasic DE0nano board\nTarget FPGA: Altera Cyclone IV E EP4CE22F17C6\nTotal logic elements: 11,518 / 22,320 ( 52 % )\nTotal comb. functions: 11,158 / 22,320 ( 50 % )\nDedicated logic registers: 5,298 / 22,320 ( 24 % )\nEmbedded Multiplier 9-bit elements: 6 / 132 ( 5 % )\nTotal pins: 60 / 154 ( 39 % )\nTotal memory bits: 344,064 / 608,256 ( 57 % )\nTotla PLLs: 1 / 4 ( 25 % )\nMaximum clock speed (slow 1200mV 0C model): 67.48 MHz\n\n\nTarget board: Altera/Terasic DE2 board\nTarget FPGA: Altera Cyclone II EP2C35F672C6\nTotal logic elements: 11,469 / 33,216 ( 35 % )\nTotal comb. functions: 11,096 / 33,216 ( 33 % )\nDedicated logic registers: 5,254 / 33,216 ( 16 % )\nEmbedded Multiplier 9-bit elements: 6 / 70 ( 9 % )\nTotal pins: 60 / 475 ( 13 % )\nTotal memory bits: 344,064 / 483,840 ( 71 % )\nTotla PLLs: 1 / 4 ( 25 % )\nMaximum clock speed (slow model): 56.96 MHz\n\n\n \n\n\n \n \n \n\n===== \n Contact =====\n\nIf you have any questions about the STORM Core / STORM SoC or if you want to give any kind of\nfeedback, feel free to drop me some lines... ;)\n\nstnolting@gmail.com\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe processor is running in it's BETA status.\nHowever, currently I'm am concentrating on my new project: Atlas 2k Processor" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - zero_gravity name: storm_soc status: FPGA proven svn-updated: Feb 3, 2013 updated: Mar 14, 2014 wishbone-compliant: 1 - category: Other created: Mar 22, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - egorkrivtsov name: study_risc_core_8bit status: Empty updated: Mar 22, 2014 wishbone-compliant: 0 - category: Processor created: Oct 25, 2012 description: "===== \n Description =====\n\nsub86 is a frugal 32bits cpu that executes a small subset of the legacy x86-32 instructions.\nThe core has been designed with a C compiler back end code generator with three focus : \n- limit the number of opcode and instructions as much as possible.\n- the resulting binary code must run functionally equivalent on real PC and on sub86 core.\n- make the core as small as possible, by limiting the number of required hardware ressources ( alu , multiplier , number of registers : only EAX/EBX/ECX/EDX/ESP/EBP/PC/flags registers are implemented).\n\nThe status of the development (in Dec 2012) is debugging using dhrystone on a small subsystem, as of now the system shows\na 0.22DMIPS/MHz or 22DMIPS @ 100MHz.\nAlso test are on going for running a unix like os (xinu) in a 94kB snapshot.\n\nThe limited opcodes implemented creates bigger binaries, around 1.5x has been observed.\n\nIn the SVN repository there is only the verilog file for the core and no test bench, for the moment." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ultro name: sub86 status: Alpha svn-updated: Jan 4, 2013 updated: Dec 18, 2012 wishbone-compliant: 0 - category: Other created: Sep 4, 2013 description: "===== \n Description =====\n\nSimple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C implementation of algorithm provided too). \n\nHigh wiring complexity due to explicit \"neighbor\" interconnect (row, column, and 3x3 sub-block) may result in unroutable designs on FPGA families with reduced routing resources. \n\nWorking on an Zynq XC702 FPGA." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dsheffie name: sudoku status: Alpha svn-updated: Nov 19, 2013 updated: Sep 5, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Dec 27, 2011 description: "===== \n Description =====\n\nThe DLX processor is an academic processor described in in John L. Hennessy and David A. Patterson's Computer Architecture: A Quantitative Approach. Our project aims to offer a decent structural VHDL description of the processor. Moreover, advanced computer architecture features, power management, debug unit, memory management unit and OCP will be added to the project. The final goal of the project is to provide a multi-processor system-on-chip which can support VLSI research or simple embedded application." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lenzo name: superscalar_dlx status: Empty svn-updated: Oct 31, 2012 updated: Oct 31, 2012 wishbone-compliant: 0 - category: Testing / Verification created: Aug 26, 2014 description: "===== \n Description =====\n\nThe SystemVerilog Directed Test Bench.\nThis project contains an exact duplication of the VHDL Test Bench Package parser and usage model. This enables users to create a simple test environment for verification efforts using SV. This also enables scripts that were used on the VHDL system to be reused in a SV environment. (providing the same functionality is coded in the SV environment.)\n\nCurrent state is Beta, please report any problems to the bug tracking system so I can address issues." language: Other license: Apache License version 2.0 licenselink: http://opensource.org/licenses/Apache-2.0 maintainers: - sckoarn name: sv_dir_tb status: Beta svn-updated: Aug 26, 2014 updated: Aug 26, 2014 wishbone-compliant: 0 - category: Processor created: Oct 20, 2014 description: "===== \n Description =====\n\nSweet32 is best described as a \xE2\x80\x98no-frills\xE2\x80\x99 Minimal-RISC 32bit microprocessor, created by Valentin Angelovski in Melbourne Australia.\n\n\nDesigned with low gate-count in mind, typical Sweet32 logic utilization on the \nLattice MachXO2 FPGA (for example), is 842 LUT4 elements in a standard configuration \nand area-optimized form. Further details can be found in the Sweet32 RISC CPU overview 0v80. HDL sources can be found in the SVN link given above \n\n\nSweet32 Architecture Summary:\n\n\n 16x32-bit General Purpose CPU registers\n 27 Instructions, Von Neumann and Big-endian oriented core\n 16x16-bit multiplier standard, with optional 32x32-bit multiplier support\n single-cycle external Interrupt channel\n Basic Trace/debug interrupt support included\n Small FPGA Footprint\n Sweet32 minimum-system example includes the following functional elements:\n \n Sweet32 CPU and BIU (Bus interface unit) running at 33.3MHz and 100MHz respectively\n 4KBytes RAM implemented as Block RAM and can also function as Boot ROM\n 16-bit programmable system timer\n 1 x UART\n 1 x 11-bit sigma-delta ADC input channel\n 2 x 11-bit sigma-delta PWM output channels\n 4-bit User output port\n \n Sweet32 VHDL is released under LGPL 2.1\n C compiler support effort currently in progress" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Valentin_A name: sweet32_cpu status: FPGA proven svn-updated: Nov 21, 2014 updated: Nov 21, 2014 wishbone-compliant: 0 - category: Memory core created: Dec 16, 2010 description: "===== \n Description =====\n\nFIFO Queues are used in switches. This core designed a buffer which is configurable in term of size and width. Size of buffer defines total number of word in buffer and width defines word size. There is also a port which returns asserts when there are specific number of free words in buffer. If free words are equal or higher than this specific number, free signal is asserted. This specific number is configurable. Buffer also has read/write/clock/reset controlling signals and has 2 buses; Data in and Data Out. Buffer can be accessed for read and write at same clock cycle, but one cycle needed to retrieve currently writing data." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ahmadlashgar name: swich_buffer status: Empty updated: Dec 16, 2010 wishbone-compliant: 0 - category: Processor created: Oct 27, 2001 description: "===== \n Description =====\n\n32 bit pipelined processor.\nInstruction set is non conventional in that it does not use a conventional decoder for instructions. The instruction set is made by collecting together \"atomic\" control signals together to form the instruction. This was done to eliminate the need for the decoder and save an extra pipeline stage. As a consequence latency is reduced and recovery from pipeline flushes do not degrade performance as badly.\n\nThe design goals for the processor were speed, small size and flexibility.\nAn extensible bus architecture is supported so that extra functions and bus architectures could be tightly coupled to the processor. This would support such functions as adding DSP instructions,multiple processor and network processing to the processor.\n\nPlease refer to /sxp/doc/instr.txt \nfor more information about the instruction set. \n\n(The SXP processor was built from scratch using the GPL'ed Verilog simulator Icarus. The instruction set cannot be copyrighted and the architecture has been taught in computer architecture classes for more than 20 years. I feel that this core is pretty safe from copyright and IP patent concerns.)\n\nFor more information see /sxp/doc/README.txt\nThis will supply more information about the project and its\norganization.\n\nSXP Designers:\nSam Gladstone\nBob Hoffman\nNate Gregoire\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Verilog compatible with Icarus verilog simulator.(Latest Dev release)\n- Fast recovery from pipeline flushes\n- Instructions tightly coupled with pipeline control circuits.\n- Extensible bus architecture\n- Includes functionality for both synchronous and memory reg file\n- Interrupt handling\n- Harvard architecture\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Processor is synthesizable. (Tested with Synopsys DC)\n- Processor is fully simulatable with any Verilog simulator. \n- C++ processor model correctly follows Verilog behavior\n- \"Coder\" visual instruction generator works correctly. (TK/TCL)\n- Processor correctly handles interrupts.\n- Programmable timer circuit (halt signal, interrupt timer, etc.) works fine.\n- Instruction level trap (virtual memory, illegal op, etc.) being developed." language: Verilog license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - samg name: sxp status: Beta svn-updated: Mar 10, 2009 updated: Dec 12, 2001 wishbone-compliant: 0 - category: Memory core created: Oct 9, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - madhu54321 name: synchronous_reset_fifo status: Stable svn-updated: Dec 19, 2011 updated: Dec 19, 2011 wishbone-compliant: 0 - category: System on Chip created: Sep 9, 2003 description: "===== \n Description =====\n\n6805 compatible CPU Core. Does not have any of the standard 6805 on chip peripherals at this stage other than the parallel I/O port.\n\nThis was the first of the 68xx processors I attempted and have only just got around to completing it..\n\nThe Home Page for the project is Here \n \n\n\n \n \n \n\n===== \n Features =====\n\n- 6805 compatible core\n- 4 x 8 bit Parallel I/O ports\n- Dual 8 bit Timer\n- MiniUART compatible with 6850 ACIA.\n- Runs with an E clock of 12.5MHz and system clock of 25MHz\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Prints out \"Hello World\" and waits for an input character\n- Implemented on B5-X300 Spartan 2e board\n- Needs to include a Multiply instruction to be compatible with the C8" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - dilbert57 - davidgb name: system05 status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 7, 2008 wishbone-compliant: 0 - category: System on Chip created: May 16, 2003 description: "===== \n Description =====\n\n6809 System On a Chip that emulates the SWTPc 6809.\n\nIt has been ported to a variety of FPGA boards including the XESS XSA-3S1000, BurchED B5-X300 and Digilent Spartan 3 Starter board.\n\nThe System09 project page with revision history can be found at http://members.optusnet.com.au/jekent/system09 .\n\nSystem09 runs the Flex9 disk operating system for the 6809 which can be found at the Flex Users Group . The Flex disk operating system and most of the associated software has been placed in the public domain. The source code for Flex9 can be found in the CVS repository.\n\nI have included ROMs for the NOICE debugger for the 6309/6809.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 6809 instruction compatible\n- 6850 compatible ACIA/UART (57.6 KBaud)\n- Hardware Trap Logic\n- Dual 8 bit I/O port\n- Simple timer\n- 80 x 25 character Video Display with colour attributes\n- Compact Flash interface\n- PS/2 Keyboard Interface\n- SYS09BUG Monitor ROM with Video driver\n- Dynamic Address Translation supports up to 1Mbyte of RAM\n- Fits in 300KGate Spartan IIe\n- Uses Xilinx Block RAM for monitor ROM and VDU memory.\n- Optional NOICE ROMs\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Implemented on XESS XuLA-200 using ISE 12.4.\n- Implemented on Terasic DE1 board using Altera Quartus II.\n- Implemented on XESS XSA-3S1000 + XST-3.0 running Flex9 from IDE drive / CF card\n- Implemented on Digilent XC3S200 Starter Board with RAM disk\n- Implemented on BurchED B5-X300 FPGA Board running Flex9 from CF.\n- Limited Implementation on Digilent XC3S500E starter board using Block RAM.\n- Runs the SYS09BUG Monitor ROM with Video Display drivers.\n- Runs the Flex9 Disk operating system from RAM Disk, IDE Drive or Compact Flash\n- Also run NOICE Monitor for the 6809\n- Implemented with WebPack ISE 7.1i for upward compatibility." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - dilbert57 - davidgb name: system09 status: Stable svn-updated: Aug 6, 2012 updated: Oct 9, 2011 wishbone-compliant: 0 - category: Processor created: Sep 9, 2003 description: "===== \n Description =====\n\n68HC11 System on a Chip designed for a 300K Gate Spartan II, but will fit in a 200K gate device. It does not include the 68HC11 peripherals.\n\nThe Home page for the project is Here \n \n\n\n \n \n \n\n===== \n Features =====\n\n- 68HC11 compatible CPU core\n- Modified SWTBUG Monitor ROM\n- MiniUart modified to look like a 6850\n- dual 8 bit parallel I/O port\n- Compact Flash Interface\n- Dynamic Address Translation RAM (1Mbyte addressing)\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- New release in CVS for Web Pack ISE 6.2\n- Designed for BurchED B5-X300 board\n- Runs 6800 instructions\n- Bit operators untested\n- Fractional and Integer division untested\n- Condition codes for division known not to be correct.\n- New more reliable UART runs at 57.6 Kbaud.\n- 25MHz system Clock\n- CPU runs at 12.5 MHz with 15 ns B5-SRAM module." homepage: http://members.optushome.com.au/jekent/system11/index.html language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - dilbert57 - davidgb name: system11 status: Alpha svn-updated: Mar 10, 2009 updated: Apr 7, 2008 wishbone-compliant: 0 - category: Processor created: Sep 9, 2003 description: "===== \n Description =====\n\n6800 System on a chip with added 6801 instructions. Fits on 200K Gate Spartan II board. Will fit on an XC2S100 if an external ROM is used.\n\n Sytem68 Development History\n\nMichael Hasenfratz is working on a Wishbone version of System68 called\n system6801\n\n6800 Flex Operating System and software is available from the Flex Users Group \n \n\n\n \n \n \n\n===== \n Features =====\n\n- 6800/6801 instruction compatible core \n- MiniUART Modified to look like 6850 \n- Parallel I/O Port \n- Compact Flash interface \n- SWTBUG Monitor ROM \n- Dynamic Address Translation RAM for extended addressing\n- Bus Trap logic generates interrupts on any address/data/control signal\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Runs old SWTPC & TSC Basic Interpreters.\n- Implemented on BurchED B5-X300 Spartan2e FPGA board.\n- Update More Reliable UART runs at 57.6 Kb.\n- Uses 25 MHz System Clock\n- CPU runs with 12.5 MHz E clock." language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - dilbert57 - davidgb name: system68 status: Stable svn-updated: Mar 10, 2009 updated: Apr 7, 2008 wishbone-compliant: 0 - category: System on Chip created: Aug 22, 2003 description: "===== \n Description =====\n\nA Wishbone SoC of a 6800/01 CPU based project\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Motorola 6800/01 'instruction set' CPU CORE (Object code compatable)\n- RMCA01 - Relocatable Macro Cross Assembler included (Shareware by M. Hasenfratz)\n- Tested on Altera Apex20K, Cyclone and Stratix developement boards (NIOS Kits) \n- All system components have Wishbone Interfaces:\n - 6800/01 CPU (Core by John Kent)\n - miniUart/ACIA\n - miniUart/SCI\n - Timer / Counter\n - Programmable I/O (PIO)\n - 128byte RAM [Note: uses Altera LPM_RAM encapsulated in WishBone I/F]\n - 2KB ROM with debug monitor [Note: uses Altera LPM_ROM encapsulated in WishBone I/F]\n - External SRAM 'wrapper'\n - External ROM 'wrapper'\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Wishbone CPU01 CORE, Done\n- Wishbone miniUart/ACIA (6850 style), Done\n- Wishbone miniUart/SCI (6801 Serial Communications Interface), Testing\n- Wishbone Internal Altera LPM_ROM / LPM_RAM 'wrapper', Done\n- Wishbone External SRAM 'wrapper', Done\n- Wishbone External ROM 'wrapper', Done\n- Wishbone PIO (Programmable I/O port), Testing" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - mikehsr name: system6801 status: Stable svn-updated: Mar 10, 2009 updated: Mar 10, 2004 wishbone-compliant: 1 - category: Other created: Aug 19, 2004 description: "===== \n Description =====\n\nA SystemC/Verilog random number generator based on the combination of a LFSR and a CASR with very good statisticall properties.\nBased on the Thomas E. Tkacik work available at:\nhttp://ece.gmu.edu/crypto/ches02/talks_files/Tkacik.pdf\n\n\nThis work is given by Universidad Rey Juan Carlos (Spain)\nwww.gdhwsw.urjc.es\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Very good statisticall properties\n- Synthesizable\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Done" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jcastillo name: systemc_rng status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 9, 2010 wishbone-compliant: 0 - category: Crypto core created: Jul 2, 2004 description: "===== \n Features =====\n\n- SystemC and Verilog code is provided\n- Verified using TLM(Transaction Level Modelling Style)\n- Encoder and decoder in the same block\n\nThis work is given by Universidad Rey Juan Carlos (Spain)\nwww.gdhwsw.urjc.es\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 128 bits low area implementation uploaded\n- 192 bits low area implementation uploaded\n \n\n\n \n \n \n\n===== \n Description =====\n\nHere you can find two different implementations of AES encryption algorithm:\n - A 128 bits AES algorithm focusing on very low area applications.\n - A 192 bits AES algorithm focusing on very low area applications.\n \nThe 128 bits low area implementation takes about 500 cycles to encrypt/decrypt a block. \nThe 192 bits low area implementation takes about 280 cycles to encrypt/decrypt a block. \nThey don't use memories to store the S-box and have many other architectural improvements to reduce the area comsumption.\n\nImplements the encoder and decoder in the same block.\n\nThe cores were written in SystemC RTL, and verified using TLM(Transaction Level Modelling Style).\n\nVerilog synthesizable code is also provided\n\nAll implementations have been tested on a Xilinx Virtex2 FPGA succesfully." language: SystemC and Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jcastillo name: systemcaes status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 9, 2010 wishbone-compliant: 1 - category: Crypto core created: Jul 2, 2004 description: "===== \n Description =====\n\nSystemC DES is a implementation of the DES algorithm in SystemC focusing on low area applications. \nImplements the encoder and decoder in the same block.\nIt was fully verified using TLM (Transaction Level Modelling Style) defined in the SystemC Verification Library.\nVerilog translation for synthesis is also provided.\nThe core was tested on a Virtex2 FPGA succesfully.\n\nThis work is given by Universidad Rey Juan Carlos (Spain)\nwww.gdhwsw.urjc.es\n \n\n\n \n \n \n\n===== \n Features =====\n\n- SystemC and Verilog code are provided\n- Verified using TLM(Transaction Level Modelling Style)\n- Encoder and decoder in the same block\n\n- Synthesis Results:\n\nComparation between SystemC DES project and DES IP project\n\nSynthesis results for a Xilinx XC2V1000FG456-4\n\n- DES IP \n\nArea: 11% \nFreq.: 167 Mhz \nCycles per block: 16 \n\n- SystemC DES\n\nArea: 4% \nFreq.: 90 Mhz \nCycles per block: 16\n\n\nIf you need a more troughput choose DES IP core. \nIf you need less throughput but want half area choose SystemC DES\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Writing documentation" language: SystemC and Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - jcastillo name: systemcdes status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 1, 2011 wishbone-compliant: 1 - category: Crypto core created: Aug 27, 2004 description: "===== \n Features =====\n\n- Implements the MD5 standard\n- It doesnt make the block padding, you must input the 128 bits blocks padded and in little endian mode\n- The output is given in little endian\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Done\n \n\n\n \n \n \n\n===== \n Description =====\n\nA SystemC/Verilog synthesizable MD5 hash core. \n\nThis work is given by Universidad Rey Juan Carlos (Spain)\nwww.gdhwsw.urjc.es" language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jcastillo name: systemcmd5 status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 9, 2010 wishbone-compliant: 0 - category: Communication controller created: Mar 30, 2010 description: "===== \n Description =====\n\nRS232 Protocol 16550D uart (mostly supported)\n - language : systemVerilog IEEE 1800-2005 (Quaruts2-9.1sp1 Support)\n - scale : fpga cyclone3 800cell, >50Mhz\n - bus : wishbone\n\n - \n\n \n \n\n\n \n \n \n\n===== \n TODO: =====\n\nLin's automotive standards\n -> subset of transport layer circuit" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hiroshi name: systemverilog-uart16550 status: Alpha svn-updated: May 1, 2010 updated: May 5, 2010 wishbone-compliant: 1 - category: Processor created: May 5, 2006 description: "===== \n Description =====\n\nThe T400 \xC2\xB5Controller is an implementation of National's 4-bit COP400 microcontroller family architecture. It is intended to be used as a replacement for the original chip in SOCs recreating legacy systems.\n\n\n\n\n\nIts final target is to provide design variants that are compatible with the COP420/421 and COP410L/411L family members. All of them derived from the common t400_core design. Such a sample system has been implemented in several FPGA families.\n\n\n\nCOP421-like features\n64 bytes internal RAM\n1024 bytes internal ROM (only small part used for program)\n4 MHz required performance\n\n\n\n\nThe implementation has been done with the free version of the vendor tools (Quartus II 7.2sp3 and ISE 10.1). Your mileage may vary.\n\n\n\n\n\nAltera EP1C12Q240C8:\n\n\n\n583 / 12060 Logic Elements\n8,448 / 239,616 Memory Bits (RAM & ROM implemented in memory block)\n59 MHz maximum registered performance\n\n\n\n\nXilinx Spartan-IIE XC2S300EPQ208-6:\n\n\n\n643 / 6144 Logic Cells\n2 / 16 Block RAMs (RAM & ROM implemented in memory block)\n60 MHz maximum registered performance\n\n\n\n\nThe T400 \xC2\xB5Controller has been successfully integrated in the FPGA Adventure Vision project.\n\n\n\n \n\n\n \n \n \n\n===== \n Tools =====\n\nThe following tools are integrated and are required for this project:\n\n\n\nThe Macro Assembler AS\nThe GHDL simulator\nThe Perl scripting language\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe project has Stable status:\n\n\n\nAll of the targeted functionality is implemented in synthesizable VHDL.\nVerification suite is available containing self-checking assembler patterns for all implemented instructions.\nAll instructions implemented and verified with black-box tests.\nToplevel system designs resembling COP420, COP421, COP410L and COP411L are available and verified with regression test suite.\nProven synthesizability for different FPGA families.\nStable interfaces for internal modules.\n\n\n\n\nKnown bugs will be logged on the Tracker page. Please feel free to enter any problems you encounter with this core.\n\n\n\n \n\n\n \n \n \n\n===== \n Documentation =====\n\nThe COPS Family User's Guide and the specific datasheets can be downloaded from DatasheetArchive.\n\n\n\n \n\n\n \n \n \n\n===== \n Download =====\n\nThe latest release of the T400 \xC2\xB5Controller project is version 1.1.\n\n\n\n\nGet this and all previous versions of the design files from SVN: Download repository.\n\n\n\n\nPlease keep in mind that trunk/ is work in progress and might contain smaller or bigger problems.\n\n\n\n\nYou should also check the Tracker for known bugs and see if they affect your work." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - arniml name: t400 status: FPGA proven svn-updated: May 29, 2009 updated: Aug 19, 2009 wishbone-compliant: 0 - category: Processor created: Mar 23, 2004 description: "===== \n Description =====\n\nThe T48 \xC2\xB5Controller core is an implementation of the MCS-48 microcontroller family architecture. While being a controller core for SoC, it also aims for code-compatability and cycle-accuracy so that it can be used as a drop-in replacement for any MCS-48 controller.\n\n\n\n\n\nIt can be configured to better suit the requirements and characteristics of the integrating system. On the other hand, nearly the full functionality of a stock 8048/8049 is available.\nSuch a sample system has been implemented in several FPGA families.\n\n\n\n8048-like features\n64 bytes internal RAM\n1024 bytes internal ROM (only small part used for program)\n11 MHz required performance\n\n\n\n\nThe implementation has been done with the free version of the vendor tools (Quartus II 7.2sp3 and ISE 10.1). Your mileage may vary.\n\n\n\nAltera EP1C12Q240C8:\n\n738 / 12060 Logic Elements (ROM implemented with LUTs)\n512 / 239,616 Memory Bits (RAM implemented in memory block)\n59 MHz maximum registered performance\n\n\nXilinx Spartan-IIE XC2S300EPQ208-6:\n\n771 / 6144 Logic Cells (ROM implemented with LUTs)\n1 / 16 Block RAMs (RAM implemented in memory block)\n30 MHz maximum registered performance\n\n\n\n\nAlongside with the microcontroller design, an implementation of the 8243 I/O expander chip is available.\n\n\n\n\n\nThe T48 \xC2\xB5Controller has been successfully integrated in the FPGA Donkey Kong, the FPGA Adventure Vision, and the FPGA Videopac projects.\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe project has Stable status:\n\nAll of the targeted functionality is implemented in synthesizable VHDL.\nBasic verification suite is available containing self-checking assembler patterns for all implemented instructions.\nAll instructions implemented and verified with black-box tests.\nSystem toplevel exhibits original MCS-48 interface timing.\nProven synthesizability for different FPGA families.\nStable interfaces for internal modules.\nCore functionality verified with in-depth white-box tests.\nIntegration manual available.\n\n\n \n\n\n \n \n \n\n===== \n Documentation =====\n\nThe first step of this project was to collect information of the original MCS-48 family architecture. The available documents were bundled in electronic form and represent a superset of the architecture specification for the T48 \xC2\xB5Controller. Download this document here: mcs-48.pdf (link is external to OpenCores.org).\n\n\n\n \n\n\n \n \n \n\n===== \n Download =====\n\nThe latest release of the T48 \xC2\xB5Controller project is version 1.2.\n\n\n\n\nGet this and all previous versions of the design files from SVN: Download repository.\n\n\n\n\nPlease keep in mind that trunk/ is work in progress and might contain smaller or bigger problems.\n\n\n\n\nYou should also check the Tracker for known bugs and see if they affect your work.\n\n\n\n \n\n\n \n \n \n\n===== \n Verification =====\n\nThe verification of the T48 \xC2\xB5Controller core is based on self-checking assembler tests that are executed with one single testbench.\nAll test programs contribute to the regression suite that allows automated, scripts-based verification whenever the design files have changed.\n\n\n\n\n\nThe test suite will be split up into two parts. First, a set of tests is generated to proof that each single instruction works in the expected way. As this excludes all implementation specific issues and only looks at the architectural features, these tests are called black-blox tests.\nWhen issues with the internal implementation of some features arise, more in-depth tests are necessary to stimulate the design in a way that triggers potential bugs. These tests form the white-box test suite.\n\n\n\n\n\nA C-model of the core architecture is available that is used as a reference for the hardware design. This model is implemented as an executable program (native compiled code for the host system) and has been used for years now within the MAME project. It executes the same assembler tests of the regression suite and by comparing the machine state after each instruction with the RTL implementation it acts as a instruction-cycle accurate reference.\n\n\n\n \n\n\n \n \n \n\n===== \n Tools =====\n\nThe following tools are integrated and are required for this project:\n\n\n\nThe Macro Assembler AS\nThe GHDL simulator\nThe Perl scripting language" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - arniml name: t48 status: FPGA proven svn-updated: Aug 15, 2009 updated: Aug 19, 2009 wishbone-compliant: 0 - category: Processor created: Apr 25, 2002 description: "===== \n Description =====\n\n8052 compatible microcontroller core.\n\nTwo different top levels:\nT8052:\n- Single cycle synchronous RAM/ROM\n- Wishbone bus interface for memory mapped peripherals\nT8032:\n- Wishbone bus interface\n\nA utility to create VHDL ROMs is also included.\nTo create a ROM compatible with the 8052 core type:\nhex2rom [-b] inputfile.hex ROM52 13b8s > ROM52.vhd\nLeonardo Spectrum can infer the ROMs created with hex2rom to Xilinx block RAM.\n\nI have also modified the baud rate recognition of the BASIC-52 ROM to support the faster instruction timing. The modified BASIC-52 might also work with other high speed 8032 compatible cores such as the 80c320.\n\nBrowse source code here.\nDownload latest tarball here.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- All peripherals/interrupts implemented\n- Single cycle per byte fetch\n- Supports synchronous RAM/ROM\n- Single cycle MOVX (8052)\n- Optional second DPTR\n- Technology independent\n- Three stage pipeline" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - andreas name: t51 status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 1, 2014 wishbone-compliant: 1 - category: Processor created: Nov 5, 2002 description: "===== \n Description =====\n\nConfigurable cpu core that supports 6502, 65C02 and 65C816 instruction sets.\n\nA SoC debug system with ROM, RAM and two 16450 UARTs is included in the distribution. It is possible to run the NoICE debugger on this system.\n\nBatch files for runnning XST and Leonardo synthesis can be found in syn/xilinx/run/. Check these scripts to see how to use the included VHDL ROM generators.\n\nBefore you can run the scripts you need to compile hex2rom and xrom or download binaries from here. You must also replace one of the hex files in sw/ or change the batch files to use another hex file.\n\nBrowse source code here.\nDownload latest tarball here.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 6502 NMOS mode is cycle accurate, including dummy read and writes\n- Decimal mode is supported\n \n\n\n \n \n \n\n===== \n Status =====\n\n- NMOS 6502 mode supports all documented instructions\n- 65C02 and 65C816 modes are incomplete\n- Complete enough to run EhBASIC\n- The standard 6502 core is cycle accurate and used in a wide number of projects" language: VHDL license: 3-clause BSD licenselink: http://opensource.org/licenses/BSD-2-Clause maintainers: - jesus - mikej name: t65 status: FPGA proven svn-updated: Mar 10, 2009 updated: Mar 31, 2010 wishbone-compliant: 0 - category: Processor created: Mar 3, 2009 description: "===== \n Description =====\n\nA 6507-compatible microprocessor was developed. It will be used in a SoC that targets the ATARI 2600 system. RIOT(MOS 6532) and TIA chips will be developed to complete the entire system.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Cycle accuracy with original 6507.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- July 2009. Project ended.\n- April 28, 2009 - ALU 100% covered. FSM still undergoing verification.\n- March 26, 2009 - Verification started.\n- March 25, 2009 - Simulation ended. ALU and FSM are coded.\n- March 18, 2009 - Simulation started.\n- March 06, 2009 - ALU and FSM started to be coded. No support for undocumented opcodes yet.\n- March 04, 2009 - Project started." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - nscad - gabrieloshiro - creep name: t6507lp status: Design done svn-updated: Aug 31, 2009 updated: Dec 6, 2010 wishbone-compliant: 0 - category: Processor created: Apr 21, 2002 description: "===== \n Description =====\n\nConfigurable cpu core that supports Z80, 8080 and gameboy instruction sets.\n\nZ80 and 8080 compability have been proven by numerous implementations of old computer and arcade systems.\nIt is used in the zxgate project, a zx81, zx spectrum, trs80 and Jupiter ACE clone project.\nAnd also in the FPGA Arcade project.\n\nA Z80 SoC debug system with ROM, RAM and two 16450 UARTs is included in the distribution. It is possible to run the NoICE debugger on this system.\n\nBatch files for runnning XST and Leonardo synthesis can be found in syn/xilinx/run/. Check these scripts to see how to use the included VHDL ROM generators.\n\nBefore you can run the scripts you need to compile hex2rom and xrom or download binaries from here. You must also replace one of the hex files in sw/ or change the batch files to use another hex file.\n\nThe z88dk C compiler can be used with T80. The \"embedded\" configuration can be used with the debug system without modifications.\n\nBrowse source code here.\nDownload latest tarball here.\n\nThanks to MikeJ for some serious debugging and to the zxgate project members for invaluable Z80 information.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Technology independent\n- Up to 35MHz clock in Spartan2 -5 using XST synthesis\n- 10k gates and up to 100MHz in 0.18 CMOS\n- Supports all undocumented Z80 instructions\n- Supports all Z80 interrupt modes\n- Correct R register behaviour\n- Correct Z80 instruction timing\n- Almost 100% correct behavior of the undocumented Z80 flags\n- Both a synchronous (for implementation) and an asynchronous (for board level simulations) Z80 top level\n- Only a synchronous 8080 top level\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Z80 compability and functionality thoroughly verified in FPGA\n- The gameboy mode is experimental\n- No gameboy top level" language: VHDL license: 3-clause BSD licenselink: http://opensource.org/licenses/BSD-2-Clause maintainers: - jesus - mikej name: t80 status: Stable svn-updated: Mar 10, 2009 updated: Apr 16, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Mar 21, 2011 description: "===== \n Description =====\n\nA custom instruction for approximation of the hyperbolic tangent function tanh(x) with a max. error of 0.1" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - psant064 - davidopoulin name: tanhapprox status: Alpha svn-updated: May 14, 2011 updated: Mar 21, 2011 wishbone-compliant: 0 - category: Communication controller created: Nov 24, 2013 description: "===== \n Description =====\n\nTCP Socket\n\n\n\nTCP Socket is a TCP/IP stack implementation. The core acts as a server, allowing a remote client to establish a bidirectional TCP socket connection directly to logic within your FPGA.\n\n\n\nFeatures\n\nEasily add network connectivity to your FPGA\nNo need for a soft CPU\nSmall footprint (less than 800 LUTs in Spartan 6)\nFree Open Source Solution (MIT license)\nConnect to your FPGA with a web browser or telnet client\n\n\n\n\nImplementation\n\n\nTCP Socket is implemented in C, and is compiled into synthesisable Verilog using the Chips development environment (included). A precompiled Verilog module precompiled/server.v is also provided to get you up and running. For more details check out TCPIP.pdf.\n\n\nDemo\n\n\nA simple web-app demo for the Digilent Atlys Spartan 6 development card is provided. This includes everything you need to get up and running, including the Ethernet MAC. If you want to give it a try, why not use the precompiled .bit file. For more details check out README.pdf." language: Verilog license: MIT licenselink: http://opensource.org/licenses/MIT maintainers: - jondawson name: tcp_socket status: FPGA proven svn-updated: Dec 23, 2013 updated: Sep 22, 2014 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Features =====\n\n- 8 bit parallel backend interface\n- Needs external Framer\n- Supports E1 bit rate and time slots (32 time slots or 32 DS0 channels at bit rate 2.048Mbps)\n- Supports ST-Bus (Serial Telecom bus) interface.\n- Routes time slots to/from HDLC controller via the backend interface and software support or to/from memory.\n- Supports read for all or partial TDM slots from the ST-bus.\n- Supports write for all or partial TDM slots to ST-bus.\n- Supports two serial lines one input and one output.Mli>9. It supports N\xC3\x9764 mode (i.e. it supports sampling (or writing) to N consecutive time slots)\n- Supports two serial lines one input and one output.\n- Can be connected to other ST-Bus compatible devices via serial or star configurations.\n- If no data is available for transmission it sends all ones.\n- Backend interface uses the Wishbone bus interface which can be connected directly to the system or via FIFO buffer.\n- Optional External FIFO buffer, configuration and status registers.\n- The core will be made of two levels of hierarchies, the basic functionality and the Optional interfaces and buffers which makes it easy to add extra serial lines by duplicating the TDM controllers in parallel. \n- ISDN (2B+D) support can be supported by adding three parallel HDLC controllers on the first three time slots. \n- For complete specifications refer to spec document\n \n\n\n \n \n \n\n===== \n IMAGE: tdm_top.jpg =====\n\nFILE: tdm_top.jpg\nDESCRIPTION: Core top block diagram\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Code is ready for both TDM and ISDN controllers in the OpenCores CVS (see Download section). \n- Need help in verfying the design. \n \n\n\n \n \n \n\n===== \n Resource usage =====\n\nTDM core: which includes ST-Bus interface that inserts/samples 32 channels and does the conversion between serial and parallel representation.\n\n\nVendor\n\nDevice\n\nSize\n\nFrequency\xC2\xA0\n\nBoard Tested\n\nFunctional Test\n\nNotes\n\n\n\nAltera\n\nEP20K100EBC356-3\n\n130LCs\n\nCLK_I(backend)=139.06MHz\n\n-\n\n-\n\nNo optimization was peroformed, using Quartus II" language: VHDL license: custom licensetext: "This VHDL design file is an open design; you can redistribute it and/or\nmodify it and/or implement it after contacting the author\nYou can check the draft license at\nhttp://www.opencores.org/OIPC/license.shtml\n" maintainers: - khatib name: tdm status: Stable svn-updated: Mar 10, 2009 updated: Dec 5, 2001 wishbone-compliant: 1 - category: Communication controller created: May 3, 2003 description: "===== \n Description =====\n\nThe TDM_Switch core is a non-blocking digital switch that has a capacity of 256 x 256 channels at 2.048 Mb/s. Some of the main features are: Processor Mode and input offset delay.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 256 x 256 channel non-blocking switching at 2.048 Mb/s\n- Accept 8 serial data streams of 2.048 Mb/s\n- Per-stream frame delay offset programming\n- Connection memory block programming\n- Microprocessor Interface\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis IP core is synthesized for Xilinx SPARTAN-II series FPGA\xE2\x80\x99s, fit at xc2s50-6tq144 device and the post place & route simulation model simulate with Cadence NC-Sim simulator." language: Verilog license: unknown maintainers: - armanas name: tdm_switch status: Stable svn-updated: Mar 10, 2009 updated: Dec 19, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Apr 3, 2013 description: "===== \n Description =====\n\nThis IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx platforms. \nResource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower.\n\nA complete description can be found in the ternary adder documentation: http://opencores.org/usercontent,doc,1365162582\n\nNote that the used method for the Xilinx ternary is patented (US patent no 7,274,211). Hence, only private, research or non-commercial use is allowed with this implementation!" language: VHDL license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - plutonium name: ternary_adder status: FPGA proven svn-updated: Apr 5, 2013 updated: Jan 14, 2015 wishbone-compliant: 0 - category: Testing / Verification created: Aug 7, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Other license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vivekv name: testbench_for_fifo status: Empty updated: Aug 7, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Apr 27, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - Malaskar name: tftp_v2 status: Empty updated: Apr 27, 2011 wishbone-compliant: 0 - category: Processor created: Nov 26, 2007 description: "===== \n ATTENTION! =====\n\nOnly the SVN was updated.\nI don't know how I can update the latest version download. \n \n\n\n \n \n \n\n===== \n Description =====\n\nThis is a stable Version of a 68000 compatible CPU. \nIt is an adapted Version to use with the Minimig Core. \n\n\"compatible\" means that most of byte and word Instructions are cycle exact but many other Instructions are faster.\n\"adapted\" means that the synchronous Mode, some bus control signals and the FC Out are missing. They are not needed for the minimig. \n \n\n\n \n \n \n\n===== \n Features =====\n\ncirca 3600 LC's on a ALTERA Cyclone II,\ncirca 2700 Slices an a XILINX Spartan 3,\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nTested with the Dennis van Weeren Minimig Core on the C-One Board with FPGA Extender from Individual Computers.\nSource Code and Bitstreamfiles here:\nhttp://c64upgra.de/c-one/\n\nlatest bugfix:\n14.jun.2010 bugfix Movem with regmask=XFFFF and regmask=X0000\n Add missing Illegal $4AFC\n10.feb.2009 shift and rotation opcode\n21.jan.2009 insert missing RTR opcode" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tobiflex name: tg68 status: FPGA proven svn-updated: Jun 14, 2010 updated: Jun 13, 2012 wishbone-compliant: 0 - category: Other created: Nov 16, 2009 description: "===== \n Description =====\n\nTechnica Corporation is sponsoring a new open source project. Wizardry, an open source network intrusion detection system, provides protocol analysis as well as deep packet inspection. Target for the Virtex 4 FPGA platform, this project includes several hardware components that enable basic network intrusion detection functionality: \n\n\xE2\x80\xA2\tThe Embedded Protocol Analyzing Classifier (EmPAC) is designed to perform the task of packet classification through protocol analysis. Its goal is to take an unclassified byte stream coming from the Ethernet Physical Layer Interface (PHY) and partition and classify the data blocks into corresponding protocol fields. These include header information such as source and destination address, header and payload sizes, and protocol flags, as well as the payload fields themselves.\n\n\xE2\x80\xA2\tThe Enhanced Reconfigurable Content Process (eRCP) is a processor designed as a component of Wizardry to perform the task of inspecting incoming preparsed Ethernet frames for matches to Regular Expressions.\n\n\xE2\x80\xA2\tThe Reconfigurable Double Data Rate Synchronous Dynamic Random Access Interface Memory Controller (RDIC) provides each component of Wizardry with priority-based Wishbone compliant access to shared memory resources. Each device may access the shared memory space of other components, along with its own personal private (read and write) and reserved (read only) portions of memory. RDIC supports up to 8 separate Wishbone compliant devices.\n\n\xE2\x80\xA2\tThe Java Optimized Processor (JOP) is an open source Java Virtual Machine implemented in VHDL that provides an interface to the FPGA. JOP also enables configuration of other components included in Wizardry. This component has write access to the reserved memory space of each component (for configuration data), and has read access to the shared memory space of other components (to retrieve results and output from each component).\n\n\xE2\x80\xA2\tThe Web Server provides an interface into the NIDS for the user. As the front end of the Wizardry, the Web Server contains web pages that allow the user of Wizardry to configure modules and view statistics about the state of the FPGA.\n\n\n \n\n\n \n \n \n\n===== \n Discussion Board =====\n\nhttp://tech.groups.yahoo.com/group/wizardry_group/" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - mcwaccent name: the_wizardry_project status: Mature svn-updated: Jan 19, 2010 updated: Jan 21, 2010 wishbone-compliant: 1 - category: Processor created: Nov 23, 2009 description: "===== \n Overview =====\n\n\nTheia GPU Overview\n\n\nTheia is a fully programmable Graphic Processing Unit written in structural Verilog\nTheia features a multi-core architecture.\nTheia uses a Ray-Cast approach to perform the RENDER. The Multi-core architectue benefits from\nthe parallel nature of Ray casting.\nEach core has a pipe-lined SIMD ALU, capable of performing Fixed Point arithmetic on 3D vectors.\nTheia's instruction set includes logic, arithmetic and flow control instructions.\n\nTheia features a default code written into each core's ROM.\nThe default code allows a fully functional RENDER including texturing with bi-linear filtering.\nThe user can write his own Shader program for special effects, or even overwrite the entire\ndefault code with his own!\nFor more details, see the Examples section under SVN.\n\n\nHigh level Architecture\n\n\nThe\nNext diagram ilustrates the high level GPU architecure.\n\n\n\n\n\n\nThe\nThe GPU is has multiple cores.\nThe Cores communicate with the GPU Memory using the WishBone protocol.\nThe internal GPU memory is a combination of no-share with\na cross-bar and a HUB for geometry and textures\nA Host module, is the interface between the 'outside world' (Desing Test Environment) and\ninternal GPU Blocks.\n\nNote:Although the GPU has been written in such to synthetizable, THEIA only supports behavioral simulation at the moment.\n\n Simulation Output\nYou can actually see an image as the output of the simulation\nPlease look at the Examples folder under the SVN trunk for more information\nHere are some examples of simulation outputs:\n\n\n\n\n\n\nDebug Capabilities\n\nThe simulation can be configured to generate verbose code dumps that allow you to see every instruction executed on each core\nHere is a example of a piece of output log for Core0:\n\n\n\t\t\t\n[CORE 0] IP: 142( 63068700ns ZERO\t 0080 [ 00000000 00020000 00000009 ][ 00000000 00020000 00000009 ] = [ 00000000 00000000 00000000 ])\n[CORE 0] IP: 143( 63068720ns SETX\t 0049 [ 00020000 00000000 00000000 ][ 00020000 00003106 00001d6a ] = [ 00020000 00003106 00001d6a ])\n[CORE 0] IP: 144( 63068740ns SETX\t 0047 [ 00000000 00000000 00000000 ][ 00000000 fffaccae 00000000 ] = [ 00000000 fffaccae 00000000 ])\n[CORE 0] IP: 145( 63068760ns SUB\t 0064 [ fffb0000 00040000 00000000 ][ 00050000 00040000 00000000 ] = [ fff60000 00000000 00000000 ])\n[CORE 0] IP: 146( 63068780ns SUB\t 0065 [ fffb0000 fffa0000 00000000 ][ 00050000 00040000 00000000 ] = [ fff60000 fff60000 00000000 ])\n[CORE 0] IP: 147( 63068800ns SUB\t 0058 [ 00000000 00040000 00020000 ][ 00050000 00040000 00000000 ] = [ fffb0000 00000000 00020000 ])\n[CORE 0] IP: 148( 63068840ns CROSS\t 0059 [ ffff2736 fffe3ac0 ffff9d79 ][ fff60000 fff60000 00000000 ] = [ fffe135d 0001eca3 fffb61b2 ])\n[CORE 0] IP: 149( 63068880ns CROSS\t 005a [ fffb0000 00000000 00020000 ][ fff60000 00000000 00000000 ] = [ 00000000 fff60000 00000000 ])\n[CORE 0] IP: 150( 63068930ns DOT\t 0069 [ 00000000 fff60000 00000000 ][ fff60000 fff60000 00000000 ] = [ 00320000 00320000 00320000 ])\n[CORE 0] IP: 151( 63068980ns DOT\t 006a [ fffe135d 0001eca3 fffb61b2 ][ fffb0000 00000000 00020000 ] = [ 00003149 00003149 00003149 ])\n[CORE 0] IP: 152( 63069030ns DOT\t 006b [ 00000000 fff60000 00000000 ][ ffff2736 fffe3ac0 ffff9d79 ] = [ 0008da40 0008da40 0008da40 ])\n[CORE 0] IP: 153( 63069080ns DOT\t 0066 [ fffe135d 0001eca3 fffb61b2 ][ fff60000 00000000 00000000 ] = [ 00099f2f 00099f2f 00099f2f ])\n[CORE 0] IP: 154( 63069800ns DIV\t 0063 [ 00320000 00320000 00320000 ][ 00099f2f 00099f2f 00099f2f ] = [ 000a649f 000a649f 000a649f ])\n[CORE 0] IP: 155( 63070520ns DIV\t 0067 [ 00003149 00003149 00003149 ][ 00099f2f 00099f2f 00099f2f ] = [ 00000a3e 00000a3e 00000a3e ])\n[CORE 0] IP: 156( 63071240ns DIV\t 0068 [ 0008da40 0008da40 0008da40 ][ 00099f2f 00099f2f 00099f2f ] = [ 0001d710 0001d710 0001d710 ])\n[CORE 0] IP: 157( 63071260ns JGEX\t 009e [ 00000a3e 00000a3e 00000a3e ][ 00000000 fffaccae 00000000 ] = [ 00000000 00000000 00000000 ])\n[CORE 0] IP: 159( 63071280ns JGEX\t 00a0 [ 0001d710 0001d710 0001d710 ][ 00000000 fffaccae 00000000 ] = [ 00000000 00000000 00000000 ])\n[CORE 0] IP: 161( 63071300ns ADD\t 0048 [ 00000a3e 00000a3e 00000a3e ][ 0001d710 0001d710 0001d710 ] = [ 0001e14e 0001e14e 0001e14e ])\n[CORE 0] IP: 162( 63071320ns JLEX\t 00a3 [ 0001e14e 0001e14e 0001e14e ][ 00020000 00003106 00001d6a ] = [ 00000000 00000000 00000000 ])\n[CORE 0] IP: 164( 63071340ns JGEX\t 00ad [ 000a649f 000a649f 000a649f ][ 01f40000 000a6d67 000a6d67 ] = [ 00000000 00000000 00000000 ])\n[CORE 0] IP: 165( 63071360ns COPY\t 005f [ 000a649f 000a649f 000a649f ][ 00000000 00020000 00000009 ] = [ 000a649f 000a649f 000a649f ])\n\t\t\t\n\t\t\n\t\n\n\n\nThanks for your interest in the project.\nPlease feel free to contact me any questions or help running the Simulation!." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - diegovalverde name: theia_gpu status: Beta svn-updated: Nov 7, 2012 updated: Aug 16, 2011 wishbone-compliant: 1 - category: Arithmetic core created: Mar 14, 2011 description: "===== \n Description =====\n\nTheora encoder core implementation." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - russian name: theora status: Empty updated: Mar 15, 2011 wishbone-compliant: 0 - category: Crypto core created: May 6, 2011 description: "===== \n Description =====" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: threeacompactaes status: Stable svn-updated: May 11, 2011 updated: Apr 16, 2013 wishbone-compliant: 0 - category: Crypto core created: Sep 28, 2013 description: "===== \n Description =====\n\nThree different implementations of the AES-128 (VHDL)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: threeaesc status: Stable svn-updated: Sep 29, 2013 updated: Sep 29, 2013 wishbone-compliant: 0 - category: Coprocessor created: Jun 10, 2010 description: "===== \n Description =====\n\nA fabric coprocessor module (FCM) for the PowerPC 405 CPU providing code execution timestamp, allowing to measure precisely CPU \ncode execution times." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - robotron name: timestamp status: Mature svn-updated: Jun 11, 2010 updated: Jun 11, 2010 wishbone-compliant: 0 - category: Processor created: Mar 20, 2004 description: "===== \n Description Tiny64 =====\n\nA 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles.\nThe word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also\ndiffernet word sizes.\nDue simplicity TinyX supports no interrupts, cache, MMU, FPU.\nInterrupts may supported in the future.\n\nThe assembler syntax is unusual. because jump instructions are coded\nas MOV to the R7 register.\n\nAt March 2004 is was tested 32-Bit and 64-Bit in the Xilinx XC2S200 SpartanII.\n\n \n\n\n \n \n \n\n===== \n Features Tiny64 =====\n\n2 clock cycles on all op-codes\nR7, the PC is equal handled like a normal register\n\n \n\n\n \n \n \n\n===== \n Status Tiny64 =====\n\nMarch, 24th 2004 beta" language: VHDL license: unknown maintainers: - riedelx name: tiny64 status: Stable svn-updated: Mar 10, 2009 updated: May 7, 2007 wishbone-compliant: 0 - category: Processor created: Mar 2, 2002 description: "===== \n Description =====\n\nTiny8 a simple 8 bit microprocessor with classic CISC architecture.\nThe registers resides in RAM addressed via a base pointer in the WP\nregister (like the TMS9900). So it has 256 8-bit registers that can be combined to 128 16-bit address registers (the registers pairing is free, no adjacend register numbers needed).\nThis project contains also a simple assembler.\n \n\n\n \n \n \n\n===== \n Features =====\n\nUses an ALTERA 10k10 device, only 60% of its resources needed.\n256 8-bit registers or 128 16-bit address registers.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nready to be used" language: AHDL and schematic license: custom licensetext: "You are free to use it, also the source code.\n" maintainers: - riedelx name: tiny8 status: Mature svn-updated: Mar 10, 2009 updated: Feb 11, 2007 wishbone-compliant: 0 - category: Crypto core created: Oct 13, 2012 description: "===== \n Description =====\n\nAES (Advanced Encryption Standard) is a specification published by \nthe American National Institute of Standards and Technology in 2001, as FIPS 197.[1]\n\nAES describes a symmetric-key algorithm, in which the same key is used for \nboth encrypting and decrypting the data. The block size is restricted to 128 bits. \nThe key size can be 128, 192, or 256 bits. [1]\n\nAES operates on a 4\xC3\x974 matrix of bytes, called the state. Some rounds of transformation \nconverts the plaintext into the final cipher-text. The number of rounds is six plus \nthe key size divided by 32. One round reads the state into four 4-byte variables \ny_0,y_1,y_2,y_3; transforms the variables; xor\xE2\x80\x99s them by a 16-byte round key; \nand puts the result into z_0,z_1,z_2,z_3.[3]\n\nWhen targeting a variable-length plaintext, the plaintext must first be partitioned \ninto separate cipher blocks, and then be encrypted under some mode of operation, \ngenerally using randomization based on an additional initialization vector.[4]\n\nThe cipher feedback (CFB) mode, output feedback (OFB) mode are specified in FIPS 81. \nThe counter (CTR) mode is specified by NIST in SP800-38A.[4] The advantage of these \nmodes is only using encryption algorithm for both encryption and decryption. \nSo the AES hardware price may be reduced by 50% (not need decryption hardware).\n\nThis project has implemented AES encryption algorithm. \n\nThis project provides three cores, doing AES-128, AES-192 and AES-256 encryption separately.\n\nThe cores can be used in cipher feedback (CFB) mode, output feedback (OFB) mode, \nand counter (CTR) mode. \n\n[1]\tAdvanced Encryption Standard, http://en.wikipedia.org/wiki/Advanced_Encryption_Standard\n[2]\tJ. Daemen and V. Rijmen. AES proposal: Rijndael. Original AES Submission to NIST, 1999.\n[3]\tD. J. Bernstein and P. Schwabe. New AES software speed records. In INDOCRYPT 2008, volume 5365 of LNCS, pages 322-336, 2008.\n[4]\tBlock cipher modes of operation, http://en.wikipedia.org/wiki/Block_cipher_modes_of_operation\n\n \n\n\n \n \n \n\n===== \n How to encrypt or decrypt a message =====\n\nSuppose you use \"aes_256\" module, and the operation mode is CTR.\n\n\n\n\n\nTo encrypt something, let \"aes_256.state\" be a successive values of a \"counter\".\n\n\n\n\n e.g, in clock cycle T+0, \"aes_256.state == N+0\",\n in clock cycle T+1, \"aes_256.state == N+1\",\n in clock cycle T+2, \"aes_256.state == N+2\".\n\n\n\n\nThen \"aes_256.out\" is a binary sequence. Xor the binary sequence to the plain text to get the cipher text.\n\n\n\n\n\nTo decrypt something, let \"aes_256.state\" be a successive values of the SAME \"counter\".\n\n\n\n\n\nThen \"aes_256.out\" is the SAME binary sequence. Xor the binary sequence to the cipher text to get the plain text.\n\n\n\n\n\nIf you feel it against intuition, please read\n\nhttp://en.wikipedia.org/wiki/Block_cipher_mode_of_operation\n\n\n\n \n\n\n \n \n \n\n===== \n Feature =====\n\n- Pipeline architecture\n- Ultra high speed\n- Fully synchronous design \n- Fully synthesize-able \n- ONLY ONE clock domain in entire core \n- NO latch \n- All output signals are buffered \n- Vendor-independent code\n \n\n\n \n \n \n\n===== \n Performance =====\n\nThe maximum frequency is 324.6 MHz (on Xilinx FPGA XC6VLX240T, \nfor all of AES-128, AES-192 and AES-256 implementation).\n\nThe core can encrypt 128 bit per clock cycle.\nThe throughput is 38.4 G bit /second (=4.8 G bytes/sec) if it is working with a 300 MHz clock.\n \n\n\n \n \n \n\n===== \n Specification =====\n\nSpecification ver. 0.1.2a\n \n\n\n \n \n \n\n===== \n Synthesis result =====\n\n\n\nXilinx XC6VLX240T-1FF1156\n(by Xilinx ISE version 14.2)\n\n AES-128 \xC2\xA0\xC2\xA0 AES-192 \xC2\xA0\xC2\xA0 AES-256 \xC2\xA0\xC2\xA0\n\nNumber of Slice Registers:\n3,968 5,280 6,848\n\n\nNumber of Slice LUTs:\n3,536 4,264 6,503\n\n\nNumber of bonded IOBs:\n385 449 513\n\n\nNumber of Block RAM/FIFO:\n86 100 121\n\n\nNumber of BUFG/BUFGCTRLs:\n1 1 1\n\n\n \n\n\n \n \n \n\n===== \n License =====\n\nThis project is licensed under the Apache License, version 2." language: Verilog license: Apache License version 2.0 licenselink: http://opensource.org/licenses/Apache-2.0 maintainers: [] name: tiny_aes status: FPGA proven svn-updated: Feb 21, 2013 updated: Jul 25, 2014 wishbone-compliant: 0 - category: Communication controller created: Jan 7, 2011 description: "===== \n Description =====\n\nThis is an 8 bits SPI master controller. It features optional \nprogrammable baud rate and SPI mode selection. Altera SPI doesn't\nsupport programmable rate which is needed for MMC SPI, nor does\nXilinx SPI.\n\nIt is small. It combines transmit and receive buffer and remove unused \nfunctions. It takes only 36 LEs for SPI flash controller, or 53 LEs for \nMMC SPI controller in an Altera CycoloneIII SOPC project. While Altera \nSPI takes around 143 LEs. OpenCores SPI takes 857 LEs and simple SPI \ntakes 171 LEs.\n\nIt doesn't generate SS_n signal. Please use gpio core for SS_n, which\ncosts 3- LEs per pin. The gpio number is used for the cs number in\nu-boot and linux drivers." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hippo5329 name: tiny_spi status: FPGA proven svn-updated: Jan 13, 2011 updated: Jan 9, 2011 wishbone-compliant: 1 - category: Arithmetic core created: Apr 19, 2012 description: "===== \n Description =====\n\nTiny Tate Bilinear Pairing core is for calculating Tate bilinear pairing.\nIn fact it is a special type of Tate bilinear pairing called reduced $\\eta_T$ pairing. \n\nIts features are:\n* super-singular elliptic curve E:y^2=x^3-x+1\n* the field is the Galois field GF(3^m),m=97 or 593\n* the irreducible polynomial is x^97+x^12+2 or x^593+x^112+2\n* the group size is 151 bits or 911 bits\n* vendor independent code\n* very low hardware cost (\xE2\x89\xA40.2 US dollar) if m=97\n* released under Apache License v2.0\n \n\n\n \n \n \n\n===== \n Document & Specification =====\n\nSpecification (low secure level, 151 bits group size)\n\nSpecification (high secure level, 911 bits group size)\n \n\n\n \n \n \n\n===== \n Mathematical background =====\n\nThe reduced $\xCE\xB7_T$ pairing is introduced by Barreto et.al.\nThere are at least two related nice papers:\n[1] P.Barreto, S.Galbraith, C.O hEigeartaigh, and M.Scott. Efficient pairing computation on supersingular abelian varieties. in\nDesigns, Codes and Cryptography. Springer Netherlands, Mar. 2007, vol. 42(3), pp. 239\xE2\x80\x93271.\n[2] J.Beuchat, N.Brisebarre, J.Detrey, E.Okamoto, M.Shirase, and T.Takagi. Algorithms and arithmetic operators for computing the \xCE\xB7_T pairing in characteristic three. in IEEE Transactions on Computers, Special Section on Special-Purpose Hardware for Cryptography and Cryptanalysis, 57(11):1454-1468, 2008.\n \n\n\n \n \n \n\n===== \n Synthesis results (ISE) =====\n\nLow secure level core\n\n\n\nDevice:\nXilinx Spartan 3 XC3S200-5PQ208\n\n\nNumber of Slice Flip Flops:\t1,319\n\n\nNumber of 4 input LUTs: \t3,028\n\n\nNumber of occupied Slices:\t1,730\n\n\nNumber of bonded IOBs: \t15\n\n\nMinimum period: \t10.455ns\n\n\nMaximum Frequency: \t95.6MHz\n\n\n\n* Synthesis tool is Xilinx ISE 13.4.\n\n \n\n\n \n \n \n\n===== \n Synthesis results (Quartus) =====\n\nLow secure level core\n\n\n\nDevice:\tAltera Cyclone II EP2C20F484C7\n\n\nTotal logic elements:\t3,637\n\n\nDedicated logic registers:\t1,310\n\n\nTotal memory bits:\t25,984\n\n\nTotal pins:\t15\n\n\n* Synthesis tool is Altera Quartus II 11.1.\n\n \n\n\n \n \n \n\n===== \n Speed =====\n\nThe low secure level core computes one Tate pairing in 1.05 milliseconds if with a 50MHz clock.\n\nThe high secure level core computes one Tate pairing in 20.0 milliseconds if with a 50MHz clock.\n \n\n\n \n \n \n\n===== \n Hardware cost =====\n\nXilinx Spartan 3 XC3S200 FPGA is enough for the low secure level core.\nThe price of that FPGA is less than 0.2 USA dollar per piece in 2012.\n \n\n\n \n \n \n\n===== \n Compared to \"Tate Bilinear Pairing core\" =====\n\n\n\n\tTiny Tate Bilinear Pairing core\tTate Bilinear Pairing core\n\nDevice:\tXilinx Spartan 3 XC3S200\tXilinx Virtex 4 XC4VLX200\n\nNumber of Slice Flip Flops:\t1,319\t31,383\n\nNumber of 4 input LUTs:\t3,028\t47,083\n\nNumber of occupied Slices:\t1,730\t30,149\n\nComputation time:\t1.02ms\t0.76 ms\n\n\n* The cores both have same functionality. \n* The cores both have a low secure level. The group size is 151 bits.\n \n\n\n \n \n \n\n===== \n Improvement =====\n\nThis core follows the idea in the academic paper of Mr.Beuchat et.al. \nThis core uses 20% less FPGA slices, 50% less RAM memory than Mr.Beuchat et.al.\nBut this core is slower than Mr.Beuchat et.al.\n \n\n\n \n \n \n\n===== \n Donation =====\n\nIf this project has helped you, please consider donating an FPGA to Homer Hsing (Xilinx FPGA is preferred). To donate Homer will help Homer develop more valuable projects. To assist Homer is to assist you. :)" language: Verilog license: Apache License version 2.0 licenselink: http://opensource.org/licenses/Apache-2.0 maintainers: [] name: tiny_tate_bilinear_pairing status: Stable svn-updated: Nov 14, 2012 updated: Oct 13, 2012 wishbone-compliant: 0 - category: Crypto core created: Nov 29, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - feketebv name: tinyaes status: Empty updated: Nov 30, 2014 wishbone-compliant: 0 - category: Processor created: Apr 29, 2012 description: "===== \n Description =====\n\nThis is a tiny processor meant to be nice and simple. Here are a few of the technical goals of this processor:\n\n1. 8-bit processor (8 bit registers and operations)\n2. 16-bit address bus (capable through \"segment registers\" similar to the 8086\n3. 1 instruction per clock cycle\n4. Hopefully simple to understand code" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - earlz name: tinycpu status: Alpha svn-updated: May 29, 2012 updated: May 17, 2012 wishbone-compliant: 0 - category: Processor created: Feb 24, 2009 description: "===== \n Description =====\n\nSimple minimal VHDL RISC processor.\n\nHeavily inspired by Tim B\xC3\xB6scke and his MCPU project (Avaiable here on opencores), the processor is an accumulator based machine with an index register.\n\nThe processor, like Tim's, was designed to fit in small FPGA or large CPLD.\n\nLicense is free - do with it what you will. It would be nice if you credited me, however - we all have to work.\n\nI have no idea if implementing this core will or will not violate patents, copyrights or cause any other type of lawsuits. I provide this core AS IS, without any warranties. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Accumulator based machine\n - 8 bit accumulator\n - 8 bit index register\n\n- Address modes\n - immediate\n - register\n - indirect\n\n- Harvard architecture\n - 12 bit program word\n - 10 bit Program counter\n - 8 bit data memory\n - 256 data memory addresses\n\n- ALU with\n - carry flag\n - zero flag\n - add, subtract, and nor\n\n- 1 deep stack\n - 7 states\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Fits into CPLD using an old version of Xilinx webpack\n- As of 2001, never tested in hardware" language: VHDL license: unknown maintainers: - vincbr900 name: tisc status: Beta svn-updated: Mar 10, 2009 updated: Feb 27, 2009 wishbone-compliant: 0 - category: Other created: Jun 17, 2008 description: "===== \n Description =====\n\nThe goal of this project is to provide a simple traffic light controller for different transport modeling purposes like model railways. \nI repeat \"modeling purposes\", don't even think about using it in real-world applications :)\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Very simple, stand-alone Traffic Light Controller\n- Through generics parameterizable light timing lengths\n- Testbench written in VHDL.\n- Makefile for synthesis with XST (Xilinx) and simulation with Modelsim (Mentor Graphics).\n \n\n\n \n \n \n\n===== \n Status =====\n\nThe main phase of the project is already finished, but a lot of additional features still need to be added. \n- The fixed time control mechanism could be extended with a sensor based dynamic control. \n- A parameterizable interface for modeling different kinds of road intersections would be a nice feature. \n- Specifications are still needed!" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dimo name: tlc2 status: FPGA proven svn-updated: Mar 10, 2009 updated: Jun 18, 2008 wishbone-compliant: 0 - category: Processor created: Jul 19, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - igil name: topo13 status: Empty updated: Jul 19, 2013 wishbone-compliant: 0 - category: Other created: May 10, 2010 description: "===== \n About the TosNet project =====\n\nTosNet is developed at the University of Southern Denmark, and is intended to:\n\nReduce the development time of experimental robotic controllers to arrive faster and cheaper at fully working demonstrations of new technology and concepts.\n\nIncrease the reusability of experimental systems and components, thus increasing the life-span and utilization of these, and reducing the amount of redundant work.\n\nEase the use of interacting with experimental low-level controller, to open experimental robotics up to a wider audience, and to allow high-level developers a tighter integration with the physical robots, without involving them in the low-level particulars of embedded systems.\n\nUntil now TosNet has only been used inhouse for a number of projects. We would very much like to get feedback, opinions, ideas and comments from others though - anything will be appreciated!\n\nAlso have a look at uTosNet for a single-node \"lite\"-version of TosNet.\n\n - Simon Falsig\nUniversity of Southern Denmark\n \n\n\n \n \n \n\n===== \n Description =====\n\nTosNet is a common name for the combination of an experimental control protocol, network and framework, mainly intended for use in research and development of modular, robotic systems. It provides a very easy-to-use way of interfacing various forms of electronic hardware to each other and to high-level applications on for instance a PC.\n\nThe name TosNet is used for a number of things: \n\nThe TosNet protocol \nThe TosNet protocol is the specification used for communicating data around a TosNet network. The protocol consists of a datalink layer and an application layer, each providing different services. The TosNet datalink layer supports ring-coupled networks, and performs the initial configuration of these. During transmission it provides a network watchdog and an 8-bit CRC error detection. The TosNet application layer on the other hand supports the isochronous transmission of data between nodes, along with various more advanced features such as double-buffered memory and asynchronous node-to-node and broadcast channels.\n\nThe TosNet network \nThe TosNet network is our current FPGA-based implementation of the TosNet protocol, and of a physical layer to support it. The implementation is completely FPGA-based, apart from the physical transmission components. For this, optical toslink transmitters and receivers from Toshiba are used, which can be connected directly to most FPGA chips. The physical layer provides an effective datarate of up to 10 Mbps, using an 8b10b encoding scheme and data scrambling to avoid DC offsets, and 4 times oversampling for clock recovery.\n\nThe TosNet framework \nThe TosNet framework is a complete suite of the TosNet protocol/network, FPGA-boards and add-on modules, and software parts, that make it easy to connect a number of different types of hardware to each other and to high-level applications on a PC.\n\nThe different parts have been made as a whole, and with each other in mind, but can (in theory at least) be implemented with other protocols, networks and frameworks also.\n \n\n\n \n \n \n\n===== \n Currently available on SVN =====\n\nCurrently, the following files are available for download from the project SVN server:\n\n\nDocumentation:\n\nTosNet userguide\n\nGateware:\n\nTosNet rev3.2 (with premade ip-cores for xc3s400an-fg400 and xc6slx16-csg324 devices)\nTosNet rev3.2 MicroBlaze Peripheral, including drivers\n\nHardware:\n\nBoard designs for a modular FPGA board for a xc3s400an-fg400 device, and two different add-on boards\n\n\nComing soon:\n\nDocumentation:\n\nVarious updates\n\nGateware:\n\nTestbench\n\nSoftware:\n\nVarious software files for use with the Ethernet and USB gateways\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n\n10 Mbps data rate \nUp to 15 nodes, each with up to eight 256 bit registers (128 bit read(readable from all nodes), 128 bit write(writeable from master node)).\nCycletimes around 50 us (20 kHz cycle frequency) are achievable, depending on node and register count (typical cycletimes are 100-200 us (5-10 kHz))\nCycletime jitter is (50 ns * node position in ring after master)\nFull duplex asynchronous channel with broadcast possibility, data rate of 12 bytes per cycle.\n8 bit CRC error detection\nSynchronization between all nodes within a few microseconds (max 90 ns * number of slave nodes)\nConfigurable network watchdog, restarts the network after a certain interval of network inactivity\nDistributed as VHDL code and CoreGen .xco files\nPhysical layer uses Toslink optical cables for complete noise immunity in the transmission lines\nDynamic master-slave protocol, a master node is automatically assigned at network reset\nTested on: XC3S1500 (TosNet rev1), XC3S1000 (TosNet rev1/3), XC3S200 (TosNet rev1), XC3S250E (TosNet rev1/2), XC3S400AN (TosNet rev1/2/3), XC6SLX16 (TosNet rev2/3), XC6SLX45T (TosNet rev3)\nProtocol is completely implemented in the FPGA (only five additional external components are needed pr node)\nControlapplications for PC available when using a Spartan3 PCI Express Starter Kit, the Xilinx Spartan-6 FPGA SP605 Evaluation Kit or similar\nRequires only a 50 MHz clock, and reset signal\nExternal interface consists mainly of a blockram interface\nMicroBlaze support through custom peripheral and driver\n\n \n\n\n \n \n \n\n===== \n Revisions =====\n\n\nRevision 3.2 (initial release)\nA problem discovered with revision 3/3.1 caused certain node configurations (specifically networks with four nodes), to have very frequent communication breakdowns. This was traced to the jitter/latency optimizations implemented in revision 3, which have now been relaxed a bit. Synchronization for all nodes now happens within ~(number of nodes * 90 ns), with the jitter being ~(node address * 50 ns) for a given node. More exhaustive tests will be performed to make sure that everything now works as intended though. Additionally, the input data buffer in the datalink layer has been reduced from 8+1 bytes to 1+1 bytes. With the current application layer the large buffer was not at all necessary, and the implementation of it had been a thorn in my eye for some time now. Reducing its size decreased the slicecount by about 20 (in a Spartan6), and the RTL schematic of the datalink layer is actually viewable now :)\n\nRevision 3.1\nExchanged the 8b10b encoder/decoder modules with homemade ones. The existing ones were from Xilinx and could not be distributed without a license, which was not optimal with regard to being distributed on OpenCores. The new ones have the exact same interface, and close to the same functionality. The only exceptions are that not all control symbols are supported, the code error detection is not completely failsafe (in the case of the primary/alternate encoding of HGF symbol \"111\"), and that the decoder is not able to provide a disparity error. Neither of these features were necessary though (let alone used;). The new modules even take up a bit less space than the old ones.\n\nRevision 3\n- Asynchronous communication added. Each cycle up to 12 bytes of data are sent from the master to a single specified slave node, or broadcast to all slavenodes. A FIFO buffer is used for both input and output. The transmission is not fail-safe though, as no error-check is performed on the data, and as data may be silently discarded if the receive buffer is full. A high-level protocol should thus be implemented if transmission safety is to be guaranteed.\n- MicroBlaze interface through the PLB bus. Drivers include support for full access to shared memory block, and functionality for using the asynchronous channel.\n- Possibility of disabling both master, slave and asynchronous functionality in each node, to minimize the size of the design. \n- Revised clocking scheme. Now uses clock enables instead of derived clocks, which is the \"right\" way to do it, as all parts of the design now use the same 50 MHz clock. It also reduces the number of clock lines needed.\n- Much improved jitter and synchronization performance. For a three-node network, the cycle-to-cycle deviation (jitter) is reduced to at most 60 ns, while synchronization for all nodes in the same network now happens within ~80 ns (~1.6 us with revision 2).\n\nRevision 2 \nFeatures a redesigned physical layer, which now uses 8b10b encoding instead of 4b5b/NRZI encoding, which seems to have eliminated previous problems with offset errors. The physical layer has also been simplified by removing the MII interface, and instead using an 8-bit ad-hoc interface (similar to MII though). Thus the protocol stack uses an 8 bit datawidth all the way, simplifying quite a few elements. \n\nRevision 1\nOriginal version" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - sonicwave name: tosnet status: FPGA proven svn-updated: Aug 4, 2010 updated: Sep 7, 2010 wishbone-compliant: 0 - category: Processor created: Jun 9, 2007 description: "===== \n Description =====\n\nTotalCPU is RISC core with 12-bit instruction width and variable data width (from 12 to 64 bits). It is completely realized on Verilog-2001 and has two variants of implementation - with program counter placed in register block or defined as a standalone register. The first variant requires less hardware resources but it is almost 2 times slower then the second variant. It has its own instruction set that doesn\xE2\x80\x99t depend upon data path width.\n\nthe description and sources of TotalCPU are http://www.opencores.org/cvsweb.shtml/totalcpu/ (here)\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Design done" language: Verilog license: custom licensetext: "The product is free now, though in future there will be a fee 0.01$ per exemplar for large volumes, but free for small. Any modification of the source file headers containing the license is prohibited. If you want to do some changes in the sources, add items below the headers.\n" maintainers: - totalcpu name: totalcpu status: Design done svn-updated: Mar 10, 2009 updated: Jun 16, 2007 wishbone-compliant: 0 - category: Processor created: Dec 19, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - surya089 name: transporter status: Empty updated: Dec 19, 2010 wishbone-compliant: 0 - category: Arithmetic core created: May 31, 2013 description: "===== \n Description =====\n\nThis core takes unsigned value as degrees(input) and gives the corresponding value in IEEE-754 double (output).\nThis core can be easily configured degrees(inputs) bit width can be changed to any number of bits.\nIt only takes 10 clock cycles to complete one operation." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - draunzer name: trigonometric_functions_in_double_fpu status: ASIC and FPGA proven svn-updated: Aug 17, 2013 updated: Jul 3, 2013 wishbone-compliant: 0 - category: Prototype board created: Jun 12, 2006 description: "===== \n Description =====\n\nBoilerplate Verilog for use in Technologic Systems TS-7300 FPGA computer at http://www.embeddedARM.com/epc/ts7300-spec-h.htm Implements bus cycle demultiplexing to an internal 16 and 32 bit WISHBONE bus and 10/100 ethernet interface. Provided as a ready-to-compile Altera Quartus II project complete with pinlocks, compiler assignments, PLL setting, and timing constraints. A simple stub module implements a 32 bit register in the address space of the 200Mhz ARM9 CPU that toggles onboard LEDs as an easily extendable example of creating a WISHBONE slave. Once compiled, simply upload the ts7300_top.rbf bitstream file to the Linux filesystem on the SD card. The 200Mhz ARM9 processor runs Debian Linux out-of-the-box and includes a \"load_ts7300\" Linux command to configure the FPGA. No JTAG/ISP cables are required and FPGA configuration takes all of 0.2 seconds. The Quartus II tools required to compile the project are available free of charge (Quartus II 6.0 web-edition or later) from http://www.altera.com\n\nIntended use of this project is both as a educational tool for evaluating and prototyping other open cores using the WISHBONE bus and as a jump start for Technologic Systems customers creating embedded products on the TS-7300 platform (or TS-7300 based custom designs). The inclusion of a 200Mhz GPP (general purpose processor) running Linux provides a powerful platform to study RC (reconfigurable computing) and combined hardware/software embedded design flows. The ethernet core included is the open source ethernet core project from http://opencores.org/project,ethmac,overview\n\nThings on the TS-7300 the FPGA (Cylone2 2C8) is connected to:\n- 8Mbyte SDRAM\n- 16 bpp video DAC on DB15 VGA connector\n- 10/100 Ethernet PHY #2\n- 2nd SD card slot\n- 8 RS232 serial ports\n- 40 pin GPIO header (includes 2 LEDs)\n- 224 megabytes address space to the 200Mhz EP9302 ARM9 CPU running Linux 2.4\n\nThe ARM9 CPU (Cirrus Logic EP9302) running Linux 2.4 is connected to:\n- 32 to 128 MB SDRAM\n- 32 to 128 MB NAND flash\n- PC/104 expansion bus\n- 1st SD card slot\n- battery backed RTC\n- 2 USB 2.0 high-speed host ports\n- 10/100 Ethernet PHY #1\n- 2 RS232/RS485 serial ports\n- 6 user jumpers (JP1-JP6)\n- 20 GPIO pins (for HD44780 LCD or matrix keypad)\n- EP2C8 Cyclone2 FPGA\n\nThe default TS supplied bitstream includes support for all the above while the included project source only includes support for the ARM9 bus interface, GPIO, and ethernet. These other cores as well as a non-GPL'ed version of the included Verilog bus interface are available from Technologic Systems directly.\n\n\n\n \n\n\n \n \n \n\n===== \n IMAGE: 7300stclwp.jpg =====\n\nFILE: 7300stclwp.jpg\nDESCRIPTION: Technologic Systems TS-7300 FPGA Computer\n\n \n\n\n \n \n \n\n===== \n Links =====\n\n- Technologic Systems homepage: http://www.embeddedARM.com\n- TS-7xxx SBC general support forum: http://groups.yahoo.com/group/ts-7000/\n- TS-7300 datasheet: http://www.embeddedarm.com/Manuals/ts-7300-datasheet.pdf\n- TS-7300 pricing/order information: http://www.embeddedarm.com/epc/ts7300-spec-p.php" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - joff name: ts7300_opencore status: FPGA proven svn-updated: Mar 10, 2009 updated: Aug 16, 2008 wishbone-compliant: 1 - category: Arithmetic core created: Sep 12, 2014 description: "===== \n Description =====\n\n\xE7\xBA\xBF\xE5\x9E\x8BCCD\xE9\x87\x87\xE9\x9B\x86\xE4\xB8\xB2\xE5\x8F\xA3\xE8\xBE\x93\xE5\x87\xBA" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hechanlging name: tsl1401 status: Empty updated: Sep 16, 2014 wishbone-compliant: 0 - category: Other created: Apr 11, 2011 description: "===== \n Info =====\n\nI had finished simple parser and I am working for Code Generate." language: Bluespec license: unknown maintainers: - chenm001 name: tsv status: Planning svn-updated: Aug 31, 2011 updated: Sep 9, 2011 wishbone-compliant: 0 - category: Communication controller created: Dec 18, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jeaander name: ttpc status: Empty updated: Dec 18, 2013 wishbone-compliant: 0 - category: Processor created: Mar 2, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this).\n \n\n\n \n \n \n\n===== \n Functional Block Diagram =====" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dinesha name: turbo8051 status: Beta svn-updated: Jul 10, 2013 updated: Feb 14, 2012 wishbone-compliant: 1 - category: ECC core created: Feb 16, 2005 description: "===== \n Description =====\n\nThis project features a double binary, DVB-RCS turbo decoder using the SOVA algorithm.\nTwo models are included:\n- a MyHDL model, along with a complete testbench,\n- a synthesizable VHDL model.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nDouble binary, DVB-RCS code\nSoft Output Viterbi Algorithm\nMyHDL cycle/bit accurate model and testbench\nSynthesizable VHDL model\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nRelease 0.3:\n - Synthesizable VHDL model\n - Fixed ponderation filtering\n\nRelease 0.2:\n - DVB-RCS interleaver\n - DVB-RCS puncturing (decoder only)\n - Controllable SNR for the noiser\n\nRelease 0.1: MyHDL model posted\n - Simulation system consists of a random data pattern generator, turbo coder, transmission channel (gaussian noiser with controlable standard deviation), turbo decoder and Bit Error Rate monitors\n - Turbo decoder generic parameters are: number of iterations, number of bits for the coding of the systematic and redundant data in the decoder, number of bits for the coding of the extrinsic information, first and second trellis' length, number of bits for the coding of the accumulated distances, length of the interleaver matrix side\n - No puncturing\n - No coder/decoder synchronization\n - No wishbone I/F\n - No in-operation BER monitoring\n - Simple line-write/column-read interleaver\n - Basic documentation (block diagrams)\n\n \n\n\n \n \n \n\n===== \n Results =====\n\nDecoder input signal width: 4 bits\nExtrinsic information signal width: 5 bits\nFirst trellis' length: 24\nSecond trellis' length: 12\nAccumulated distances signal width: 9 bits\nInterleaver frame size: 64 bit couples\nSignal-to-noise ratio: 5.1 dB\nCode rate: 1 / 2\n\nBit Error Rate:\n0.0368951613 @ iteration 0 (no decoding)\n0.0027355688 @ iteration 1\n0.0001380629 @ iteration 2\n0.0000722789 @ iteration 3\n0.0000255319 @ iteration 4\n0.0000212947 @ iteration 5" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dbrochart name: turbocodes status: Beta svn-updated: Jul 17, 2012 updated: Nov 19, 2014 wishbone-compliant: 0 - category: ECC core created: Jul 17, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: turbodecoder status: Empty updated: Jul 17, 2012 wishbone-compliant: 0 - category: Processor created: May 14, 2004 description: "===== \n Description =====\n\nThe TV80 is an 8-bit Z80-compatible microprocessor core, written in Verilog. It is based on Daniel Wallner's VHDL T80 core.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- executes 8080/Z80 instruction set\n- cycle timing is similar to original Z80\n- small die area\n- sample peripheral with GMII interface\n- Optional Wishbone wrapper for TV80 core now available\n \n\n\n \n \n \n\n===== \n Status =====\n\n- taped out in TSMC 130nm (250 Mhz, ~20k gates)\n- taped out in TSMC 65nm process (125 Mhz)\n- Microprocessor-controlled verification environment" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - ghutchis - hharte name: tv80 status: ASIC and FPGA proven svn-updated: Feb 2, 2012 updated: Oct 17, 2012 wishbone-compliant: 0 - category: Arithmetic core created: May 1, 2009 description: "===== \n Description =====\n\nRTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points.\nPresented algorithm is FHT with decimation in frequency domain.\nMain Features\nHigh Clock Speed\nLow Latency(97 clock cycles)\nLow Slice Count\nSingle Clock Cycle per sample operation\nFully synchronous core with positive edge triggering\nFlexible core control with regard to input data width\n\nDiscrete Hartley Transform is used in a wide variety of signal processing applications such as filtering, convolution, correlation, compression and so on.\nThe most popular usage of the Hartley Transform is image processing applications.\nFunctional Description\nThe N-point Discrete Hartley Transform is given by the next formula:\n \nwhere \n. RTL Verilog code which is presented here was designed to calculate 2D-FHT (8x8 points) algorithm with decimation in frequency domain.\nBlock Diagram\n\nVerification\nThis IP was verified using OVM-like verification environment.\nMain focus was made to compare RTL output data with golden reference model output data. \nAs a result: RTL is fully identical with golden reference model.\n\nImplementation Result\n\n \n Xilinx FPGA\n Slices\n DSP48\n BRAM\n Freq., MHz\n \n \n Virtex-4 xc4vlx60 \n 818\n 4\n 1\n 200\n \n\n \n\n\n \n \n \n\n===== \n Status =====\n\nRTL Verilog release of the Two Dimensional Fast Hartley Transform Algorithm.\nVerilog RTL - 1st version released. Refer to repository for latest revision.\nVerification - If you have any question please feel free to send me message.\nTestbench - If you have any question please feel free to send me message.\nDocumentation - If you have any question please feel free to send me message." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - irezki name: two_dimensional_fast_hartley_transform status: FPGA proven svn-updated: Jul 28, 2011 updated: Jul 25, 2011 wishbone-compliant: 0 - category: Crypto core created: Apr 30, 2006 description: "===== \n Description =====\n\nVHDL implementation of the twofish cipher for 128,192 and 256 bit keys.\nThe implementation is in library-like form; All needed components up to, including the round/key schedule circuits are implemented, giving the flexibility to be combined in different architectures (iterative, rolled out/pipelined etc). Manual in English is included with more details about how to use the components and/or how to optimize some of them. All testbenches are provided (tables, variable key/text, ECB/CBC monte carlo) for 128, 192 and 256 bit key sizes, along with their respective vector files.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- implementation for 128, 192 and 256 bits key size\n- core is provided in separate components\n- components' interface is simple (connection is described in manual)\n- core is synthesizable\n \n\n\n \n \n \n\n===== \n Status =====\n\n- core tested against all available testvectors\n- core is ready to be used" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - spyros name: twofish status: Stable svn-updated: Mar 10, 2009 updated: May 8, 2006 wishbone-compliant: 0 - category: Crypto core created: Feb 21, 2002 description: "===== \n Description =====\n\nTwofish is a 128-bit block cipher that can accept variable key length 128,192 and 256 bit. In this project we just use key length\n128 bit. Twofish is fundamental built by F-function, rotate-left one bit, rotate-right one bit, and XOR.The cipher has 16 round F-function . F-function is made up by four key-dependent 8-by-8-bit S-box, a fixed 4-by-4 maximum distance separable matrix over GF(2^8), a pseudo-Hadamard transform, bitwise rotation, and key scedule.\n\nAs can be seen from figure 1, input will be latched first into a register and then separated into four word. The four word then XOR with K0,K1,K2,K3. This step is called input-whitening. Data then goes through F-function. On F-function, there are various rotation, transformation and permutation are applied to it. F-function is made of two h-functions containing key-dependant S-boxes and Maximum Distance Separable Matrix (MDS) , Pseudo-Hadamard Transform (PHT). After going 16 time through this function, the four word of data are one again XOR-ed with four sub-key K4,K5,K6,K7. This step is called output whitening. Finally encrypted or decrypted data is latched into output register.\n \n\n\n \n \n \n\n===== \n IMAGE: twofish.jpg =====\n\nFILE: twofish.jpg\nDESCRIPTION: Figure 1. Structure of Twofish block Cipher\n\n \n\n\n \n \n \n\n===== \n IMAGE: qper.jpg =====\n\nFILE: qper.jpg\nDESCRIPTION: Q-permutation\n\n \n\n\n \n \n \n\n===== \n IMAGE: s-boxes.jpg =====\n\nFILE: s-boxes.jpg\nDESCRIPTION: S-boxes\n\n \n\n\n \n \n \n\n===== \n IMAGE: cleartext.jpg =====\n\nFILE: cleartext.jpg\nDESCRIPTION: Input register module\n\n \n\n\n \n \n \n\n===== \n IMAGE: ciphertext.jpg =====\n\nFILE: ciphertext.jpg\nDESCRIPTION: Output register module\n\n \n\n\n \n \n \n\n===== \n IMAGE: key-mod.jpg =====\n\nFILE: key-mod.jpg\nDESCRIPTION: Key-register module\n\n \n\n\n \n \n \n\n===== \n IMAGE: modifiedF.jpg =====\n\nFILE: modifiedF.jpg\nDESCRIPTION: Modified-F module\n\n \n\n\n \n \n \n\n===== \n Design specification =====\n\n1. Twofish can accept key-length 128, 192, 256 bit. In this project we used 128 bit key-length \n\n2. Use little-endian convention for input, output and key \n \n\n\n \n \n \n\n===== \n Status =====\n\nWe have finished designing Twofish core using VHDL, and the test result is OK." language: VHDL license: unknown maintainers: - poetoegde - hendro name: twofish_team status: Beta svn-updated: Mar 10, 2009 updated: Oct 17, 2002 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Specifications =====\n\n- as small as possible to fit in a Xilinx CPLD \n- fixed 9600 baudrate for this version \n- 1 start bit, 8 data bits, 1 stop bit data stream format \n- both interrupt-based and polling user interface\n \n\n\n \n \n \n\n===== \n Description =====\n\nSerial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net. \n \n\n\n \n \n \n\n===== \n Synthesis =====\n\nSynthesized with Xilinx Foundation 2.1i (Synopsys Express FPGA compiler, Xilinx P&R tools) for:\n- Xilinx Virtex FPGA family takes 14% of XCV50 slices (110 out of 768) \n- Xilinx 9500 CPLD family takes 43% of XC95288 macrocells(125 out of 288)\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- design is available in VHDL from OpenCores CVS (see Download section)\n- documentation will be available in short time\n- a new module, UART16550 family compatible could be developed if enough interest" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - olupas name: uart status: Stable svn-updated: May 5, 2009 updated: Apr 14, 2010 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Description =====\n\nuart16550 is a 16550 compatible (mostly) UART core. \n\nThe bus interface is WISHBONE SoC bus Rev. B.\n\nFeatures all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. \n\nThe datasheet can be downloaded from the CVS tree along with the source code. \n \n\n\n \n \n \n\n===== \n Status =====\n\n\n\nAug 2001\nCore updated and some more bugs fixed. It is now being verified more thoroughly but it is mostly usable.\n\n27.05.2001\nDocumentation and core code are updated.\n\n17.05.2001\nThe core is finished unless more bugs are found.\nThe test bench is very basic yet and is asking for your help to expand it. :-) \n\n26.01.2002\nThe core is functional in polling mode, checked on FPGA.\nShould be functional in interrupts mode too but not verified fully in hardware.\nMonitor debugging feature is added\nAll known bugs fixed.\n\n28.01.2002\nThe core is functional in all modes (interrupt and polling mode), checked on two different boards.\nFull operational in uCLinux using included 16550 driver." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - gorban - igorm - tadejm name: uart16550 status: Stable svn-updated: Mar 10, 2009 updated: Oct 2, 2011 wishbone-compliant: 1 - category: Communication controller created: Jan 14, 2009 description: "===== \n Description =====\n\nImplements a 16550/16750 UART core.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Full synchronous design\n- Pin compatible to 16550/16750\n- Register compatible to 16550/16750\n- Baudrate generator with clock enable\n- Supports 5/6/7/8 bit characters\n- None/Even/Odd parity bit generation and detection\n- Supports 1/1.5/2 stop bit generation\n- None or 16/64 byte FIFO mode\n- Receiver FIFO trigger levels 1/4/8/14/16/32/56\n- Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2\n- Automatic flow control with RTS/CTS\n- All interrupt sources/modes\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Test script creation done, should cover most functions\n- Test log file available\n\nThe core was synthesized on a Altera Cyclone II, connected to x86\nstandard hardware and than tested with standard OS drivers from:\n\n- Linux 2.2/2.4/2.6\n- Windows 2000/XP/Vista\n- *BSD\n- *DOS\n\n \n\n\n \n \n \n\n===== \n Simulation =====\n\nIt's possible to simulate and test the design with GHDL.\nA Makefile is available for starting the simulation. The testbench\ncreates a log file (uart_log.txt).\n\n\n \n\n\n \n \n \n\n===== \n Resource usage =====\n\n- Altera Cyclone II\n - 440 LE\n - 1216 memory bits\n - Frequency: 130 MHz\n\n- Xilinx Spartan 3E\n - 378 Slices\n - 1 RAMB\n - Frequency: 100 MHz" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hasw name: uart16750 status: FPGA proven svn-updated: Aug 2, 2010 updated: May 6, 2013 wishbone-compliant: 0 - category: Communication controller created: Feb 12, 2010 description: "===== \n Description =====\n\nHave you ever needed a fast and easy way to test your new FPGA board?\nYou know you have all the interfaces but it will take time to finish the software or the verification just to start debugging.\nThis core might be what you are looking for.\nThe UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. The parser supports two modes of operation: text mode commands and binary mode commands. Text mode commands are designed to be used with a hyper terminal software and enable easy access to the internal bus. Binary mode commands are more efficient and also support buffered read & write operations with or without automatic address increment.\n\nVHDL version now available\nBlock Diagram\n\n\nFor detailed information download the Core Specifications 1.0 document.\n\nSynthesis Results\n\n\n Manufacturer \n Family \n Device \n Device Utilization \n Elements Utilization \n Fmax \n\n\n Xilinx \n Spartan 3 \n xc3s50-5pq208 \n 25% \n 195 Slices \n >150MHz \n\n\n Xilinx \n Virtex 5 \n xc5vlx30-3ff324 \n 2% \n 99 Slices \n >200MHz \n\n\n Altera \n Cyclone III \n ep3c5f256c6 \n 5% \n 235 LEs \n >200MHz \n\n\n Altera \n Startix III \n ep3sl50f484c2 \n \n 165 Registers, 186 ALUTs \n >200MHz \n\n\n Lattice* \n MachXO \n LCMXO2280C-4T144C \n 10% \n 116 Slices \n >100MHz \n\n\n\n* Lattice device synthesis results provided by Paul V. Shatov" language: Verilog & VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - motilito - smuller name: uart2bus status: FPGA proven svn-updated: Feb 25, 2012 updated: Sep 11, 2013 wishbone-compliant: 0 - category: Communication controller created: Jan 15, 2013 description: "===== \n Description =====\n\nThe UART to SPI IP Core include a simple command parser that can be used to access an internal bus of SPI via a UART interface. This IP can be used understand the SPI transaction protocol. The internal bus is designed with address bus of 16 bits and data bus of 8 bits. The core implements a very basic UART transmit & receive blocks which share a common baud rate generator and a command parser. The parser supports text mode of command parsing. Text mode commands are designed to be used with hyper terminal software and enable easy access to the internal bus. \n \n\n\n \n \n \n\n===== \n Block Diagram =====" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dinesha name: uart2spi status: Mature svn-updated: Jan 31, 2013 updated: Jan 31, 2013 wishbone-compliant: 0 - category: Communication controller created: Apr 20, 2012 description: "===== \n Description =====\n\nSimple uart core with wishbone slave interface and programmable baud rate generator, based on clock speed and desired baud rate" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: uart_block status: FPGA proven svn-updated: May 12, 2012 updated: May 5, 2012 wishbone-compliant: 1 - category: Communication controller created: Apr 24, 2014 description: '' language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - pavelmvl name: uart_core status: Empty updated: Jan 20, 2015 wishbone-compliant: 0 - category: Communication controller created: Nov 13, 2013 description: "===== \n Introduction =====\n\nTransmitter and receiver in FPGA for converting UART to/from audio fiber optics.\n\n\n\nPhoto of an assembled board with annotation\n\n\n\n\nIt is wishbone compliant because using an UART , it can be added to a Wishbone UART and be of interest for a Wishbone implementer. This core is well tested.\n\nThey is two versions:\n-Fixed baudrate (0 to 2.5Mbit/s) - a full set of 2 transmitter and 2 receiver fit in a single XC9572XL CPLD\n-variable baudrate 50Mhz/n*p where n between 20 to 100 fiber optic baudrate and p>=1 baudrate divider. Fit 1x transmiter + receiver in a single XC9572XL CPLD. The baudrate is adjustable from external pins DIP SWITCH or jumper.\n\n\nThe fiber represent signal as follow :\n0 : 1 period of low frequency F signal\n1 : 2 periods of high frequency 2xF signal\n\n\nwhy en encoder/decoder and why not connect directly the UART to a fiber optic transmiter and receiver :\nBecause it would not work. The optical receiver for audio fiber optic is designed for AC signal (0.1 to 16Mhz).\n\nA duplex communication use 2 fiber optics .\n\nthe prototype use a XC9572XL CPLD from Xilinx \n\n\nThe test work with several MByte transmitted and received at 1.25Mbaud (packets of 64byte data checked by CRC).\n\nthe UART used are PIC32 procesors exchanging data on fiber optic (the UART is driven by DMA, requiring less effort for the CPU)\n\n\n \n\n\n \n \n \n\n===== \n Prototype =====\n\n\n\n\nThe prototype use two Microchip processors communicating over fiber optic\nPIC32MX220 and PIC32MX440\n\n4x optical transceiver for audio :\n\nEverlight PLR137 / PLT137\n\n2 x fiber optic cables \n\n1x CPLD board with Xilinx XC9572XL CPLD (which fit the two receiver and two transmitter).\n\n\n \n\n\n \n \n \n\n===== \n The receiver =====\n\nThe receiver sample the fiber optic signal and measure duration of periods of the input (optic_in)\nThe receiver output \n-0 for long period of input signa\n-1 for short period of input signal\n\nThe sampling frequency is 50Mhz (clock available in the CPLD)\nThe receiver integrate a low pass filter and the decoder itself that measure the frequency of the input signal (from the fiber).\nthe receiver then produce a signal suitable for the UART RX pin.\n\n\n\n\nThe low pass is probably not required but very easy to implement.\n\nThe receiver integrate also a \"learn\" bit that say if the peiods should be measured at low-to-high of high-to-low transitions on the input. This is an important phase information that the receiver automatically detect during reception.\n\nThe receiver synchronize itself with the received signal, that is a multiple of the UART bitrate.\n \n\n\n \n \n \n\n===== \n Receiver VHDL code =====\n\n--fixed bitrate version (1.25Mbit/s 8N1)\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\n\nentity spdif_to_RX is\n Port ( iCLK : in STD_LOGIC;\n optic_in : in STD_LOGIC;\n RX : out STD_LOGIC;\n\t\t\t learn_out : out STD_LOGIC\n\t\t\t );\nend spdif_to_RX;\n\narchitecture Behavioral of spdif_to_RX is\n\n\n\n--low pass\nsignal q1 : STD_LOGIC;\nsignal q2 : STD_LOGIC;\nsignal samp : STD_LOGIC;\n\n--RX generator\nsignal samp2 : STD_LOGIC;\nsignal cnt : natural range 0 to 63;\n\nsignal learn : STD_LOGIC;\n\n--constant periode_1_max : natural := (20+7);\n--constant periode_0_min : natural := (40-7);\n\n--signal RX1 : STD_LOGIC;\nsignal RX2 : STD_LOGIC;\n\nbegin\nlearn_out\n\ninput_low_pass:process (iCLK)\nbegin\n\nif (iCLK'event and iCLK= '1') then\n\t\n\tq1\tq2\tif(q1=q2)then\n\t\tsamp\tend if;\nend if;\n\nend process;\n\nfiber_decoder:process (iCLK)\nbegin \n\nif (iCLK'event and iCLK= '1') then\n\n\tsamp2\tif(samp2/=samp and samp=learn) then\n\t\tif(cnt>33) then\n\t\t\tRX\t\t\tRX2\t\telsif (cnt\t\t\tRX\t\t\tRX2\t\telsif(cnt\t\t\tRX2\t\telse\n\t\t\tlearn\t\tend if;\t\n\t\tcnt\telse\n\t\tif(cnt=20) then\n\t\t\tRX\t\tend if;\n\t\tif(cnt\t\t\tcnt\t\tend if;\n\tend if;\n\nend if;\n\t\nend process;\n\nend Behavioral;\n\n \n\n\n \n \n \n\n===== \n The transmiter =====\n\nThe transmitter receive UART signal TX and produce the fiber optic signal.\n\nThe transmitter core must synchronise the bits from TX with the local clock and at the same time synchronize itself with the START bits from the UART.\n\nThe transmittter first synchronize itself with the input START bits, then output a synchronized version (tx_bit).\n\nThe optic_stage process then transform tx_bit to optic_out, the signal suitable for the fiber optic.\n\nThe transmitter use the blank formed by the STOP bits to re-synchronize with the next START bit. When the input in uninterrupted data (ie each STOP bit is immediately followed by a START bit) and when bit_div is equal to 1 (ie the UART bitrate and fiber optic bitrate are equal) , then the transmitter relie only on the exact match of the local ocillator with the incoming data.\nAny difference is corrected at the end of incoming packet data (STOP bit not followed by START bit).\nwhen bit_div>1, re-synchronization occur at each byte and the incoming data can have a bit clock slightly different than the expected one.\n\nAs described, the transmitter core have many advantage.\n\n \n\n\n \n \n \n\n===== \n Transmitter VHDL =====\n\n--fixed bitrate version (1.25Mbit/s 8N1)\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.STD_LOGIC_ARITH.ALL; \nuse IEEE.std_logic_unsigned.all;\n--use IEEE.NUMERIC_STD.ALL;\n\n\nentity TX_to_spdif_full is\n Port ( iCLK : in STD_LOGIC;\n TX : in STD_LOGIC;\n optic_out : out STD_LOGIC\n\t\t\t );\nend TX_to_spdif_full;\n\narchitecture Behavioral of TX_to_spdif_full is\n\n\n--output flip-flop\nsignal optic_flop:STD_LOGIC:='0';\n--optic stage \nsignal optic_cnt : STD_LOGIC_VECTOR(3 downto 0);\t--value 0 to 9 (divide 50Mhz/10=5Mhz)\nsignal half0 : STD_LOGIC;\nsignal half1 : STD_LOGIC;\nsignal optic_bit:STD_LOGIC;\n--input stage\nsignal tx_cnt : STD_LOGIC_VECTOR(4 downto 0);\t\t--value 0-19 (divide 50Mhz/20=2.5Mhz)\nsignal tx_bit:STD_LOGIC:='1';\nsignal start_detected : STD_LOGIC:='0';\nsignal tx_half : STD_LOGIC;\t\t\t\t\t\t\t\t--1/2 bit\nsignal bit_position : STD_LOGIC_VECTOR(3 downto 0);--value 0-9 (bit position from start to stop)\n\n\n\n\n\n\nbegin\n\n\noptic_out\n--generate signal on fiber optic\noptic_stage:process (iCLK)\nbegin \n\nif (iCLK'event and iCLK = '1') then\n\n\tif(optic_cnt=9) then\t\t\t--divide 50Mhz / 10 = 5 Mhz \n\t\thalf0\t\tif(half0='1') then\n\t\t\thalf1\t\tend if;\n\t\tif(optic_bit='1' or half0='0') then\n\t\t\toptic_flop\t\tend if;\n\t\tif((half0='1') and (half1='1'))then\n\t\t\toptic_bit--\t\t\toptic_flop\t\t\t\n\t\tend if;\t\t\t\n\t\toptic_cnt'0');\n\telse\n\t\toptic_cnt\tend if;\n\t\nend if;\n\t\nend process;\n\n--Synchronize input (TX pin) with local clock\ninput_stage: process (iCLK,TX)\nbegin \nif (iCLK'event and iCLK = '1') then\n\t\n\n\n\tif(start_detected='0') then\n\t\tif(TX='0') then\n\t\t\tstart_detected\t\t\ttx_cnt'0');\n\t\t\tbit_position'0');\n\t\t\ttx_half\t\tend if;\t\n\telse\t\t\t\t\t\t\t\t\t\t\t--start detected=1\n\t\tif(tx_cnt=19) then\t\t\t\t\t--0.5 bit time\n\t\t\tif(tx_half='0')then\n\t\t\t\ttx_bit\t\t\telsif(tx_half='1')then\n\t\t\t\tif(bit_position/=9)then\n\t\t\t\t\tbit_position\t\t\t\tend if;\n\t\t\t\tif(bit_position=9 and tx_bit='1') then --stop bit\n\t\t\t\t\tbit_position'0');\n\t\t\t\t\tif(TX='1')then\n\t\t\t\t\t\tstart_detected\t\t\t\t\tend if;\n\t\t\t\tend if;\n\t\t\tend if;\n\t\t\ttx_half\t\t\ttx_cnt'0');\n\t\telse\n\t\t\ttx_cnt\t\tend if;\n\tend if;--start detected\nend if;--clk event\t\t\t\n\t\nend process;\nend Behavioral;\n\n \n\n\n \n \n \n\n===== \n Application =====\n\nThis is my application and it is also used for intensive testing.\n\n\n\n\n\n\n\nThis is a machine (Robot) controller . The application communicate with USB-to-fiberoptic.\nOn the other side, the fiberoptic-to-machine receive the commands and provide ACK (aknowledge) . All communication are segmented as packets and CRC controlled .\n\nThe image show a real testing (with two PIC32 cards , and the CPLD ).\n\nThe 3 number on the top are machine position\nThe 3 number on the bottom are total CRC error received by both parts (which is always 0 in normal use). The errors where numerous during developpement . It took 24hour to discover that my CPLD evaluation board did not have a 25Mhz clock as documented but a 50Mhz.\n\n\n\n \n\n\n \n \n \n\n===== \n SPDIF audio fiber optics =====\n\n\n\n\nAudio SPDIF fiber optic (TOSLINK)\n\nwith Everlight PLR137 SPDIF transceiver.\n \n\n\n \n \n \n\n===== \n PCI to fiber =====\n\nA PCI card with fiber optic transceiver.\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Variable baudrate =====\n\nThe variable baudrate version use two values :\n\n\nperiod STD_LOGIC_VECTOR (6 downto 0)\nthis is the number of 50Mhz clock period for each bit on the fiber optic.\nIt must be not too small otherwise the signal would be difficult to sample . a value not smaller than 20 (5Mhz high freq) to 100 (500Khz low freq) would be ok.\n\nbit_div STD_LOGIC_VECTOR (6 downto 0)\nthis is the ratio between baudrate on the fiber and baudrate on the TX/RX pin.\nit can be any value equal to or greather than 1\n\nfor example:\n\nOne want to achieve a UART to/from fiber optic module working at 115200baud\n\n50Mhz/115200=434.02\n\nperiod=62 (fiber optic signal 806Khz / 1.6Mhz)\nbit_div=7\nbaudrate=50Mhz/(62x7)=115207bit/s which is a good approximation of the target baudrate and is synchrone with the fiber optic baudrate.\n\nThe variable bit rate version is named V2 in the download.\n\nother values :\n\ntarget baudrate divider period bit_div actual baudrate\n1.25Mb/s 40 40 1 1.25Mb/s\n1Mb/s 50 50 1 1.0Mb/s\n750K 66 33 2 757.5K \n500K 100 50 2 500K\n250K 200 50 4 250K\n125K 400 50 8 125K\n115200b/s 434 62 7 115207b/s\n19200b/s 2604 40 65 19230b/s \n\n \n\n\n \n \n \n\n===== \n Version 3 =====\n\nI have modified the VHDL for version 3 :\n\n-Signal \"learn\" removed (it is useless because the transmitter now start each bit with a rising edge on the fiber optic\n-Synchronisation of the trannsmitter on START BITS on TX after 3/4 stop bit when bit_div >= 4 ( because in that case , the fiber optic has a resolution of 1/4 bit).\n\nI have also looked for other Xilinx CPLDs that can support this design :\nXC95xxXL\nCoolrunner 2 (XC2C000)\nCoolrunner XPLA3 (XCR3000XL)\nAll of these are very similar( at my sense..).\n\nI have build a more practical prototype with XC9572XL PLCC44, and conducted tests with the following parameters :\n\n50Mhz ocscillator , period 20, bit_div 1,@2.50Mbits/s \n50Mhz ocscillator , period 20, bit_div 2,@1.25Mbits/s \n50Mhz ocscillator , period 40, bit_div 10,@500Kbit/s \n\nThe core work absolutely perfectly on all these cases , with several Mbytes transmitted with check CRC .\n\n\n\n\n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Version 4 =====\n\nHello again,\nIn version 4 , considering the commercial adapter that i will manufacture, i had to propose a module that can handle much more different baudrates , but still using a unexpensive CPLD. \nI found finally that the VHDL can be extended to include provision for all low bitrates ( up to 300Kbs) while still including the synchronized mode . \nI have added a signal :\ndirect_mode : in STD_LOGIC\nthis signal tell the transmitter to work in direct mode , the transmitter just do direct transmission of the TX signal at high speed \nif (iCLK'event and iCLK = '1') then\n if(direct_mode='1')then\n\t\ttx_bit=TX;\n else\n..\nThis mode of transmission will accept any baudrate in fact that is much lower than the transmission rate on the fiber optic (which is still chosen rather high 2.5Mbit/s.\nThe VHDL code for version 4 which include this change is available in the download.\n\n\nFor example , i have tested my module with a simple PC serial port at 9600baud, with a conversatioon via fiber optic\n\n\n\nAn adapter is needed to convert PC serial port to 3.3V\n\n\n\nPC serial to 3.3V MAX3232 adapter" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - chipmaker78 name: uart_fiber status: Mature svn-updated: Nov 26, 2013 updated: Dec 24, 2013 wishbone-compliant: 1 - category: Communication controller created: Jan 3, 2011 description: "===== \n Description =====\n\nThis is a fully synchronous (single clock domain, no asynchronous resets) UART with a FIFO buffered cpu interface and a SystemVerilog transaction based self-checking testbench. The VHDL RTL is written in a \"single process\" style to improve code readability and lets the synthesis tool infer the flops and gates.\n\nThe cpu interface is simple (address, data in, data out, read enable, write enable).\nTransmit and receive FIFO size is configurable with a generic.\nBaud rate is register programmable.\nCurrently only support no parity bit, 8 data bits and 1 stop bit (N81)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - andrewbridger name: uart_fifo_cpu_if_sv_testbench status: Planning svn-updated: Jan 4, 2011 updated: Jan 3, 2011 wishbone-compliant: 0 - category: Communication controller created: Aug 29, 2011 description: "===== \n Block Diagram =====\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nControl the activity and status of your FPGA by targeting a memory mapped space inside it.\n\n\n\n\nBased on:\n\n\n-- elements from the GH libraries (GH_library)\n-- HLeFevre UART project (LeFevre_uart)\n\nSimple three steps access procedure:\n\n-- Write words of 2 bytes address and 4 bytes data.\n-- Ask for an update targeting the update register (default 0x8000 0x00000000)\n-- Read words of 2 bytes address and 4 bytes data.\n\nThe code comes plug and play:\n\n* the whole uart initialization process is automatic\n* 4 pins interface to the outsideworld: serial tx, serial rx, uart clock, hard reset\n* up to 2^16 32 bit wide registers for user logic control and monitor\n\n\nDeclare the registers you want to read and write in the top level entity: \n\n+ the rest will be handled automatically by FSMs.\n+ almost no documentation is required.\n+ no knowledge of the internals of the core required.\n+ the top entity is self-explanatory.\n\n\nRemotely control the logic from a PC:\n\n~ Under Windows use RealTerm to simply send and receive HEX commands (realterm.sourceforge.net).\n~ Simple Python script to drive the uart via command line in linux (see software details tab above).\n~ TCP/IP to UART bridging is just around the corner using inexpensive external devices.\n\n\ncrossplatform compatible (tested on Xilinx Virtex-5 and Altera Stratix-4 devices). \nTested up to 1 Mbps with a 29.4912 MHz oscillator.\n\n\n## Feeback:\n>> Give comments and feedback using the official core thread on the OpenCores forum:\nforum_thread\n>> Tell us what you do with our core posting an answer in the bug tracker ticket below\nbug_tracker" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - aborga - predmauro name: uart_fpga_slow_control status: FPGA proven svn-updated: Apr 11, 2012 updated: Jul 16, 2012 wishbone-compliant: 0 - category: Communication controller created: Apr 24, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - bentaf name: uart_module_generic status: Empty updated: Apr 24, 2013 wishbone-compliant: 0 - category: Communication controller created: Jun 2, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - gavinux name: uart_plb status: Stable svn-updated: Jun 4, 2011 updated: Jun 3, 2011 wishbone-compliant: 0 - category: Arithmetic core created: May 15, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - shraddhajoshi name: uarts status: Empty updated: May 15, 2013 wishbone-compliant: 0 - category: Processor created: Nov 20, 2005 description: "===== \n Description =====\n\nUCore is a RISC microprocessor compatible of the MIPS32R2 Instruction Set. It can run all the MIPS32R2 instructions except the branch likely instructions. For these instructions are not recommended in the specification. \n The processor has 6 pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Register Fetch (RF), Execution (EX), Memory Access (MEM) and Write Back (WB).\n The processor uses synchronous ram as its Register file, data RAM and instruction RAM, which makes it be easily implemented in both FPGA and ASIC, especially in FPGA.\n The processor\xC2\x81fs instruction set and privilege resource are designed strictly to the \xC2\x81gMIPS32 Architecture for Programmers\xC2\x81h (Volume I-III\xC2\x81CRevision 2.50) specification from MIPS Technologies Inc. \n The processor has been implemented in FPGA and synthesized by Design Compiler using UMC .18 ASIC libraries. When MMU and Caches are disabled, it can run at a speed 150MHz and occupies 3000 LUTs in Xilinx XC2VP30 (using Synplify 8.1 Pro and ISE 7.1i) FPGA; when implemented in Altera EP2C35 (using Quartus 6.0) FPGA, it can run at a speed of 120MHz and occupies 3300 LEs. \n When using a MMU with 64 entries of fully associated TLBs, an 8KB data cache and an 8KB instruction cache, it occupies 13300 LUTs and can run at 46 MHz in XCV4LX160 FPGA.\n According to the synthesis results of Design Compiler, the speed of the processor is 480 MHz and its power consumption is 197.6mW in Virtual Silicon\xC2\x81fs UMC .18 ASIC libraries, occupying 0.466 square millimeter silicon or 23,000 equivalents gates.\n Many programs have been ported to the processor and tested on FPGA. They are uC/OS II, U-Boot, UIP/LWIP, Dhrystone, WEB&NAT server and so on. There are also some small test programs. The first one is an assembly program modified from the Plasma core written by Steve Rhoads, it tests all the instruction of UCore processor. The second and third ones are a 1000bits PI calculation program and a program sorting 10 short integers, which are written in C and compiled using GCC MIPS cross compiler. \n Programs used to test the SDRAM, Flash, SRAM, VGA modules and a program used to download Motorola S-record format binary to the chip from UART are developed and tested, too. You can get detailed information from the Makefile locating in the tool dictionary. \n I have built a system using the processor core. It contains the UCore, a 32k data/instruction on-chip SRAM, a timer, a UART, a SRAM controller, a SDRAM controller, a Nor Flash Controller, a VGA controller and a MAC controller and packet buffer for it. The system has been tested on Altera\xC2\x81fs DE2 board and a Xilinx XC2VP30 FPGA board at 50MHz. All the programs mentioned in the previous section have been successfully run in FPGA.\n I have run the Dhrystone benchmark version 2.1 in the system, and it's score is 141DMIPS when run at 100 MHz. \n I have used GCC 3.2.3 and GCC 4.0.0 cross tool chains to generate the codes, then I translated them to format I need using a Perl script wrote by myself.\n The scripts used to build the GNU tool chain is lying in test/utils dictionary, named build-gcc.sh. You can download the GNU tool chain source and use the script to build a cross tool chain of yourself.\n I have verified the processor carefully. If anyone finds there are bugs in it, please let me know. I\xC2\x81fll fix it as quickly as possible. My email is whitewill@163.com.\n The code can be downloaded from the download section. The URL is http://www.opencores.org/pdownloads.cgi/list/ucore. It\xC2\x81fs an old version of the system. \n The latest version will be uploaded to CVS repository latter.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Fully MIPS32R2 Compatilbe\n- Verified on many FPGA board\n- Confiugrable MMU and Cache modules\n \n\n\n \n \n \n\n===== \n Status =====\n\n- status1\n- status2\n \n\n\n \n \n \n\n===== \n Thanks =====\n\nEmpty block" language: Verilog license: custom licensetext: "This source file may be used and distributed freely without\nrestriction provided that this copyright statement is not\nremoved from the file and any derivative work contains the\noriginal copyright notice and the associated disclaimer.\n\nPlease let the author know if it is used\nfor commercial purpose.\n\nTHIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - whitewill name: ucore status: FPGA proven svn-updated: Mar 10, 2009 updated: Aug 4, 2010 wishbone-compliant: 1 - category: Communication controller created: Feb 9, 2010 description: "===== \n Description =====\n\nVHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication!\n\nAn advanced/versatile version of the core is included in the PC-FPGA Communication Platform project!" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - NikosAl name: udp_ip__core status: Stable svn-updated: Dec 21, 2010 updated: Mar 7, 2014 wishbone-compliant: 0 - category: Communication controller created: Oct 11, 2011 description: "===== \n Description =====\n\nImplements UDP, IPv4, ARP protocols\nZero latency between UDP and MAC layer (combinatorial transfer during user data phase)\nAllows full control of UDP src & dst ports on TX.\nProvides access to UDP src & dst ports on RX (user filtering)\nCouples directly to Xilinx Tri-Mode eth Mac via AXI interface\nchoice of ARPV2 layer with multislot cache, or smaller single slot ARP for point to point implementations\nSeparate building blocks to create custom stacks\nEasy to tap into the IP layer directly\nSeparate clock domains for tx & rx paths\nTested for 1Gbit Ethernet, but applicable to 100M and 10M\nMore detail in doco under Downloads\n- provided by Peter Fall and the FIXQRL project" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - pjf - adrianf0 name: udp_ip_stack status: FPGA proven svn-updated: Apr 18, 2015 updated: Nov 5, 2014 wishbone-compliant: 0 - category: ECC core created: May 5, 2005 description: "===== \n Description =====\n\nUltimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput still benefits from this architecture, as can be seen from the synthesis page.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nExecutes in one clock cycle per data word\nAny polynomial from 4 to 32 bits\nAny data width from 1 to 256 bits\nAny initialization value\nSynchronous or asynchronous reset\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nRevision 1.0 released." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - gedra name: ultimate_crc status: ASIC and FPGA proven svn-updated: Mar 10, 2009 updated: Aug 1, 2013 wishbone-compliant: 0 - category: Other created: Jun 4, 2009 description: "===== \n Description =====\n\nHi,\n Everyone, You can find detailed information about project in this pdf. \n The pdf explains most of the things about the project like:\n 1. Port list for unconfuser.\n 2. Address for each pad.\n 3. Polynomials used for each pad.\n 4. Steps to be followed to code state machine.\n 5. Diagrams briefly explaining confuser and unconfuser working.\n\n Hope this much information would be sufficient to grasp everything about project.\n The project need to be optimized for number of gates, Have 12k count for now need to make it to around 8k. Hope it will be done in 2 weeks :)" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - protik name: unconfuser status: Beta svn-updated: Jul 1, 2009 updated: Jun 23, 2009 wishbone-compliant: 0 - category: Processor created: Feb 23, 2014 description: '' language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jimbrakefield name: up_core_list status: Empty updated: May 28, 2014 wishbone-compliant: 0 - category: Other created: Oct 5, 2004 description: "===== \n Status =====\n\n- Found the old project files and documentation and uploaded to opencores\n- PCB with XC9536XL 90% done, may go into new PCB rev\n- Several configurations have been tested with an prototype \n \n\n\n \n \n \n\n===== \n Description =====\n\nThe goal was to create a set of HDL designs that can convert a small PLD to emulate any JTAG/ISP/Download cable. In most cases those designs are pretty trivial. \n\nAll (almost all) current testing is now done using Chameleon dongle from http://www.amontec.com\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Emulated Cables\n - ByteBlasterMB/II\n - Xilinx Parallel Cable III\n - Atmel ATDH2081\n - Atmel STK200\n - JTAG Wiggler\n - Cypress UltraISR Cable\n - LVTP (Low Voltage Trival PIC Programmer)\n - TI MSP JTAG Cable" language: VHDL license: unknown maintainers: - openchip name: upcable status: FPGA proven svn-updated: Mar 10, 2009 updated: Dec 3, 2004 wishbone-compliant: 0 - category: Communication controller created: Sep 25, 2001 description: "===== \n Description =====\n\nThis is a USB 2.0 compliant core. USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core. A industry standard PHY interface for USB has been developed. This interface is called USB Transceiver Macrocell Interface or UTMI for short. The host interface of the USB core will be WISHBONE SoC compliant. \n\nMore information about the USB standard and a full specification can be found at www.usb.org \n\nMore information about the WISHBONE SoC and a full specification can be found here. \n\nThe UTMI specification (and various other useful USB papers) can be downloaded from here. \n\nFor further information, questions and general discussions related to the USB core, please visit the USB Mailing list. \n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 8/2/2001 New Directory Structure ! We have agreed on a common directory structure at OpenCores. \n- Second release is checked in ! [March 31, 2001] \n - The Core is now configurable \n - Moved buffer memory (SSRAM) outside the core \n - Many small fixes and additions (see usb_doc for more details) \n - This is still a development version, see the doc/STATUS file for the actual status \n - Please do not make any modifications on the sources as I'm still actively working on the core \n - Please submit bugs and comments to the bugtracker\n - PLEASE HELP: I'm still looking for people to help me verify the core \n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: usb status: Stable svn-updated: May 5, 2009 updated: Jul 27, 2013 wishbone-compliant: 1 - category: Communication controller created: May 10, 2004 description: "===== \n Description =====\n\nThis project consists of the translation of the USB 1.1 Function IP Core Verilog code and dependencies, maintained by Rudolf Usselmann, into a Synopsys CoCentric SystemC Compiler compatible SystemC code.\nThis project is part of the BrazilIP Fenix project.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Written In SystemC\n - Synopsys CoCentric SystemC Compiler Compatibility\n - Fully Synthesisable\n- 8051 Interface\n- OCP Interface\n- Test bench is included\n - SystemC code: simulation through binary generated by the gcc\n - Verilog code: simulation through tools like ModelSim or Icarus (the IP Core Verilog files may be generated by CoCentric SystemC Compiler)\n \n \n\n\n \n \n \n\n===== \n Status =====\n\n- The translation is done.\n- It was verified by simulation with OCP Interface (SystemC and Verilog.)\n- It was verified by simulation with 8051 Interface (Verilog.)\n- OCP Interface Protocol under verification.\n- The hardware verification will be made (XILINX XC2V2000.)\n - The XILINX TIMED SIMULATION (Verilog code generated by ISE) in ModelSim is done.\n\xC2\xA0\n \n\n\n \n \n \n\n===== \n Requirements =====\n\n- SystemC v2.0.1\n- g++ or Visual C++ Compilers\n- Synopsys CoCentric SystemC Compiler (optional)" language: SystemC license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - alfoltran name: usb11 status: Stable svn-updated: Mar 10, 2009 updated: Jul 9, 2004 wishbone-compliant: 0 - category: Communication controller created: Feb 10, 2011 description: "===== \n Description =====\n\nThis is a Verilog to VHDL translation of Rudolf Usselmanns USB 1.1 PHY. \nSince the original design operates with a 48 MHz clock and I required a 60 MHz version I added also a modified version with a 60 MHz clock section - the changes are only in file usb_rx_phy_60MHz.vhdl (the unmodified version usb_rx_phy.vhdl is also provided).\nThe design and especial the DLL section has been simulated using the USB 1.1 Simulation model." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - M_artin name: usb11_phy_translation status: FPGA proven svn-updated: Apr 23, 2011 updated: Apr 25, 2013 wishbone-compliant: 0 - category: Communication controller created: Feb 10, 2011 description: "===== \n Description =====\n\nA USB FS Host simulation environment (test bench) in VHDL.\n\nThis USB FS test bench has been used with the Model Sim VHDL Simulator, however 4\nany other 'event driven' VHDL simulator should work as well.\n\nThis test bench contains a 'Command Engine' that supports all 'low level' USB FS commands as\n\n* Out Token Command \n* In Token Command\n* SOF Token Command\n* Setup Token Command\n* Data0 Command\n* Data1 Command\n* ACK Handshake Command\n* NAK Handshake Command\n* STALL Handshake Command\n* USB Reset\n\nSince all USB HS devices must be downward compatible, this FS simulation environment is also \nuseable for USB 2.0 designs. A true USB 2.0 implenentation needs some more work - few USB 2.0 \ncommands as Data2, MData, NYET and PING are already implemented, however the CHIRP logic is \nmissing and a complete new clock logic will be required. \n\nAll commands are implemented as procedure calls, this procedures add the synchronization preamble, \nPIP, its complement, correct bit-stuffing and CRC-5 respective CRC-16 bits in all this cases.\n\nAn independent USB Monitor monitors all bus activities and logs the result on the screen and in a \nResult.out file. \n\nThis monitor detects all USB FS Token, Data and Handshake commands It also adds direction information to distinguish if the commands are initialized from the USB host or the USB device under test.\nDocumentation will be found in the DOWNLOAD section (USB FS TestBench.pdf)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - M_artin name: usb11_sim_model status: Design done svn-updated: Apr 25, 2013 updated: Apr 24, 2013 wishbone-compliant: 0 - category: Communication controller created: Sep 19, 2002 description: "===== \n Description =====\n\nUSB 1.1 slave/device IP core. Default configuration is 6 endpoints:\n1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk\nOut, 1 Interrupt IN. Includes control engine, providing full enumeration\nprocess in hardware - no external micro-controller necessary.\nDerived from my USB 2.0 Function IP core, except all the high speed\nsupport logic has been ripped out and the interface was changed from\nshared memory to FIFO based.\n\nA basic test bench is now included as well. It should be viewed\nas a starting point to write a more comprehensive and complete\ntest bench.\n\nI expect the users of this core to have some fundamental USB knowledge\nand be familiar with the UTMI specification and with the general USB\ntransceivers (e.g. from philips). If you are not familiar with these two\nyou should check out www.usb.org and read up on this subject ... \n \n\n\n \n \n \n\n===== \n Features =====\n\n- USB 1.1 Compliant Function\n- Hardware enumeration support\n- No micro controller/CPU required\n- FIFO based interface\n- Written In Verilog\n- Fully Synthesisable\n- Tested in Hardware \n \n\n\n \n \n \n\n===== \n Status =====\n\nThis core is fully functional and completed.\nIt was verified in hardware in an XESS XCV800 FPGA prototype board.\n- Sept. 25 2002\n - Added a basic test bench\n - Changed Top Level\n\n \n\n\n \n \n \n\n===== \n Dependencies =====\n\nTo use this IP core, you must also download the USB 1.1 PHY , Generic FIFOs and the Generic memories models.\n\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: usb1_funct status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 27, 2012 wishbone-compliant: 0 - category: Communication controller created: Feb 19, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dinesha name: usb2uart status: Planning svn-updated: Apr 20, 2013 updated: Feb 19, 2013 wishbone-compliant: 0 - category: Communication controller created: Sep 19, 2011 description: '' language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - makhtar - dragon_123123 - fordred - gopimos - tipparaj - aeldieb name: usb3 status: Empty updated: Jan 21, 2014 wishbone-compliant: 0 - category: Communication controller created: Mar 26, 2014 description: "===== \n Description =====\n\nA simple full speed USB device core with 4 endpoints.\nComes with virtual COM port demo sw.\n\nMore details to follow." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - ultra_embedded name: usb_device_core status: FPGA proven svn-updated: Mar 27, 2014 updated: Mar 27, 2014 wishbone-compliant: 1 - category: Communication controller created: Dec 7, 2006 description: "===== \n Description =====\n\nMain features of latest v5 HW are:\n\n-LPC memory read (can be disabled),LPC Firmware Hub memory read\nand IO write for POST Code capture (and display on LED segments)\n-POST code peek mode (LPC reads from dongle are disabled)\n-POST code logger (sends all postcodes to USB serial port as hexadecimal bytes in ASCII)\n\nThis is hardware project for existing USB dongle\nboard (costing about 150 EUR you should check from sales(at)artecgroup.com). Using it for LPC dongle.\n \n\n\n \n \n \n\n===== \n IP cores =====\n\n- LPC slave (supporting IO write, Memory read and LPC Firmware Hub read from device ID 0x0000)\n- Flash Waveform generator\n- FTDI parallel interface to onboard flash (supports 32 byte block write and 64K block read)\n- FTDI parallel interface to convert and send bytes as hex codes in ASCII\n- Scanning LED segment display coder\n \n\n\n \n \n \n\n===== \n Status =====\n\n- HW cvs tag HWVersion_1_0 released (HW code 3)\n\n- Software cvs tag SoftVersion_1_1 released (dongle.py script version 1.1)\n\n- HW/Software bundle cvs tag version_1_4 released (bug fixes and added LPC Firmware hub [FWH] read). Contains HW version code 4 and dongle.py script version 2.0\n\n- HW/Software bundle cvs tag version_1_5 released (Added Post code logger hardware, fast block read hardware and fast read flow control hardware. Updated software to support all the new hardware and older HW in legacy mode). Contains HW version code 5 and dongle.py script version 2.5\n\n \n\n\n \n \n \n\n===== \n IMAGE: usb_dongle.jpg =====\n\nFILE: mini_LR_DSC_0016.jpg\nDESCRIPTION: LPC USB dongle\n\n \n\n\n \n \n \n\n===== \n PCB Board =====\n\nhttp://www.artecgroup.com/products/hardware-products/programmable-lpc-dongle.html\n\nCan buy at:\nhttp://artecgroup.myshopify.com/products/programmable-lpc-dongle\n\n- Cyclone FPGA EP1C6T144C8N\n- Serial Platform Flash\n- Intel Strata Flash E28F128 (16MB) in 16 bit mode\n- FTDI parallel to USB bridge FT245BM\n- 4 segment LED display\n\nShort dongle user guide by coreboot.org:\nhttp://www.coreboot.org/Artecgroup_programmable_LPC_dongle\n\n \n\n\n \n \n \n\n===== \n IMAGE: block_diagram.png =====\n\nFILE: block_diagram.png\nDESCRIPTION: Block diagram\n\n \n\n\n \n \n \n\n===== \n Downloads =====\n\nHardware, software and Quartus project bundle for v5 hardware\nhttp://www.opencores.org/cvsget.cgi/usb_dongle_fpga/release/usb_dongle_v5_web_release.zip\n\nDatasheet for v5 hardware\nhttp://www.opencores.org/cvsget.cgi/usb_dongle_fpga/release/dongle_v5_datasheet_ver1_09.pdf\n\nSoftware and datasheet bundle for v5 hardware \nhttp://www.opencores.org/cvsget.cgi/usb_dongle_fpga/release/DongleTool_2_5.zip\n\nALTERA EPCS configuration memory programmer tool (needs python and pyParallel), dongle v5 binary and diagram of ByteBlaster II hardware (older Altera cables like ByteBlaster MV won't work)\nhttp://www.opencores.org/cvsget.cgi/usb_dongle_fpga/release/EPCS_update_tool.zip\n\nLPC Dongle AD67441103 PCB schematic\nhttp://www.opencores.org/cvsget.cgi/usb_dongle_fpga/doc/441103_DONGLE_SCHEMATIC.pdf\n\nLPC Dongle AD67441104 PCB schematic\nhttp://www.opencores.org/cvsget.cgi/usb_dongle_fpga/doc/441104_DONGLE_SCHEMATIC.pdf" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - nuubik name: usb_dongle_fpga status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 27, 2009 wishbone-compliant: 0 - category: Prototype board created: Jul 15, 2010 description: "===== \n Description =====\n\nThe ZTEX USB-FPGA-Module 1.11 is a Spartan 6 FPGA board with USB 2.0 interface, 64 MB DDR-SDRAM and Flash memory.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\n High-Speed (480 MBit/s) USB interface via Mini-USB connector (B-type)\n Cypress CY7C68013A EZ-USB-Microcontroller \n Xilinx Spartan 6 XC6SLX9, XC6SLX16 or XC6SLX25 FPGA \n \n 90 General Purpose I/O's (GPIO):\n \n 82 FPGA GPIO's \n 8 EZ-USB FX2 GPIO's \n \n \n \n 15 special I/O's (SIO): \n \n 4 pins for FPGA configuration via JTAG\n 2 pins for 1 serial ports \n 2 pins I2C interface (2 pins) \n 2 interrupt pins \n 3 timers \n 1 Wakeup pin \n 1 Breakpoint pin \n \n \n \n 64 MByte DDR SDRAM: \n \n 200 MHz clock frequency\n 16 Bit bus width \n Up to 800 MByte/s data rate \n Easy to use hard memory controller included Spartan 6 FPGA with 6 ports. (examples included in SDK) \n \n \n MicroSD socket for standard and high capacity (SDHC) microSD cards (the cards must support the SPI mode) \n 128 Kbit EEPROM memory (can be used to to store the firmware) \n FPGA configuration via USB (no JTAG adapters or other additional utilities required) or from Flash memeory\n\n\n \n\n\n \n \n \n\n===== \n Images =====\n\n\n \n\n\n\n\nSpartan 6 USB-FPGA-Module 1.11 from ZTEX. Click on the image for a larger version.\n \n \n\n\n\n\nBlock diagram of Spartan 6 USB-FPGA-Module 1.11 from ZTEX\n \n \n\n \n\n\n \n \n \n\n===== \n References =====\n\n\n Product Homepage\n ZTEX Wiki\n Schematics (PDF)" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ZTEX name: usb_fpga_1_11 status: Stable svn-updated: Apr 9, 2014 updated: Nov 3, 2011 wishbone-compliant: 0 - category: Prototype board created: Jul 28, 2011 description: "===== \n Description =====\n\nThe ZTEX USB-FPGA-Module 1.15 is a Spartan 6 FPGA LX45 to LX150 board with USB 2.0 interface, 128 MB DDR2-SDRAM and Flash memory. \n \n\n\n \n \n \n\n===== \n Features =====\n\n\n High-Speed (480 MBit/s) USB interface via Mini-USB connector (B-type)\n Cypress CY7C68013A EZ-USB FX2 Microcontroller \n Four Xilinx Spartan 6 FPGA variants: LX45 (XC6SLX45), LX75 (XC6SLX75), LX100 (XC6SLX100) and LX150 (XC6SLX150) FPGA \n \n 99 General Purpose I/O's (GPIO):\n \n 91 FPGA GPIO's \n 8 EZ-USB FX2 GPIO's \n \n \n \n 15 special I/O's (SIO): \n \n 4 pins for FPGA configuration via JTAG\n 2 pins for 1 serial ports \n 2 pins I2C interface (2 pins) \n 2 interrupt pins \n 3 timers \n 1 Wakeup pin \n 1 Breakpoint pin \n \n \n \n 128 MByte DDR2 SDRAM: \n \n Up to 400 MHz clock frequency\n 16 Bit bus width \n Up to 1600 MByte/s data rate \n Easy to use hard memory controller included Spartan 6 FPGA with 6 ports. (see SDK for examples) \n \n \n \n MicroSD socket for extensible Flash memory (standard and high capacity (SDHC) cards, SPI mode support required) \n \n Bitstream loading from Flash to FPGA supported by the Firmware\n Accessible from EZ-USB FX2, from FPGA and from Host software using the SDK\n \n \n \n Fast FPGA configuration using CPLD:\n \n Up to 24 MByte/s via USB\n Up to 2.5 MByte/s from microSD Flash (depends on the speed of the card)\n \n \n Memory mapped IO between EZ-USB FX2 and FPGA\n 128 Kbit EEPROM memory (can be used to store the EZ-USB firmware) \n 2 Kbit MAC-EEPROM: contains a unique non erasable MAC-address \n Heat sink for high performance / high speed applications\n No soldering required: Female pin headers on bottom side (two 2x32 und two 1x23)\n Temperature range: 0-70\xC2\xB0C (-25\xC2\xB0C - 85\xC2\xB0C on request)\n FPGA configuration / programming via USB using the SDK. (No JTAG adapters or other additional utilities required.)\n FPGA configuration / programming from Flash memory \n\n \n\n\n \n \n \n\n===== \n Images =====\n\n\n \n\n\n\n\nUSB-FPGA Module 1.15d with Spartan 6 LX150 (XC6SLX150). Also available with LX45 (1.15a, XC6SLX45), LX75 (1.15b, XC6SLX75) and LX100 (1.15d, XC6SLX100). Click on the image for a larger version.\n \n \n\n\n\n\nBlock diagram of Spartan 6 LX45 to LX150 USB-FPGA-Module 1.15 from ZTEX\n \n \n\n \n\n\n \n \n \n\n===== \n References =====\n\n\n Product Homepage\n ZTEX Wiki\n Schematics (PDF)" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ZTEX name: usb_fpga_1_15 status: Stable svn-updated: Apr 11, 2014 updated: Nov 28, 2012 wishbone-compliant: 0 - category: Prototype board created: May 11, 2009 description: "===== \n Desciption =====\n\nThe ZTEX USB-FPGA-Module 1.2 is a Spartan 3 FPGA board with USB 2.0 interface.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\n Xilinx Spartan-3 XC3S400 FPGA \n High-Speed (480 MBit/s) USB interface via Mini-USB connector\n Up to approx. 300 MBit/s net transfer rate via USB \n Cypress CY7C68013A EZ-USB-Microcontroller \n \n 60 General Purpose I/O's (GPIO):\n \n 52 FPGA GPIO's \n 8 EZ-USB FX2 GPIO's (4 if Flash option is installed) \n \n \n \n 20 special I/O's (SIO): \n \n 6 SIO's for FPGA configuration including JTAG \n 2 serial ports (4 pins) \n I2C interface (2 pins) \n 2 interrupts \n 3 timers \n 1 clock output \n 1 Wakeup pin \n 1 Breakpoint pin \n \n \n FPGA configuration via USB (No JTAG adapters or other additional utilities required.)\n 128 Kbit EEPROM memory can be used to store the firmware)\n Flash memory (optional, can be used to store the Bitstream) \n\n\n \n\n\n \n \n \n\n===== \n Images =====\n\n\n \n\n\n\n\nTop side of the Spartan 3 USB-FPGA-Module 1.2 from ZTEX. Click on the image for a larger version.\n \n \n \n \n\n\n Block diagram of Spartan 3 USB-FPGA-Module 1.2 from ZTEX.\n \n \n \n\n\n \n \n \n\n===== \n References =====\n\n\n Product Homepage\n ZTEX Wiki\n Schematics (PDF)" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ZTEX name: usb_fpga_1_2 status: Stable svn-updated: Aug 11, 2012 updated: Jul 15, 2010 wishbone-compliant: 0 - category: Prototype board created: Jul 29, 2014 description: "===== \n Description =====\n\nUSB-FPGA Module 2.13 is an FPGA Board with Spartan 6 XC6SLX16 FPGA, USB 2.0 controller, 66 MByte DDR SDRAM, Flash, many GPIO's and on-board voltage regulators. \n \n\n\n \n \n \n\n===== \n Features =====\n\n\n USB 2.0 interface with Mini-USB connector (B-type)\n Cypress CY7C68013A EZ-USB FX2 Microcontroller\n Xilinx Spartan 6 XC6SLX16 FPGA (XC6SLX9 and XC6SLX25 on request) \n External I/O connector (consisting in two female 2x32 pin headers with 2.54mm grid) provides:\n \n\t 88 General Purpose I/O's (GPIO) connected to FPGA \n\t 6 General Purpose I/O's (GPIO) connected to EZ-USB FX2 Controller \n\t 6 Special I/O's (SIO) connected to EZ-USB FX2 Controller \n\t JTAG signals \n\t Reset signal \n\t External power (4.5 V .. 16 V) input \n\t 3.3V output \n\t I/O voltage output or input \n \n \n \n 64 MByte DDR SDRAM: \n \n 200 MHz clock frequency\n 16 Bit bus width \n Up to 800 MByte/s data rate \n Easy to use hard memory controller included Spartan 6 FPGA with 6 ports. \n \n \n 128 MBit on-board Flash memory\n \n\t Allows Bitstream loading from Flash to FPGA (up to 6.5 MByte/s) \n\t Accessible from EZ-USB FX2 and from FPGA\n \n \n 128 Kbit EEPROM memory (can be used to store the EZ-USB firmware) \n 2 Kbit MAC-EEPROM: contains a unique non erasable MAC-address and is used to store firmware settings\n On-Board power supply: \n \n 3.3 V: 2000 mA \n 2.5 V: 2000 mA \n 1.2 V; 1000 mA \n \n \n\n \n\n\n \n \n \n\n===== \n Block Diagram =====\n\n\n \n\n\n \n \n \n\n===== \n Images =====\n\n\n \n\t\n\t\n\n\n\tTop side of USB-FPGA Module 2.04b with Spartan 6 XC6SLX16.\n \n \n\t\n\t\n\n\n\tBottom side of USB-FPGA Module 2.04.\n \n \n \n\n\n \n \n \n\n===== \n References =====\n\n\n USB-FPGA Module 2.04 product page\n Overview of Series 2 FPGA Boards\n ZTEX Wiki\n Schematics (PDF)" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ZTEX name: usb_fpga_2_04 status: Planning svn-updated: Jul 31, 2014 updated: Jul 31, 2014 wishbone-compliant: 0 - category: Prototype board created: Apr 10, 2014 description: "===== \n Description =====\n\nUSB-FPGA Module 2.13 is an Artix 7 FPGA Board with USB 2.0 controller, 256 MB DDR3 SDRAM, Flash, many GPIO's and on-board voltage regulators. It's available in 4 variants with different FPGA types: XC7A35T, XC7A50T, XC7A75T and XC7A100T\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n\n Four Xilinx Artix 7 FPGA variants: XC7A35T, XC7A50T, XC7A75T and XC7A100T \n USB 2.0 interface using Cypress CY7C68013A EZ-USB FX2 Microcontroller (100 pin version)\n Four Xilinx Artix 7 FPGA variants: XC7A35T, XC7A50T, XC7A75T and XC7A100T \n External I/O connector (consisting in two female 2x32 pin headers with 2.54mm grid) provides:\n \n 100 General Purpose I/O's (GPIO) connected to FPGA \n JTAG signals \n Reset signal \n External power (4.5 V .. 16 V) input \n 3.3V output \n I/O voltage output or input \n \n \n \n 256 MByte DDR3 SDRAM: \n \n Up to 400 MHz clock frequency\n 16 Bit bus width \n Up to 1600 MByte/s data rate \n Usable with the Xilinx Memory Interface Generator (MIG), examples are included in the SDK\n \n \n 128 MBit on-board Flash memory\n \n Allows Bitstream loading from Flash to FPGA (up to 16.5 MByte/s) \n Accessible from EZ-USB FX2 and from FPGA\n \n \n 128 Kbit EEPROM memory (e.g. used to store the EZ-USB firmware) \n 2 Kbit MAC-EEPROM: contains a unique non erasable MAC-address and is used to store firmware settings\n Fast FPGA configuration via USB using CPLD: up to 24 MByte/s\n On-Board power supply: \n \n 3.3 V: 2000 mA \n 1.8 V: 1000 mA \n 1.5 V: 2000 mA \n 1.0 V; 4000 mA \n \n \n XC7A50T, XC7A75T and XC7A100T variants only: Heat sink for high performance / high speed applications included\n Optional: \n \n Battery to store a key for bitstream encryption \n On-board JTAG connector \n \n \n\n \n\n\n \n \n \n\n===== \n Block Diagram =====\n\n\n\n \n\n\n \n \n \n\n===== \n Images =====\n\nClick on the images for larger versions.\n\n\n\n\n \n\t\n\t\n\n\n\tTop side of USB-FPGA Module 2.13d with Artix 7 XC7A100T FPGA, 256 MB DDR3 SDRAM and USB 2.0 interface.\n \n \n\t\n\t\n\n\n\tUSB-FPGA Module 2.13 with heat sink as delivered with XC7A50T to XC7A100T variants.\n \n \n \n\n\n \n \n \n\n===== \n References =====\n\n\n USB-FPGA Module 2.13 product page\n Overview of Series 2 FPGA Boards\n ZTEX Wiki\n Schematics (PDF)" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ZTEX name: usb_fpga_2_13 status: Stable svn-updated: Apr 11, 2014 updated: Jul 31, 2014 wishbone-compliant: 0 - category: Prototype board created: Nov 25, 2013 description: "===== \n Description =====\n\nAn FPGA Board with the largest Artix 7 XC7A200T FPGA, USB 2.0 controller, Flash memory, 100 GPIO's and on-board voltage regulators. \n \n\n\n \n \n \n\n===== \n Features =====\n\n\n USB 2.0 interface, Mini-USB connector (B-type)\n Cypress CY7C68013A EZ-USB FX2 Microcontroller (128 pin version)\n Two Xilinx Artix 7 FPGA variants: XC7A200T (stock type) and XC7A100T (on request) \n External I/O connector:\n \n Compatible to all Series 2 FPGA Boards \n Consits in 2x32 pin headers on bottom side\n 100 General Purpose I/O's (GPIO) connected to FPGA \n JTAG signals \n Reset signal \n External power (4,5 V .. 16 V) input \n 3.3V output \n I/O voltage output or input \n \n \n 128 MBit on-board Flash memory\n \n Allows FPGA configuration from Flash (up to 16.5 MByte/s) \n Accessible from EZ-USB FX2 and from FPGA\n \n Fast FPGA configuration via USB using CPLD: up to 24 MByte/s\n Memory mapped IO between EZ-USB FX2 and FPGA\n 128 Kbit EEPROM memory (used to store the EZ-USB firmware) \n 2 Kbit MAC-EEPROM: contains a unique non erasable MAC-address and stores firmware settings\n On-Board power supply: \n \n 3.3 V: 2 A \n 1.8 V: 1 A \n 1.0 V: 14 A (sufficient for high performance applications)\n \n \n Heat sinks (two types) for high performance / high speed applications included \n Optional: \n \n Battery to store a key for bitstream encryption \n On-board JTAG connector \n \n \n\n\n \n\n\n \n \n \n\n===== \n Block Diagram =====\n\n\n\n \n\n\n \n \n \n\n===== \n Images =====\n\nClick on the images for larger versions.\n\n\n\n\n \n\t\n\t\n\n\n\tTop side of USB-FPGA Module 2.16b with Artix 7 FPGA XC7A200T.\n \n \n\t\n\t\n\n\n\tUSB-FPGA Module 2.16 with active cooler. A heat sink kit containing an active and a passive cooler belongs to the contents of delivery of the FPGA Board.\n \n \n \n\n\n \n \n \n\n===== \n References =====\n\n\n USB-FPGA Module 2.16 product page\n Overview of Series 2 FPGA Boards\n ZTEX Wiki\n Schematics (PDF)" language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - ZTEX name: usb_fpga_2_16 status: Stable svn-updated: Feb 5, 2014 updated: Jul 31, 2014 wishbone-compliant: 0 - category: Communication controller created: Feb 16, 2012 description: "===== \n Description =====\n\nUSB2.0 keyboard,UTMI or ULPI interface,by using LZJ USB core.\nThe source link is http://cache.ourdev.cn/bbs_upload587234/files_50/ourdev_713391VDCJQO.rar.\nEmail: chengjun0356@163.com" language: Verilog & VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - beichengjun name: usb_keyboard status: Empty updated: Feb 16, 2012 wishbone-compliant: 0 - category: Communication controller created: Sep 16, 2002 description: "===== \n Description =====\n\nVery simple USB 1.1 PHY. Includes all the goodies: serial/parallel\nconversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a\nsimplified UTMI interface. Currently doesn't do any error checking in\nthe RX section (should probably check for bit unstuffing errors).\nOtherwise complete and fully functional.\n\nThere is currently no test bench available. This core is very simple\nand is proven in hardware. I see no point of writing a test bench at\nthis time. \n\nI expect the users of this core to have some fundamental USB\nknowledge and be familiar with the UTMI specification and with the\ngeneral USB transceivers (e.g. from philips). If you are not familiar\nwith these two you should check out www.usb.org and read up on\nthis subject ...\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- FPGA or ASIC implementation possible\n- 8 bit wide unidirectional UTMI interface\n- serial parallel conversion\n- bit stuffing/unstuffing\n- NRZI encoding/Decoding\n- DPLL\n- Implemented in Verilog\n- Fully synthesizable (runs well over the required 48MHz in a Spartan II)\n- Very small: 111 LUTs (7%) of Spartan II XC2S50\n \n\n\n \n \n \n\n===== \n Status =====\n\nThis core is fully functional and completed.\nIt was verified in hardware in an XESS XVC800 FPGA prototype\nboard with an USB 1.1 IP core I have written.\n\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: usb_phy status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 31, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Apr 28, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dingyj name: usb_uvm_verification status: Empty updated: Apr 28, 2013 wishbone-compliant: 0 - category: Communication controller created: Sep 30, 2004 description: "===== \n Status =====\n\nVersion 2.0 is now available. \n\nDesign has been tested in simulation and hardware.\n\nTo do. Still need to test isochronous mode, pre-amble mode, and all host mode features related to accessing a low speed device via a hub. \nSynthesizable under Quartus 7.2 SP3. Uses approximately 2700 logic cells in an Altera Cyclone EP2C20.\n\n\"Works like a champ for me. Thank you. I did a PHY card for a Digilent Nexys2 board using a MAX8586 switch and a Philips SP1301 OTG PHY. I've used it in both Host and Device mode with no problems whatsoever.\" \n- Mike Kentley http://www.hddcinc.com\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nUSBHostSlave is a USB 1.1 Host and Function IP core. It supports full speed (12Mbps) and low speed (1.5Mbps) operation, and supports the four types of USB data transfer; control, bulk, interrupt, and isochronous transfers. USB Function has four endpoints, each with their own independent FIFO. All FIFO depths configurable via parameters. It has a 8-bit Wishbone slave bus interface.\n\nAll the state machines have been designed using ActiveHDL FSM2HDL, so they are easily readable and understandable, but it is still possible to edit the Verilog RTL if so desired. Graphical state diagrams are used because they are much easier to understand than just RTL source code. Graphical state diagrams ease creation, maintenance, documentation, and re-use, of FSMs. Aldec ActiveHDL is an excellent tool for creating graphical state diagrams, only requiring a single .asf file per state machine module. This makes it easy to maintain the FSMs and incorporate them into your existing text based module hierarchy.\n\nFor those who are targeting Altera FPGAS, there is a complete Quartus project for usbDevice. The project has been tested on an Altera development board, and requires a custom Santa Cruz daughter card. See downloads section for full schamatics and bill of materials.\n\nhttp://www.opencores.org/pdownloads.cgi/list/usbhostslave\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- USB 1.1 Host and Function\n- Full and low speed.\n- Control, bulk, interrupt, and isochronous transfers\n- FIFO interface\n- FIFO depth configurable.\n- Automatic SOF generation\n- 8-bit Wishbone interface\n\n \n\n\n \n \n \n\n===== \n Known Issues =====\n\nBus-turn-around time is compliant with low speed, but not full speed USB 1.1 specification. The USB 1.1 spec requires host or device to provide a response within 6.5 bit times in both full and low speed modes. Operating with a system clock of 48Mhz, usbhostslave currently provides a response within 1uS (12 full speed bit periods, 1.5 low speed bit times). \n\nThe USB 1.1 specification takes into account the worst case system configuration of 5 cascaded hubs, and 6 maximum length cables (see figure 7-31 in USB 1.1 spec), resulting in a worst case system bus-turn-around time of 16 full speed bits. So, operating with a system clock of 48MHz, usbhostslave will be within full speed system spec for 2 cascaded hubs, and 3 maximum length cables. Increasing clock speed to 96MHz would make the core USB 1.1 compliant.\n \n\n\n \n \n \n\n===== \n USB PHY daughter card =====\n\nA USB PHY daughter card compatible with usbhostslave is available;\nhttp://www.base2designs.com/DUSB-PHY.htm\nSanta Cruz format daughter card that supports many development kits from Altera and Microtronix.\n \n\n\n \n \n \n\n===== \n News =====\n\nNow available, Linux driver patch files for Linux 2.6.22 and 2.6.28. Thanks to Mario Becroft and Julian Vetter." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - sfielding name: usbhostslave status: FPGA proven svn-updated: Mar 18, 2011 updated: Aug 8, 2013 wishbone-compliant: 1 - category: Processor created: Mar 9, 2011 description: "===== \n Description =====\n\nThis project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows\nsimulate and synthetize the Simplez processor. It is a didactic processor created by\nGregorio Fern\xC3\xA1ndez in his book \"Conceptos B\xC3\xA1sicos de Arquitectura y Sistemas Operativos\",\n2003 Edition.\n\nThis theoretical processor has a von Neuman architecture, with a set of eight instructions\nand 512 memory words. Each twelve bits word, contains two fields: operation code and\ndata address. Basically, Simplez repeats cyclically the next three steps:\n\n- Reads the instruction stored in a main memory's address.\n- Decodes the instruction and executes it.\n- Generates the address in the main memory of the next instruction." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - peraltahd - monteromrtn - Julyan name: usimplez status: FPGA proven svn-updated: Nov 9, 2011 updated: Nov 11, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Sep 13, 2014 description: "===== \n Description =====\n\nI have NI USRP-2932 which is national instrument product. It is interface device between analog(RF) and Digital(Host) System. It contains ADC,DAC,DDC,DUC and FPGA for signal processing. It has LAN interface port which is using Gbit Ethernet. Now I have to do two things either re-program internal FPGA or Interface this device with External FPGA. Once this things happen we can perform lots of application on this." language: Verilog & VHDL license: unknown maintainers: - bhavikav name: usrp_interfacing status: Empty updated: Sep 16, 2014 wishbone-compliant: 0 - category: Other created: Feb 25, 2010 description: "===== \n About the uTosNet project =====\n\nuTosNet (pronounced microTosNet) is developed at the University of Southern Denmark ( http://www.sdu.dk ), and is intended to:\n\nReduce the development time of experimental robotic controllers to arrive faster and cheaper at fully working demonstrations of new technology and concepts.\n\nIncrease the reusability of experimental systems and components, thus increasing the life-span and utilization of these, and reducing the amount of redundant work.\n\nEase the use of interacting with experimental low-level controller, to open experimental robotics up to a wider audience, and to allow high-level developers a tighter integration with the physical robots, without involving them in the low-level particulars of embedded systems.\n\nUntil now uTosNet has only been used inhouse for a number of projects. We would very much like to get feedback, opinions, ideas and comments from others though - anything will be appreciated!\n\nAlso have a look at TosNet for the full-blown, multi-node version of TosNet.\n\n - Simon Falsig\nUniversity of Southern Denmark\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC.\nThe framework is based on the Node-on-Chip architecture (link to paper coming).\n\nIt works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access from the PC (through uTosNet) and the other port exposed to access from user-defined modules. This allows easy and generic storage of process variables.\n\nCurrently two versions of uTosNet are supported:\n\nPC side USB converter chip UART FPGA\nPC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA\n\n\nNote that the UART version does NOT include an implementation of a UART. It has however been prepared for use with the UART implementation from the PicoBlaze processor, which is available as a free download from Xilinx here.\n \n\n\n \n \n \n\n===== \n Currently available on SVN =====\n\nCurrently, the following files are available for download from the project SVN server:\n\n\nDocumentation:\n\nuTosNet userguide\nEmbedix Spartan3AN-50 documentation\n\nGateware:\n\nFPGA-side code for uTosNet (except the uart functionality itself)\nUSB/RS232 example\nEthernet/SPI example\nuTosNet UART controller example \n\nHardware:\n\nPCB design files for a very simple FPGA board based on the Spartan3 50AN, and an add-on board with extra connectors, leds, the USB/UART converter chip and the Digi Connect ME 9210 module.\n\nSoftware:\n\nA simple commandline application for use with the Ethernet/SPI version (a simple terminal emulation program, such as PuTTY or HyperTerminal, can be used with the USB/UART version)\nC++ source code for the Ethernet version, for use with the Digi ME 9210" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - sonicwave name: utosnet status: FPGA proven svn-updated: Aug 29, 2011 updated: Aug 26, 2011 wishbone-compliant: 0 - category: Processor created: Oct 12, 2014 description: "===== \n Description =====\n\nThis project is a soft processor core compatible with 586 instruction set.\nIt has been developped on Nexys4 board, with Artix7-100 FPGA with external SRAM and SPI flash.\nThe project contains the core and also a platform to demonstrate the core with interfaces for\nexternal 16MB SRAM and 128Mbit SPI Flash.\nThe platform boots linux kernel with a ramdisk contained in the SPI flash.\nThe processor core has wishbone interface.\n\n** CORE DETAILS:\n\n* Features:\n- 586 instruction set implementation, conditional mov added.\n- MMU with protected and paged mode supported with 4KB page size.\n- TLB 8 entries\n- CPUID (0x0617)and CMPXCHG8B are implemented, with conditional mov.\n- pre-fetch queue is 32 bytes long.\n- 8kB Instruction cache, 8kB Data cache, 128bit loaded at once into prefetch queue.\n- Hardware multiplication and Division\n- 32 bit wishbone interface with bursts.\n- ~16000 dhrystones v2.1 @ 75MHz with -O2 option under gcc 4.6.2, no register, around ~ 9 VAX MIPS. \n\n* Known limitations:\n- no FPU, but emulation mechanism with \"device not available\" fault #7.\n- some instruction are missing, but not used in Linux/GCC : like the decimal adjust.\n- Protected and Paged mode are supported, there are some limitation in the protected \nmode implementation like segment limit.\n- bits and features for MSR/TSC/PAE/NX bit not implemented.\n- MMU page size is 4KB , no PSE / PSE36 bit supported\n- Segment prefix in protected mode are the default or GS descriptor, FS prefix\n in protected mode is not used in Linux 32b.\n\n**PLATFORM DETAILS:\nHARDWARE:\n- Minimal set of peripherals : timer and interrupt controller.\n- one 16750 interface with 64byte fifo , re-used from uart16750 opencore project.\n- IT87xx SuperIO chip implemented only for GPIOs parts. 16x GPIOs Connected to leds of nexys4.\n ( GPIO Linux driver fot IT87 compatible with userspace interface. )\n- SPI interface serial-in , parallel out\n- Bus Interface Unit to arbitrate between instruction fetch and data operations and\n also MMU specific operation like updating the bit for page directory/table entries.\n- The Platform mapping in the Artix7-100 fills 42% and clock frequency used in the project is 75MHz \n- clock divider for timer and uart are hard coded for 75MHz base clock.\n\nSOFTWARE:\n- internal ROM to boot and copy SPI flash into RAM, provide minimal description\n and configuration for Linux with command line to configure TTY console on uart\n at 115200 baud.\n- SPI image with Linux 3.19 ( 3.17/3.14/3.12/2.6.x were tested as well) and initramfs\n with busybox built from buildroot 2015.02 with dhrsytone/whetstone utilities.\n- Kernel has been built on regular PC UBUNTU 14.04LTS with regular GCC as well.\n- .config file for the kernel included, settings optimized for size and FPU emulation on.\n- testbench and script to run under verilator simulator\n\n** CODE\n- Structural Verilog with description in technology independent gates.\n- Routing of such structure on FPGA is fast.\n\n********** USEFUL NOTICE\nnotice: you need on nexys4 board to put SW1 and SW2 ON while SW0 is reset.\notherwise SW1-SW2 sets test modes.\n\ntoggle SW0 to reset/start the fpga.\n \n\n\n \n \n \n\n===== \n Links =====\n\nMore versions of the core are also available on www.valptek.com\n\nFor instance evolutions with :\n- different cache configurations and size\n- optimization for lower area\n- customizable/extendable instruction set for supporting custom vector opcodes.\n- dual core versions\n\nvideos on youtube can be found here : https://www.youtube.com/channel/UCNbm8Bah54cwhedmCRWyXMA/videos\n \n\n\n \n \n \n\n===== \n Support =====" language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - ultro name: v586 status: FPGA proven svn-updated: May 7, 2015 updated: May 7, 2015 wishbone-compliant: 1 - category: Other created: Mar 22, 2013 description: "===== \n Description =====\n\nVectorial generator:\n\n-Interface: bit or bus\n-Configuration: dynamic\n-Applications: waveform generator, serial or parallel communication\n\nExamples:\n\n-Included in the own .vhd headfile\n\nConfiguration:\n\n-It is necessary to adjust the following type which defines the input size (it affects to area resources):\n\n SUBTYPE valores_vector IS INTEGER RANGE -1 TO nat_synth_65536'high; -- values range for each sample (always from -1) \n TYPE vector_integer IS ARRAY (nat_synth_128'high DOWNTO 0) OF valores_vector; -- number of samples*2\n\nwhere:\n\n SUBTYPE nat_synth_65536 IS NATURAL RANGE 0 TO 65535;\n SUBTYPE nat_synth_2048 IS NATURAL RANGE 0 TO 2047;\n(...) \n SUBTYPE nat_synth_16 IS NATURAL RANGE 0 TO 15;" language: VHDL license: unknown maintainers: - arroxo2 name: vectorial_generator status: FPGA proven svn-updated: Mar 31, 2014 updated: Mar 31, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Sep 14, 2008 description: "===== \n Description =====\n\nA 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details. Source and user manual available here\n \n\n\n \n \n \n\n===== =====\n\n\n \n\n===== \n Status =====\n\n- Tested in hardware" language: Verilog license: unknown maintainers: - daledrinkard name: verilog_cordic_core status: FPGA proven svn-updated: Mar 10, 2009 updated: Aug 12, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Jan 3, 2014 description: "===== \n Synopsis =====\n\nVerilog Fixed point math library \n\n\n\n\n\nOriginal work by Sam Skalicky, originally found here\n\n\n\n\n\nExtended, updated, and heavily commented by Tom Burke\n\n\n\n\n\nThis library includes the basic math functions for the Verilog Language, \nfor implementation on FPGAs.\n\n\n\n\n\nAll units have been simulated and synthesized for Xilinx Spartan 3E devices\n using the Xilinx ISE WebPack tools v14.7\n\n\n\n\n\nThese math routines use a signed magnitude Q,N format, where N is the total \nnumber of bits used, and Q is the number of fractional bits used. For instance, \n15,32 would represent a 32-bit number with 15 fractional bits, 16 integer bits, \nand 1 sign bit as shown below:\n\n\n\n\n\n\n\n\n|1|<- N-Q-1 bits ->|<--- Q bits -->|\n|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|\n\n\n\n\n\n\n\n\n\nThis library contains the following modules:\n\n\nqadd.v - Addition module; adds 2 numbers of any sign.\nqdiv.v - Division module; divides two numbers using a right-shift and \n subtract algorithm - requires an input clock\nqmult.v - Multiplication module; purely combinational for systems that \n will support it\nqmults.v - Multiplication module; uses a left-shift and add algorithm - \n requires an input clock (for systems that cannot support \n the synthesis of a combinational multiplier)\nTest_add.v - Test fixture for the qadd.v module\nTest_mult.v - Test fixture for the qmult.v module\nTestDiv.v - Test fixture for the qdiv.v module\nTestMultS.v - Test fixture for the qmults.v module\n\n\n\n\n\n\n\nThese math routines default to a (Q,N) of (15,32), but are easily customizable \nto your application by changing their input parameters. For instance, an \nunmodified use of (15,32) would look something like this:\n\n\n\n\n qadd my_adder(\n .a(addend_a),\n .b(addend_b),\n .c(result)\n\t );\n\n\n\n\nTo change this to an (8,23) notation, for instance, the same module would be \ninstantiated thusly:\n\n\n\n\n qadd #(8,23) my_adder(\n .a(addend_a),\n .b(addend_b),\n .c(result)\n\t );" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tomburkeii name: verilog_fixed_point_math_library status: FPGA proven svn-updated: May 26, 2014 updated: Oct 30, 2014 wishbone-compliant: 0 - category: Other created: Oct 10, 2008 description: "===== \n Overview =====\n\nVeristruct is an an IEEE1364.1995 preprocessor that adds some C-style struct support to the Verilog language. It takes as input Veristruct files (with a .vs extension) and struct definition files (with a .struct extension). It outputs standard Verilog files (with a .v extension). Veristruct files are, for the most par t, standard Verilog files\xE2\x80\x94but, as well as the normal nets and regs, bundled, hierarchical variables can be declared and used. \nVeristruct can process one veristruct file per invocation (which may include many .struct struct definition files). \nVeristruct is written in object oriented Perl. Please feel free to fix any bugs you find!\n\nVeristruct outputs IEEE1364.1995 compliant .v files. Structs declarations are expanded into their elements, and struct element references are expanded into formally compliant variable names. Double underscores are used to indicate depth. When entire structs are referenced (instance names are used without element references) a guess is made as to what is desired. In sensitivity lists and module por t lists, the name is exploded into its constituent elements (and appropriate \nseparator tokens are added). In module instance por t lists, it is assumed that the module being instantiated has multiple ports with the instance name as the base (that will be the case if the module was written in Veristruct).\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Implement c-like Structs in Verilog\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Working with certain limitations.\n\nThe following limitations currently exist within Veristruct: \n- Namespace collisions not detected: Veristruct currently does no checking for namespace collisions. If you don\xE2\x80\x99t use double underscores in your variables names, though, you should be fine. \n- Limited lvalue support: Slices of some struct elements (and whole structs, in most contexts) cannot be lvalues. Veristruct will return an error when it encounters these. \n- Structs can only be declared in .struct files: This is a deliberate limitation. It avoids polluting the Verilog syntax even more. \n- \xE2\x80\x98ifdefs ignored: Because Veristruct is not designed to replace the normal Verilog preprocessor, it does not do its job. As such, you will need to ensure that do not rely on your structs being conditionally included using normal pre-processor directives. There are many ways around this. Ranges in structs can be tick defined, and variable declarations can be surrounded in \xE2\x80\x98ifdefs, which will get honoured later." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - julius name: veristruct status: Mature svn-updated: Aug 24, 2009 updated: Aug 24, 2009 wishbone-compliant: 0 - category: Arithmetic core created: Mar 27, 2009 description: "===== \n Description =====\n\n\n\n\n\n\n\n\nA versatile counter that can be defined as a binary, gray or LFSR counter. Usage include baudrate generator, address generator for FIFO and much more.\n\n \n\n\n\n\n\n\nAs a user you edit a define file to make the counter fit your project demands. You the generate a tailored counter. The performance and area can hereby be optimezed for the given application\n\n\n\n\n\n\n\nPros and cons with different types of counter\n\n\nLFSR\n\nextremely low area usage\nhigh performance\none cycle shorter count cycle compared to binary versions\ntypically used for interval timer and as adress generator for FIFO\n\n\nBinary\n\nThe standard type, usefule for various types of implementation\n\n\nGray\n\nThe Gray type counter toggles only one bit per update\nImplemented as a normal binary counter with an extra output stage converting the state to Gray encoding\nTypical usage is adress generator for asynchroinous FIFOs\n\n\n\n\n\n\n\n\n\n\nThis module is written in Verilog and uses pre processor commands." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback name: versatile_counter status: FPGA proven svn-updated: Jan 27, 2011 updated: Jul 14, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Feb 5, 2014 description: "===== \n Description =====\n\nThis project implements a simple parametrized FFT engine. \nThe user may define length of FFT (fftlen equal to a power of 2), and may also define the format of numbers used.\nTo change the format of numbers, the user must change definition of the icpx_number (internal complex number) type defined in the icpx_pkg.vhd file.\nIt is also necessary to adjust the conversion functions defined in this file.\nThe user must also modify the butterfly.vhd file, so that the entity \"butterfly\" performs calculations on the user defined type.\n\nThere are two implementations available.\n\nIn the first one (in single_unit directory), all calculations are performed by a single \"butterfly block\".\n\nIn the second one (in multiple units directory), there is one \"butterfly block\" for each stage of the\nradix-2 implementation. Therefore the calculation is performed much faster.\nAdditionally this implementation allows to calculate FFT on a stream of data with\noverlapping blocks. New FFT is calculated after next block of input data with length of fftlen/2 is read.\nIn this implementation also the window function may be used to limit the spectral leakage.\n\nBoth implementations rely on known latency of the \"butterfly\" block.\nIn the first implementation it is defined by the constant BTFLY_LATENCY in the fft_engine.vhd file.\nIn the second implementation it is defined by the constant MULT_LATENCY in the fft_engine.vhd file, and additionally\nit is used as a latency of the multiplier multiplying the data by the window function).\n\nIt is assumed, that butterfly block (and the multiplier in the second implementation) work in a pipeline mode\n(so new data may be delivered to the input every clock pulse, and the results are output after the known latency.\n\nThe single_unit implementation to speed up processing, uses two DPRAMs for data. \nIt allows to read both input data for the \"butterfly block\" simultaneously, and to write both results simultaneously.\nWhen the engine completes calculations, the results may be read from the output, and simultaneously the new data may be written to the output (it is granted that different DPRAMs are used for input and output).\n\nThe multiple_units implementation uses DPRAMs in \"read before write\" configuration, to allow simultaneous operation of all\nstages of the radix-2 FFT.\n\nThe design is prepared for simulation with ghdl.\n\nThe script \"test_fft.m\" may be run in Octave (probably also in Matlab) to check, that the core works correctly. \nIt configures the core for selected FFT length, generates the test data, compiles and runs the simulation and displays comparison between the results calculated with floating point FFT and results calculated by the simulated core.\nThe implementation of the \"butterfly block\" is not optimal (e.g. it lacks proper rounding) and therefore there may be small differences between those values.\n\nFor simulation you need the following free software packages:\nghdl ( http://ghdl.free.fr )\noctave ( http://www.octave.org )\n\nYou may also install gtkwave, to view internal signals (simulation may generate the .ghw file for gtkwave).\n\nThe code is synthesizable. It has been successfully synthesized with ISE toolkit from Xilinx.\n\nFor FFT length of 256 (LOG2_FFT_LEN=8) and complex numbers with 16-bit real and imaginary parts (ICPX_WIDTH=16), the resources consumption is as follows:\n\nFor the single_unit implementation:\nFor chip xc3s500e:\n\n Number of BUFGMUXs 1 out of 24 4%\n Number of MULT18X18SIOs 4 out of 20 20%\n Number of RAMB16s 2 out of 20 10%\n Number of Slices 825 out of 4656 17%\n\nFor chip xc6slx45:\n\n Number of RAMB16BWERs: 2 out of 116 1%\n Number of DSP48A1s: 4 out of 58 6%\n Number of Slice Registers: 58 out of 54,576 1%\n Number of Slice LUTs: 475 out of 27,288 1%\n Number of occupied Slices: 188 out of 6,822 2%\n Number of MUXCYs used: 92 out of 13,644 1%\n Number of LUT Flip Flop pairs used: 477\n\nFor the multiple_units implementation:\n\nFor chip xc6slx45:\n\n Number of RAMB16BWERs: 12 out of 116 10%\n Number of RAMB8BWERs: 2 out of 232 1%\n Number of DSP48A1s: 40 out of 58 68%\n Number of Slice Registers: 1,258 out of 54,576 2%\n Number of occupied Slices: 683 out of 6,822 10%\n Number of MUXCYs used: 764 out of 13,644 5%\n Number of LUT Flip Flop pairs used: 1,838\n\nAll my sources in this project are published under the BSD license. You can use them and modify them, however you should keep the\ninformation about the original author.\n\nI don't know whether my IP core infringes any patents. If you want to use it for commercial purposes, you should check it yourself.\nI also don't know if my IP core works correctly in all possible conditions. I provide it \"AS IS\" without any warranty.\nYou use it on your own risk!" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - wzab name: versatile_fft status: Beta svn-updated: Mar 24, 2015 updated: Mar 24, 2015 wishbone-compliant: 0 - category: Memory core created: Mar 31, 2009 description: "===== \n Introduction =====\n\n\n\n\n The FIFO implementation outlined in this document can easily be configured to suit the following \n\n\n\n\nasynchronous FIFO with different clock domains for read and write sides\nsynchronous FIFO with programmable flags\nmultiple FIFO sharing the same memory resource\n\n\n\n\nThis FIFO can easily be extended to have common wishbone interface for all individual FIFO channels." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback name: versatile_fifo status: FPGA proven svn-updated: Nov 4, 2010 updated: Feb 11, 2014 wishbone-compliant: 0 - category: Communication controller created: Mar 31, 2009 description: "===== \n Overview =====\n\n\n\n\n\n\nThis is a modular IO component. With this modular IP design tou can get multiple (by default up to 8) IO channels. Each channel has a RX and TX FIFO with depth 31 bytes. The FIFO is based on the Versatile FIFO also available from OpenCores. All IO channels have a common bus interface compatible with 16550 UART. This makes software integreation easier\n\n\n\n\n\n\nThis IP support many different types of IO\n\n16550 compatible UART\nLED control\nRGB LED control\nRC5 compatible IR receiver\n\nOther can be added" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback name: versatile_io status: Planning svn-updated: Oct 26, 2011 updated: Apr 23, 2009 wishbone-compliant: 1 - category: Library created: Sep 1, 2010 description: "===== \n Description =====\n\nA Verilog HDL library with frequently used functions. Care have been taken to fully support synthesis of all modules. Different versions exist for optimal synthesis support. Currently ACTEL and ALTERA are supported" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback name: versatile_library status: Alpha svn-updated: Dec 8, 2011 updated: Sep 14, 2010 wishbone-compliant: 0 - category: Memory core created: Jun 18, 2009 description: "===== \n Overview =====\n\nThis is a modular memory controller supporting different types of memories. Initial design will have support for SDR SDRAM. Upcoming releases will add support for DDR SDRAM and possibly other variants as well\n\n\n\n\n\n\n\nThe design is built with the following modules\n\nWishbone interface\nDual async FIFO buffers\nSpecific memory controller\n\n\n\n\n\n\n\n\nWishbone interface\nThe wishbone interface supports up to 8 independent interfaces where 4 are high priority real time ports\n\n\n\n\n\n\n\nDual async FIFO buffers\nThis design uses up to 8 outgoing and up to 8 incoming FIFO queues. On the outgoing channels control and data are transmitted and on the incoming read data is received. These are async FIFO supporting different clock domains for wishbine and memory side. FIFO implemenation is based on versatile_FIFO found on OpenCores.\n\n\n\n\n\n\n\nSDR SDRAM controller\nA state machine is used for communication to/from memories." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - unneback - mikaeljf - julius name: versatile_mem_ctrl status: Planning svn-updated: Aug 11, 2011 updated: Nov 4, 2010 wishbone-compliant: 1 - category: Other created: Nov 28, 2008 description: "===== \n Description =====\n\nAn implementation of the Vector Graphic, Inc. Computer System of the early 1980's on a Xilinx Spartan 3E Starter Kit. The Vector ZCB and FlashWriter II video card are implemented. The system also includes a memory management unit, serial ports, and keyboard interface. This design is based on several cores from OPENCORES.ORG.\n\nYou can see some pictures of it running on my blog.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Vector ZCB CPU Card\n - Uses OpenCores Wishbone High-Performance Z80 CPU Core\n - Can optionally use the OpenCores TV80 CPU Core if the wb_tv80 Wishbone wrapper is used.\n - Vector Graphic MON4.3 monitor stored in block RAM.\n - Two UARTs (Compatible with Vector Monitor)\n - PS/2 Keyboard interface to emulate the original parallel ASCII keyboard.\n- Flashwriter II Video Card\n - Uses OpenCores Monochrome Text-Mode VGA Video Display Adapter with custom Wishbone wrapper and original fonts from the Vector Graphic Flashwriter II. Display size changed to 80x24 to match the Flashwriter II.\n- Vector HD/FD Disk Controller\n - Uses StrataFLASH on Spartan 3E Board for storage.\n - Read-Only\n- Other\n - Memory Management Unit\n - Uses OpenCores Asynchronous DDR SDRAM controller\n- Wishbone backplane created using a modified version of OpenCores WISHBONE Builder\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Dec 15, 2008 Update\n - Made UARTs compatible with Bitstreamer Card\n - Can select either Mon 4.0C (serial) or Mon 4.3 (Flashwriter2) Monitor.\n - Can boot CP/M using Mon 4.0C. this allows logging of console output.\n - Fixed shifted keys bug in ASCII Keyboard. CTRL and Arrow keys not working.\n - Fixed first character of each line corruption in Flashwriter2.\n- Dec 7, 2008 Update\n - Can boot CP/M 2.2 from Vector HD-FD controller.\n - Ran exz80all.com instruction set exerciser. Some test failures.\n - DDR Controller commented out, replaced with block RAM where possible:\n - New memory map: 0-2FFF, B000-FFFFh RAM, enough for CP/M with 12K TPA.\n - Running CP/M Exposes some PS/2 Keyboard bugs with shifted and CTRL characters.\n- Tested on Spartan 3E Starter Kit\n- Z80 Core, MMU, Flashwriter II, keyboard interface, UART working\n- DDR SDRAM Controller has problems in this design and needs debugging. The RAM data retention seems fine, but I think the cache has an issue. The memr.com program can be run under CP/M to provide a thorough memory test.\n- Can run the Vector Monitor 4.3 (Flashwriter for I/O) and Monitor 4.0C (Serial I/O)" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hharte name: vg_z80_sbc status: Alpha svn-updated: Mar 10, 2009 updated: Dec 29, 2008 wishbone-compliant: 1 - category: Video controller created: Sep 25, 2001 description: "===== \n Description =====\n\nThe OpenCores VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost all available LCD and CRT displays\n\nThe core supports a number of color modes, including 32bpp, 24bpp, 16bpp, 8bpp gray-scale, and 8bpp-pseudo color. The video memory is located outside the primary core, thus providing the most flexible memory solution. It can be located on-chip or off-chip, shared with the system\xE2\x80\x99s main memory (VGA on demand) or be dedicated to the VGA system. The color lookup table is, as of core version 2.0, incorporated into the color-processor block.\n\nPixel data is fetched automatically via the Wishbone revB.3 Master interface, making this an ideal \xE2\x80\x9Cprogram-and-forget\xE2\x80\x9D video solution. More demanding video applications like streaming video or video games can benefit from the video-bank-switching function, which reduces flicker and cluttered images by automatically switching between video-memory pages and/or color lookup tables on each vertical retrace.\nThe core can interrupt the host on each horizontal and/or vertical synchronization pulse. The horizontal, vertical and composite synchronization polarization levels, as well as the blanking polarization level are user programmable. \n\n \n\n\n \n \n \n\n===== \n IMAGE: block_diagram.gif =====\n\nFILE: block_diagram.gif\nDESCRIPTION: \n\n \n\n\n \n \n \n\n===== \n Features =====\n\nCRT and LCD display support\n24bit Standard VGA interface\nSeparate VSYNC/HSYNC and combined CSYNC synchronization signals\nComposite BLANK signal\nTripleDisplay support\n12bit Interface\nCompatible with DVI transmitters and 12bit VGA ADCs\n4 different output modes\nCan be used simultaneous with the 24bit interface\nUser programmable video resolutions \nUser programmable video timing\nUser programmable video control signals polarization levels\n32bpp, 24bpp and 16bpp color modes\n8bit gray-scale and 8bit pseudo-color modes\nSupports video- and/or color-lookup-table bankswitching during vertical retrace\n32bit WISHBONE revB.3 compliant slave and master interfaces\nOperates from a wide range of input clock frequencies\nStatic synchronous design\nFully synthesizeable \nSee the on-line documentation (current revision 1.2) for more information.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- VGA/LCD core v2.0 is ready and available in verilog from OpenCores CVS via cvsweb or via cvsget.\n- Low level abstraction layer available in C from CVS.\n- Character simulation software is currently under development.\n \n\n\n \n \n \n\n===== \n synthesis results =====\n\nLeonardoSpectrum synthesis results for Altera devices. Aimed at 100MHz clock operation (wishbone clock & pixel clock), area optimezed.\n\n- FLEX: EPF10K50E-1: 1112lcells, 16080mem_bits@82MHz wishbone, 100MHz pixel clock\n- ACEX: EPF1K50-1: 1113lcells, 16080mem_bits@85MHz wishbone, 107MHz pixel clock\n- APEX: EPF20K60E-1: 1142lcells, 16080mem_bits@47MHz wishbone, 119MHz pixel clock" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - rherveille - hoffer name: vga_lcd status: ASIC and FPGA proven svn-updated: Mar 10, 2009 updated: Sep 21, 2013 wishbone-compliant: 1 - category: Video controller created: Aug 6, 2010 description: "===== \n Description =====\n\nThis core is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.\n\n\nMinimal VGA framebuffer core\nRGB565 16bpp\nDirectly drives a 3x8-bit DAC and sync signals.\nFully configurable timings and resolution\nMultiple buffering support with buffer switch during the blanking interval to prevent tearing artifacts.\nMilkymist CSR and FML bus interfaces.\nTwo asynchronous clock domains - VGA and system.\nBit-banged DDC interface.\n\n \n\n\n \n \n \n\n===== \n More information =====\n\n\nCore documentation\nCSR bus specifications\nFML bus specifications" language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: vgafb status: FPGA proven svn-updated: Aug 24, 2010 updated: Aug 7, 2010 wishbone-compliant: 0 - category: Arithmetic core created: May 27, 2004 description: "===== \n Features =====\n\n- direct traceback option.\n- self test automation\n- support any popular convolution code. \n- throughput and area of decoder are scalable.\n- in place state metric storage.\n- parameterized modules.\n- something else.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Place a VHDL/Verilog version for K=7 rate=1/2 Poly=(91,121 in decimal) TracebackDepth=64 decoder for Download\n \xC2\xA0 It's a zip file, rename to .zip\n or look up the http://viterbi-gen.sourceforge.net example section.\n- Version 1.3\n- Place a TD-SCDMA version of K=9 rate=1/2 decoder for download.\n- Place a VHDL version of K=9 rate=1/2 decoder for download, in the requirement of Mitchell.\n- Version 1.2\n- contributed by moti: add encoder.pl, new testbench, insert srst signal in traceback module\n\n- Version 1.1\n- Version 1.0\n- To be continued\n- Updated \n \n\n\n \n \n \n\n===== \n Viterbi HDL Code Generator =====\n\nThis is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.\n\nIf you have any advices, please email to jhonson.zhu@gmail.com.\nAnd I have creat a project at sourceforge.net, too. You can find them here.\n\nhttp://viterbi-gen.sourceforge.net\n\nNow you can post questions \nhttp://groups.yahoo.com/group/vhcg (Disabled)" language: Other license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - mike name: vhcg status: Design done svn-updated: Apr 14, 2009 updated: Mar 25, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Apr 8, 2010 description: "===== \n Description =====\n\nVHDL Implementation of a basic Pipeline MIPS processor. It has a translator of MIPS assembler code and implement the division algorithm restoring." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - elujan name: vhdl-pipeline-mips status: Stable svn-updated: Apr 10, 2010 updated: May 29, 2010 wishbone-compliant: 0 - category: Other created: May 15, 2006 description: "===== \n Description of project =====\n\nThis project emulates a CPU for an FPGA under simulation with the use of text files. It can be used to test an FPGA - CPU interface using realistic real-world stimuli. One main text file per CPU emulation instance is used for global CPU commands, and thread spawning. Each spawned thread is tied to an additional text file to use as its 'source code'.\n \n\n\n \n \n \n\n===== \n Functionality: =====\n\nFeatures:\nConfiguration of clock, and reset, and read latency.\nWait for time period\nWait for signal value (good for interrupts)\nDeclare local and global variables (bit, vector8, or string)\nNested while loops with separate variable space in each nesting\nNested if conditionals (no new variable space)\nUnlimited number of threads\nPrint variables to a file (line by line)\nWrite a value or variable to an address\nRead a value from an address and place in variable\nRead using a DMA and writing values to a file\n\nThread control:\nEach thread runs until it hits a wait or the end of the file. If no wait is hit, then it will continue to run and choke the system. There is no DMA write provided as the software supports only 0 latency writes such that consecutive writes in a while loop perform the DMA. See ctc.txt lines 24 - 36 for an example of this. All commands other than wait, read and write take 0 time. Only wait or wait_interruptX cause the thread switching.\n\nUsage:\nThe provided design_top_tb.vhd uses the cpu_sim.vhd, package.vhd, and the accompanying text files to show some accesses. the file access_2us.txt shows a simple read occuring every 2 microseconds. The other text files are some examples of real world use, but they won't work as they are. They need to be modified for your design needs.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n1st version in CVS" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - nachumk name: vhdl_cpu_emulator status: Alpha svn-updated: Mar 10, 2009 updated: Sep 7, 2009 wishbone-compliant: 0 - category: Testing / Verification created: Mar 27, 2007 description: "===== \n Overview =====\n\nThe VHDL test bench is a collection of VHDL procedures and functions which allow the user to create their own scripting instructions for test stimulus. The stimulus script or test case contains the instructions in a regular ASCII text file. The function of the instructions is coded in VHDL as part of the test bench. The test bench VHDL package contains procedures to create instructions, read, parse and execute the test script (stimulus file, test case, script).\n\n-------------------------------------------\nJune 10, 2009\nThis update of the Overview page was to clean up the duplicate text. An update fixing a current bug report, and request will happen shortly.\n\n--------------------------------\nJune 20, 2009\nCommit fix to variable addition/validation bug here: http://opencores.org/?do=viewbug&bug=467\nUpdate example to match the package version here: http://opencores.org/?do=viewbug&bug=472\n\n----------------------------------------\nApril 19, 2014\nCommit the VHDL Test Bench Package as is released on my privet download site.\nThis includes one minor fix, and one upgrade to enable an undefined number of parameters for a command.\nAlso, another example and a code snips file with more examples and code to copy.\nOpen Office does not enable the output of PDF files (my latest version ..), so only Open Office output is\nincluded for the documentation. Details of the changes are document.\n\nThe ttb_gen_gui tool has also been updated to enable more VHDL syntax parsing. Multi pin definitions\non a single line are now supported.\n\n----------------------------------------\nAug. 19 2014\nChange licensing of the VHDL Test Bench Package to BSD-2 clause\nRemove duplicate copies of package files from packet_gen example\nRemove old versions of ttb_gen application, rename most recent version to ttb_gen_gui\n \n\n\n \n \n \n\n===== \n Blog Link =====\n\nI have started a Blog at this link:\nhttp://vhdltb.blogspot.com/" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - sckoarn name: vhld_tb status: ASIC and FPGA proven svn-updated: Aug 19, 2014 updated: Sep 4, 2014 wishbone-compliant: 0 - category: Video controller created: Jun 10, 2012 description: "===== \n Description =====\n\nThe core supplies post-processing for a video signal.\nIt reduces the color width while dithering the image to keep the impression of more colors than really exist.\nThis reduces banding effects and enhances the quality for the viewer.\n\nThe used method is \"Sierra Lite\".\n\nThe core is configurable (at compile/synthesis time) in:\n- resolution\n- input color width\n- output color width\n\nIt uses very few ressources. \nCommon Full HD Dithering (1920*1080 @ 60hz @ 6 bit from 8 bit source)\nused with many LCD Displays possible on cyclone 2:\n- 120 LE\n- 8kbit Memory (2 M4K Blocks)\n- timing met (~125 Mhz required, ~140 Mhz possible)\n\nTested in simulation:\nbmp read -> processing -> written back to bmp\n\nTested on hardware using Altera/Terasic DE1:\n- Cyclone 2\n- 640 * 480 @ 60hz\n- Reduction from 8 bit per color to 3 bit per color\n \n\n\n \n \n \n\n===== \n How to use =====\n\nSimulation\n----------\n\n1. Compile both files, containing dither entity and testbench.\n2. Run all\n3. Testbench will stop automatically when the whole image is processed\n4. View Output.bmp for result\n\nNote: for some reason MS Paint doesn't like the output.bmp\nJust use another programm, e.g. FireFox, IrfanView, MS VisualStudio...\n\nyou should also try:\n- exchange the image in input.bmp\n- change reduced bits per pixel\n\n\nImplementation\n--------------\n- The core needs an image stream with 1 pixel(RGB) each clock.\n- You can disable the core if the stream is stopped for some reason.(e.g. VGA offscreen)\n- The core needs the x position of the current sample. \n- You should NOT input the same x position twice in a row\n- Always increase x with each clock cycle or turn the core off.\n- y change is automatically recognized\n- x must increase\n- y can increase or decrease, result may look slightly different but is same quality" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Peip_Robert name: video_dithering status: FPGA proven svn-updated: Jun 29, 2013 updated: Jun 29, 2013 wishbone-compliant: 0 - category: Video controller created: Nov 21, 2006 description: "===== \n Description =====\n\nThis kit is meant for people which want to start developing on fpgas but don't want to spent too much money on tooling and jtag debuggers.\n\nthis kit will contain a small fpga (altera Cyclone II) and an AVR (atmega64) microprocessor with dataflash for programming the fpga through the serial or USB connection. \n\nas peripherals for the fpga there are a video encoder and decoder on board, to connect the kit between a DVD player and a TV through composite I/O.\n\nsimple video filters can be tested on the kit, and as the AVR can use the fpga as external memory, it's also possible to control filters real time, or make stuff like an \"ambilight\" look-a-like. ( see new generation Philips LCD TVs ) \n\nWithin this project I will show how far the kit is developed, and hope that other developers will help with making the first I/O blocks to help the real starters. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- SD video in (composite)\n- SD video out (composite)\n- RS232 for programming and control\n- USB for control\n- All other pins are available on I/O connectors\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- working on the board design\n- selecting the exact components for the peripherals\n \n\n\n \n \n \n\n===== \n FILE: fpga_starter_kit_overview.pdf =====\n\nFILE: fpga_starter_kit_overview.pdf\nDESCRIPTION: block overview" language: Other license: unknown maintainers: - vlotech name: video_starter_kit status: Empty svn-updated: Mar 10, 2009 updated: Mar 11, 2015 wishbone-compliant: 0 - category: Video controller created: Feb 21, 2011 description: "===== \n Description =====\n\nThe Video Stream Scaler scales streaming video up or down in resolution. Bilinear and nearest neighbor resize\nmodes are supported.\n\nThis core provides run-time adjustment of input and output resolution, scaling factors, and scale\ntype. Compile time adjustment of maximum resolutions and data width.\n \n\n\n \n \n \n\n===== \n Resource usage and speed =====\n\nFPGA: Altera Cyclone III 3C120\nConfiguration: 10 bits per pixel, 1 color channel, RFIFO size of 3\n\nLogic Cells: 571\nRegisters: 237\nM9ks: 9\n9x9 multipliers: 3\n18x18 multipliers: 8\n\n\nGreater than 108MHz (SXGA 60Hz) maximum clock rate on Altera Cyclone III 3C120, speed grade 7, 19% total logic element utilization." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - tesla500 name: video_stream_scaler status: FPGA proven svn-updated: Feb 25, 2011 updated: Aug 7, 2012 wishbone-compliant: 0 - category: Video controller created: Mar 18, 2002 description: "===== \n Description =====\n\nThe 'Video Compression Systems Project' was started with the idea to provide readily available blocks for compression systems. Which, combined toghether, form a complete compression standard.\n\nExamples of popular standards are:\n- MPEG (MPEG-1, MPEG-2, MPEG-4) and H.264\n- H.310, H.320 etc. (video conferencing)\n- JPEG & MJPEG\n- etc.\n\nAll aspects of a standard are covered. The links on the top of this page provide access to the blocks needed to build a complete system.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Finished cores:\n- - 8x8 fully pipelined parallel DCT. Provides a DCT result every clock cycle.\n- - QNR. Quantization & Rounding Unit.\n- - Run-Length-Encoder.\n- - Huffman Encoder / Decoder.\n- - A base profile H.264 encoder\n\n- Developers wanted." language: VHDL and Verilog license: Custom (Verilog) and 3-clause BSD (VHDL) licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rherveille - andyzexia name: video_systems status: Stable svn-updated: Jun 23, 2009 updated: Aug 27, 2008 wishbone-compliant: 0 - category: Arithmetic core created: Oct 28, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: videocompression status: Empty updated: May 1, 2012 wishbone-compliant: 0 - category: Communication controller created: Dec 18, 2014 description: "===== \n Block Diagram =====\n\n\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe PCIe Engine is designed by Nikhef - Amsterdam, The Netherlands - for the ATLAS / FELIX project.\nIts main purpose is to provide a simple Direct Memory Access (DMA) interface to the Xilinx Virtex-7 PCIe Gen3 hard block. \nThe Engine is specifically designed for the 256 bit wide AXI4-Stream interface of the Xilinx Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe).\n\n\n\n\n\n\nDMA read and write\nThe main purpose of the PCIe Engine is therefore to provide an interface to standard FIFOs.\nThis is the done by the DMA_read_write block in the diagram above. \nThe read/write FIFOs have the same width as the Xilinx AXI4-Stream interface (256 bits) and run at 250 MHz.\nThe application side of the FPGA design can simply read or write the FIFOs.\nThe PCIe Engine will handle the transfer to Host PC memory, according to the addresses specified in the DMA descriptors.\n\n\n\n\n\n\nDMA control\nAnother functionality of the Engine is thus to manage a set of DMA descriptors.\nDescriptors consist of an address, a read/write flag, the transfer size (number of 32 bit words) and an enable line.\nDescriptors are handled by the DMA_control block.\nThese descriptors are mapped as normal PCIe memory or IO registers.\nBesides the descriptors and the enable line (one per descriptor), a status register for every descriptor is\nprovided in the register map.\n\n\n\n\n\n\nGeneric regiser map\nBesides DMA specific functions, the DMA control block can also handle generic control and monitor registers for user application.\n\n\n\n\n\n\nInterrupt handler\nThe Engine is provided with a generic MSI-X compatible interrupt controller.\n\n\n\nImplementation info\nFor synthesis and implementation of the cores, it is recommend to use Xilinx Vivado 2014.2. \nOther IP cores (FIFO, clock wizard and PCIe) are provided in the Xilinx .xci format, as well as the constraints file (.xdc) is in the Vivado 2014.2 Format. \nThe Engine is also known to work well with Vivado 2014.4, constraints will be updated.\n\n\n\n\n\n\nFor portability reasons, no Xilinx project files will be supplied with the Engine. \nInstead, a bundle of TCL scripts has been supplied to create a project and import all necessary files, as well\nas to do the synthesis and implementation. \nThese scripts are be described in details in the /documentation/pci_dma_core.pdf distributed with the Engine.\n\n\n\n \n\n\n \n \n \n\n===== \n Feedback =====\n\n>> Give comments and feedback using the official core thread on the OpenCores forum:\nforum_thread" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - fransschreuder - aborga name: virtex7_pcie_dma status: FPGA proven svn-updated: Apr 30, 2015 updated: Apr 30, 2015 wishbone-compliant: 0 - category: Other created: Mar 3, 2011 description: "===== \n Description =====\n\nAn Virtual RS232 Terminal developed with Avnet Xilinx Spartan 3A Evaluation Kit ( Spartan XC3S400A ) that has a LVDS LCD Controller (Notebook LCD used for development, 3 LVDS Pairs interface) and a PS2 Keyboard Receiver.\n\nThe Core receives the ScanCodes on PS2 Keyboard, and sends ascii through serial port. Also, it received the ASCII Chars on Serial port and write on a CharRam Buffer (80x60 chars) that displays on the LCD Screen.\n\nVideo from project:\nhttp://www.youtube.com/watch?v=fX3_T2NMSnM\n\nMore info at: http://www.energylabs.com.br (Portuguese with Google Translation)\n \n\n\n \n \n \n\n===== \n Details =====\n\nThere are things working, and things to be done.\n\nWorking:\n\n- Serial Data Receiver writting to Char Ram\n- Fixed 80x60 Char RAM\n- EnergyLabs Logo on ROM \n- ScanCodes on ROM\n- IBMPC 8x8 Font on ROM\n- All ROMS was implemented as blockram, so I am using about 50% of the block ram resources.\n- LCD LVDS Controller Uses modified XAPP486 and its a LVDS33 Signal.\n- Parallax Scrolling BackGround (Made with logic)\n- EnergyLabs Logo with Transparency (Color-Key)\n\nTodo:\n\n- Faster Serial Receiver. Dunno why its so slow to receive chars on the serial, even at 115200 (Maybe its something when write)\n- Dynamic Console Size\n- All ROMS stored at external flash\n- Modify XAPP486 or make a new 7-to-1 serializer (I tryed that, but the maximum speed at my core was only 40MHz), because I dont know how Xilinx made the XAPP486 and it has 4 channels (we only need 3) and the bits are in a different way.\n- External RAM for Screen, actually I wasnt done that because I Dont have external ram.\n\nFew things:\n\n- The XAPP486 sends the 7 bits for each channel in a different way that LCD needs, as I didnt understand how XAPP486 was write, I only mapped the correct bits. Its working correct, but I think it can be better." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - racerxdl name: virtual_rs232_terminal_with_lvds_lcd status: FPGA proven svn-updated: Mar 3, 2011 updated: Mar 3, 2011 wishbone-compliant: 0 - category: DSP core created: Oct 19, 2010 description: '' language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - yuhuang1987 name: vitdec status: Alpha svn-updated: Dec 4, 2010 updated: Dec 2, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Feb 5, 2012 description: '' language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - sandunrathnayake name: viterb_encoder_and_decoder status: Mature svn-updated: Feb 13, 2012 updated: Feb 23, 2012 wishbone-compliant: 0 - category: ECC core created: Jan 16, 2012 description: "===== \n Description =====\n\nA fully configurable VHDL Viterbi decoder compliant with the AXI4-Stream interface.\nMost standards using convolutional codes like Wifi or GSM are easy to implement by configuring some generic parameters.\nThe decoder supports a high throughput even on low-cost devices.\nSee the User Guide for more information about the core.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\nDesign-time configuration of encoder polynomials (different number of states and different code rates).\nSupport for recursive and non-recursive convolutional codes.\nWindowing technique for reduced latency and memory requirements (with acquisition).\nDesign-time configuration of quantization, maximum window size, RAM usage (distributed RAM vs. Block RAM).\nRun-time configuration of block length.\nRun-time configuration of window length and acquisition length.\nBlock-to-block on-the-fly configuration.\nComprehensive documentation available.\n\n \n\n\n \n \n \n\n===== \n Benefits =====\n\n\nConfigurable for most standards that apply convolutional codes (GSM, UMTS, CDMA, CDMA2000, WiMAX, WiFi, DAB, ...).\nPipelined design for high payload throughputs (about 1 bit per clock cycle).\nAXI4-Stream interface for simple integration.\nUp to 250 MHz on Xilinx Virtex-6 FPGA (Speedgrade 1).\nCommercial support and licenses available.\n\n \n\n\n \n \n \n\n===== \n Communications Performance =====\n\n\nComparison for Viterbi communications performance in various standards.\nFrame length is set to 400, while the LLR input bit length is 4 and no windowing is used.\n \n\n\n \n \n \n\n===== \n Contact author =====\n\nCreonic GmbH - Germany \nSite: www.creonic.com\nTel: +49 631 3435988-0" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - mfehrenz name: viterbi_decoder_axi4s status: FPGA proven svn-updated: Feb 17, 2014 updated: Apr 16, 2015 wishbone-compliant: 0 - category: Arithmetic core created: Dec 13, 2012 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - Senior name: vmpc status: Empty updated: Dec 13, 2012 wishbone-compliant: 0 - category: Arithmetic core created: Nov 25, 2010 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - inet2012 name: vpu status: Empty updated: Nov 25, 2010 wishbone-compliant: 0 - category: Arithmetic core created: Aug 2, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - maximd33 name: vs1053 status: Empty updated: Aug 2, 2011 wishbone-compliant: 0 - category: Communication controller created: Mar 23, 2012 description: "===== \n Description =====\n\n=== What's \"vSPI\"? ===\n\nvSPI is a Verilog implementation of an SPI slave. Think of it as a very fast serial port. It can reliably transfer data at 27.9 mbps on an Atlys FPGA devkit (a Spartan-6 with a 100 MHz system clock).\n\nYou can use it to send data between your FPGA/ASIC project and other devices, such as a desktop computer I'm using it to send data between a self-flying RC-helicopter and my PC. If all goes according to plan, I'll be able to see live video from the helicopter's camera on my PC. I'll also be able to inject test data and make sure my logic works with known test vectors.\n\n=== What's included? ===\n\nSo far, vSPI consists of three parts:\n\n- spiifc: The minimal logic that implements the SPI slave. spiifc takes the usual four SPI lines (MOSI, MISO, SS, SCLK) and has interfaces for input and output buffer memories as well as a register bank (more on what they do is below). If you work directly with spiifc, you'll need to figure out how to get this stuff to interface with the rest of your project. This is a good place to start if you have a project without a system bus or a non-PLB bus.\n\n- PLB interface: vSPI includes also includes a PLB interface if desired. PLB is one of the system bus protocols supported by the Microblaze processor provided in Xilinx's EDK (sometimes known as XPS). I may also add support for one of ARM's AMBA bus protocols later (AXI, etc.), but there is zero support for thst right now.\n\n- spilib python library: spilib is a python library that is used on your PC to make talking with spiifc easier. It is currently built on TotalPhase's Cheetah SPI USB/SPI adapter API. It makes interactions between a PC (master) and spiifc (slave) simple.\n\nThe full documentation is available in the Downloads section or directly using this link: http://opencores.org/usercontent,doc,1332776443\n\n=== Development Notice ===\n\nDay-to-day development is managed on github at http://github.com/mjlyons/vspi. If you would like cutting edge updates or would like to contribute, please use github.\n\nThis opencores project will be updated after the completion of any stable releases. If you just want to use stable releases, feel free to use the opencores project. You won't miss out on anything.\n\n=== License ===\n\nIf you use vSPI, whether for free or commercial purposes, I only ask that you let me know so that I can publicly keep track of who is using it. I don't care if you use it as is or modify it, so long as it isn't used in technologies to physically hurt or kill anyone (missile guidance systems, etc.).\n\nIf you want to use vSPI for any reason but wish to do so without publicly stating so, we can work out an alternative licensing agreement.\n\nThe vSPI project retains all ownership of code published here. Meaning, don't take the code, claim ownership, and then somehow sue the vSPI project.\n\n=== Contact Info ===\n\nYou can reach me at buzz.vspi@clearhive.com." homepage: http://github.com/mjlyons/vspi language: Verilog license: custom licensetext: "If you use vSPI, whether for free or commercial purposes, I only ask that you let me know so that I can publicly keep track of who is using it. I don't care if you use it as is or modify it, so long as it isn't used in technologies to physically hurt or kill anyone (missile guidance systems, etc.). \nIf you want to use vSPI for any reason but wish to do so without publicly stating so, we can work out an alternative licensing agreement. \nThe vSPI project retains all ownership of code published here. Meaning, don't take the code, claim ownership, and then somehow sue the vSPI project.\n" maintainers: - mjlyons name: vspi status: FPGA proven svn-updated: Mar 24, 2012 updated: Mar 26, 2012 wishbone-compliant: 0 - category: Processor created: Jun 28, 2013 description: "===== \n Description =====\n\nVerilog implementation of the old CARDIAC teaching computer from Bell (the one made out of cardboard). This version runs on a Spartan 3 board from Digilent and it is pretty faithful to the original.\n\nDocumentation about the project:\n\n\nhttp://www.drdobbs.com/embedded-systems/the-heart-of-a-cpu/240153772\nhttp://www.drdobbs.com/embedded-systems/expanding-vtach/240155198\nhttp://www.drdobbs.com/embedded-systems/cardiac-to-fpga/240155599\nhttp://www.drdobbs.com/embedded-systems/paper-to-fpga/240155922" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - wd5gnr name: vtach status: Mature svn-updated: Jun 29, 2013 updated: Mar 30, 2014 wishbone-compliant: 0 - category: Processor created: Jul 6, 2010 description: "===== \n Description =====\n\n\n \n \n \n Fig D-1: A PDP-11/70 Console. These display and switch consoles were the \n hallmark of the PDP-11 computers in the 70ties.\n Picture courtesy of Henk Gooijen, see also \n Henk's PDP-11 collection.\n \n\n\nThe project contains a complete \nDEC \nPDP-11 \nsystem: a PDP-11/70 CPU with memory management unit, but without floating point\nunit, a basic set of UNIBUS \nperipherals (DL11, LP11, PC11, RK11/RK05), and last but not least a cache and \nmemory controllers for SRAM and PSRAM. The design is FPGA proven, runs \ncurrently on Digilent\nBasys3\n,\nNexys4 \n,\nNexys3 \n,\nNexys2 \nand\nS3board\nboards and boots \n5th Edition UNIX and \n2.11BSD UNIX.\n\n\n\n\nThis is a retrocomputing project, rebuilding hardware from the late 70s\nand running historical software. To get into the tune see \nFigure D-1, a 11/70 console, and\nFigure F-2, a baseline system setup.\n\n\n\nNews 2015-03-09: Release w11a_v0.64 available for details see section\nReleases.\n\nNews 2014-06-19: \ndoxygen\ngenerated code browsing available for vhdl and C++ sources. \nNo documentation text added so far, but helpful to navigate through the code. \nGood starting points are \n\nvhdl module list, or\n\nsys_w11a_n3 source, or\n\nC++ class list .\n\n\n\n\n\n\n\n\n\n\n\nFor more details see the sections:\n\n\n\n\n Features\n Implementation\n Installation\n Verification\n Systems\n Performance\n Roadmap\n Resources\n Thanks\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nRunning Systems\nThe project holds all the sources to synthesize a complete system. \nComplete configurations for three boards are currently part of the project,\nthe Digilent S3BOARD, Nexys2 and Nexys3 boards. \nSee section \n Features: Complete Systems for details.\n\n\n\nSo far two UNIX systems have been successfully booted on the w11a:\n\n UNIX 5th edition\n 2.11 BSD UNIX\n\nSee section \n Systems for details,\nincluding links to the disk sets.\n\n\n\n\nKnown Issues\n\nThere are some known difference between w11a and 11/70 and also known\nbugs in the current w11a implementation (see \nw11a_known_issues.txt).\nThey affect the behaviour in cases like fatal stack errors or certain\ndouble faults which don't occur in the normal operation of an operating\nsystem, and if they happen, in general lead to a crash anyway.\n\n\n\nThe known differences are not considered worth fixing them, while the\nknown bugs will be addressed in future versions of the w11a core.\n\n\n\n\nGiven that the w11a boots 2.11BSD the cores are considered \n'Design Done' and 'FPGA proven'. The USB based Rlink\ninterface and the backend software perform very well. Given the loose ends \nlisted above the project is still considered 'Beta' quality.\n \n\n\n \n \n \n\n===== \n Milestones =====\n\nBeing a 'leisture time project' things evolve at a modest pace. Key milestone\nso far were:\n\n \n \xC2\xA0\xE2\x80\xA2\n Mar-2015:\n \xC2\xA0\n use Vivado; Artix-7 ports added (for Basys3 and\n Nexys4); added RL01/RL02 disks\n \n \n \xC2\xA0\xE2\x80\xA2\n Apr-2013:\n \xC2\xA0\n new C++/Tcl backend server, w11a designs operate with rlink over USB\n \n \n \xC2\xA0\xE2\x80\xA2\n Jan-2012:\n \xC2\xA0\n Cypress FX2 USB controller support added, rlink and config over\n USB.\n \n \n \xC2\xA0\xE2\x80\xA2\n Dec-2011:\n \xC2\xA0\n Spartan-6 port of w11a added (for Digilent Nexys3 board).\n \n \n \xC2\xA0\xE2\x80\xA2\n Jul-2010:\n \xC2\xA0\n OpenCores project w11 created; \n w11a V0.5 tagged and released.\n \n \n \xC2\xA0\xE2\x80\xA2\n May-2010:\n \xC2\xA0\n w11a systems ported to Digilent Nexys2 board; lots of cleanup.\n \n \n \xC2\xA0\xE2\x80\xA2\n Sep-2009:\n \xC2\xA0\n 2.11BSD UNIX boots to multi-user mode on w11a on FPGA.\n \n \n \xC2\xA0\xE2\x80\xA2\n Aug-2009:\n \xC2\xA0\n UNIX 5th Edition boots on w11a on FPGA.\n \n \n \xC2\xA0\xE2\x80\xA2\n Jun-2009:\n \xC2\xA0\n Found \n 11/70MP system manual on \n bitsavers.\n Most of IIST implemented. Too early, but fun.\n \n \n \n \xC2\xA0\xE2\x80\xA2\n Dec-2008:\n \xC2\xA0\n Finished the last of three 2.11BSD patches, now \n \n 2.11BSD boots of a RK05 disk set and \n \n runs on a 11/70 without FPP in simh.\n \n \n \xC2\xA0\xE2\x80\xA2\n Mar-2008:\n \xC2\xA0\n Full system with CPU, cache, and minimal I/O system runs on FPGA.\n \n \n \xC2\xA0\xE2\x80\xA2\n Sep-2007:\n \xC2\xA0\n rri (rbus+rlink) implemented, w11a runs on FPGA (Digilent S3BOARD).\n \n \n \xC2\xA0\xE2\x80\xA2\n Sep-2006:\n \xC2\xA0\n CPU and MMU implemented, simple test codes run.\n \n \n \xC2\xA0\xE2\x80\xA2\n Jun-2006:\n \xC2\xA0\n Re-discovered a pile of PDP-11 manuals in a forgotten box full of old\n paper work. This triggered the idea, and with \n simh,\n ghdl and\n bitsavers\n at hand, 2.11BSD as target OS and a \n \n 11/74 picture \n as desktop background it quickly became a project.\n \n\n\n \n\n\n \n \n \n\n===== \n Releases =====\n\nMajor releases are tagged on svn, minor releases are denoted only via the svn \nrevision.\n\n\n \n Release\n Date\n svn\xC2\xA0tag\n svn\xC2\xA0rev\n README\n \xC2\xA0\n Comment\n \n \n \n \xC2\xA0w11a_V0.64\xC2\xA0\n \xC2\xA02015-05-09\xC2\xA0\n -\n 29\n README\n \xC2\xA0\n Support for Vivado; port of w11a to Basys3\n and Nexys4; RL01/RL02 disks\n \n \n \n \xC2\xA0w11a_V0.63\xC2\xA0\n \xC2\xA02015-01-04\xC2\xA0\n -\n 28\n README\n \xC2\xA0\n w11a rbus interface and C++/Tcl backend now use rlink v4\n features, much reduced number of round trips\n \n \n \n \xC2\xA0w11a_V0.62\xC2\xA0\n \xC2\xA02014-12-20\xC2\xA0\n -\n 27\n README\n \xC2\xA0\n Introduced rlink protocol v4 (see README_Rlink_V4)\n \n \n \n \xC2\xA0w11a_V0.61\xC2\xA0\n \xC2\xA02014-08-10\xC2\xA0\n w11a_V0.61\n 25\n README\n \xC2\xA0\n Bugfix for DIV instruction\n (see ECO-026-div);\n other minor fixes\n \n \n \n \xC2\xA0w11a_V0.6\xC2\xA0\n \xC2\xA02014-06-06\xC2\xA0\n w11a_V0.6\n 23\n README\n \xC2\xA0\n from 0.5 -> 0.6: revised ibus and rbus protocol; \n backend server rewritten; Nexys3 port; Cypress Fx2 support; \n LP11,PC11 support\n \n \n \n \xC2\xA0w11a_V0.581\xC2\xA0\n \xC2\xA02014-05-29\xC2\xA0\n -\n 22\n README\n \xC2\xA0\n Fixes for ISE 14.7; Spartan-6 CMT support; more man pages\n \n \n \n \xC2\xA0w11a_V0.58\xC2\xA0\n \xC2\xA02013-05-12\xC2\xA0\n -\n 21\n README\n \xC2\xA0\n LP11,PC11 support added; old backend retired; operating system kits re-organized\n \n \n \xC2\xA0w11a_V0.57\xC2\xA0\n \xC2\xA02013-04-27\xC2\xA0\n -\n 20\n README\n \xC2\xA0\n w11a systems with rlink over USB on nexsy2 and nexsy3 boards\n \n \n \n \xC2\xA0w11a_V0.562\xC2\xA0\n \xC2\xA02013-04-13\xC2\xA0\n -\n 19\n README\n \xC2\xA0\n Phase 2 of new C++/Tcl backend, add cpu and first\ndevice support; add asm-11 assembler\n \n \n \n \xC2\xA0w11a_V0.561\xC2\xA0\n \xC2\xA02013-01-06\xC2\xA0\n -\n 18\n README\n \xC2\xA0\n Add bugfixes, Cypress FX2 simulation model, and test\n designs for Nexys3 and Atlys boards\n \n \n \n \xC2\xA0w11a_V0.56\xC2\xA0\n \xC2\xA02013-01-02\xC2\xA0\n -\n 17\n README\n \xC2\xA0\n Add \n Cypress FX2\n USB interface controller; FX2 firmware supporting jtag access and\n data transfer; test system for rlink over USB verification\n \n \n \n \xC2\xA0w11a_V0.55\xC2\xA0\n \xC2\xA02011-12-23\xC2\xA0\n -\n 16\n README\n \xC2\xA0\n Add xon/xoff (software flow control) support to serport \n library; Add test design for serport verification\n \n \n \n \xC2\xA0w11a_V0.54\xC2\xA0\n \xC2\xA02011-12-04\xC2\xA0\n -\n 15\n README\n \xC2\xA0\n Add Nexys3 port of w11a\n \n \n \n \xC2\xA0w11a_V0.532\xC2\xA0\n \xC2\xA02011-11-20\xC2\xA0\n -\n 14\n README\n \xC2\xA0\n Add test design for 'human I/O' interface; migrate to\n use numeric_std\n \n \n \n \xC2\xA0w11a_V0.531\xC2\xA0\n \xC2\xA02011-09-12\xC2\xA0\n -\n 12\n README\n \xC2\xA0\n Prepare upcoming support for Spartan-6 (nexys3 and atlys)\n and Cypress FX2 USB (nexys2/3 and atlys)\n \n \n \xC2\xA0w11a_V0.53\xC2\xA0\n \xC2\xA02011-04-17\xC2\xA0\n -\n 11\n README\n \xC2\xA0\n Introduced new backend written in C++ and Tcl. Phase 1 \n with functionality to execute simple test benches\n \n \n \xC2\xA0w11a_V0.52\xC2\xA0\n \xC2\xA02011-01-02\xC2\xA0\n -\n 9\n README\n \xC2\xA0\n Introduced rbus protocol V3; reorganize rbus and rlink \n modules, many renames\n \n \n \xC2\xA0w11a_V0.51\xC2\xA0\n \xC2\xA02010-11-28\xC2\xA0\n -\n 8\n README\n \xC2\xA0\n Introduced ibus protocol V2; Nexys2 systems use DCM;\n sys_w11a_n2 now runs with 58 MHz\n \n \n \xC2\xA0w11a_V0.5\xC2\xA0\n \xC2\xA02010-07-23\xC2\xA0\n w11a_V0.5\n -\n README\n \xC2\xA0\n Initial release: w11a CPU core; \n basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05;\n two complete systems for Digilent S3BOARD and Nexys2" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - wfjm name: w11 status: FPGA proven svn-updated: Mar 9, 2015 updated: May 1, 2015 wishbone-compliant: 0 - category: Video controller created: Jun 26, 2008 description: "===== \n Description =====\n\nTexture mapping unit tailored for Milkdrop acceleration.\n\nThis core was designed for Milkymist, a highly integrated opensource VJing platform. See the project page at http://www.milkymist.org.\nA complete description of the core is available in the Milkymist documentation.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- High performance. Area-optimized implementation reaches 30MPixels/s in a fully running Virtex-4 based SoC with VGA output enabled.\n- Low resource usage (approx. 20% of XC4VLX25 slices).\n- High clock frequency (SoC meets timing at 100MHz in XC4VLX25).\n- Objects are triangle meshes.\n- Fade-to-black (decay) feature.\n- eGPL license\n\nTo be implemented :\n- Bilinear filtering.\n- Alpha blending.\n \n\n\n \n \n \n\n===== \n Status =====\n\nWorking in Milkymist... see video demonstration at http://milkymist.org/pictures.html\n \n\n\n \n \n \n\n===== \n Technical documentation =====\n\n- Texture mapping unit specifications\n- CSR bus specifications\n- FML bus specifications" language: Verilog license: eGPL2 licenselink: http://www.egpl.info/egpl-2.0.txt maintainers: - lekernel name: warp status: FPGA proven svn-updated: May 7, 2009 updated: Sep 27, 2010 wishbone-compliant: 0 - category: DSP core created: Oct 22, 2008 description: "===== \n Description =====\n\nThis core is a straight forward implementation of a Numerically Controlled Oscillator (NCO) - also referred to as a Direct Digital Synthesizer (DDS). In addition to generating the standard SIN/COS output waveforms, it also generates Square and Sawtooth outputs with very little extra resource. NCOs form an essential component in many Digital Comms applications - especially in digital modulation, up/down conversion and the generation of complex signals. This core is also great for test-benches as it provides a simple way to generate input stimuli for Filters, DSP circuits etc. The following Mean-square plot shows an example output tone of 1.7MHz for a 100MHz sample frequency. The NCO pdf datasheet fully documents how to use and configure the NCO core.\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 12-bit signed output data samples\n- 32-bit phase accumulator\n- Phase resolution of 2Pi/2^12\n- Frequency resolution of Fs/2^32 (Fs = sample frequency)\n- ~70 dB Signal-to-Noise Ratio (SNR)\n- ~70 db Spurious Free Dynamic Range (SFDR)\n- Simultaneous SIN, COS, SQUARE and SAWTOOTH outputs\n- 2 clock-cycle latency\n- Sample rates of 500MHz or better (Xilinx Virtex 5 / Altera Stratix III)\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Basic version fully tested and complete\n- Future optimizations to improve SNR/SFDR will be considered\n \n\n\n \n \n \n\n===== \n Help and Support =====\n\nSimon Doherty is a Senior Design Consultant at ZIPcores If you require further assistance regarding the implementation of this core, you may contact me directly via my Opencores email alias at sdoherty@opencores.org. Alternatively you may contact me through customer support at ZIPcores." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - sdoherty name: waveform_gen status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 26, 2011 wishbone-compliant: 0 - category: Arithmetic core created: Nov 10, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - alzhang name: wb2axi4 status: Alpha svn-updated: Mar 20, 2015 updated: Mar 31, 2015 wishbone-compliant: 1 - category: Other created: Dec 2, 2002 description: "===== \n Description =====\n\nWB Interface for TI 5x DSP (HPI) developed for use with Opencores PCI Bridge.\n \n\n\n \n \n \n\n===== \n Features =====\n\n1. Direct access to DSP Control Registers\n2. Block transfer from DSP address space to WB address space \n3. Block transfer from WB address space to DSP address space\n4. Interrupt support (both are maskable)\n- interrupt after block transfer; and \n- interrupt from DSP.\n5. Maped DSP address space to WB address space.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Core is finished, testing some parts at the moment\n- Writing documentation\n- Test bench for PCI card, with hex editor for DSP memory, was written (Win Platform). It will be available with core. \n- Screenshots of software are available. Adopting (Win) driver to be flexible as much as possible at the moment.\n- Source uploaded\n- Works (real hw) with new Opencores PCI core.\n- Updated to work with new Opencores PCI files (again)" language: VHDL and Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - gvozden - dusko name: wb2hpi status: Stable svn-updated: Mar 10, 2009 updated: Feb 20, 2004 wishbone-compliant: 1 - category: Memory core created: Apr 6, 2011 description: "===== \n Description =====\n\nTwo WISHBONE wrappers will be developed for Xilinx Memory Interface Generator (MIG). The first is compliant with version B4 Registered Feedback Incrementing Burst Cycle. The second is a non-compliant but streamlined interface developed as a proposal for inclusion as a new Burst Cycle Type geared towards interfacing with high latency devices." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - pbaker name: wb2mig status: Planning svn-updated: Apr 7, 2011 updated: Apr 7, 2011 wishbone-compliant: 1 - category: Processor created: Jan 5, 2010 description: "===== \n Description =====\n\nThis project provides interface logic and assembler routines, giving PicoBlaze (TM) embedded soft-uC the ability to access wishbone systems or slave cores as an 8-bit master device. There is no native hardware handshake mechanism at PicoBlaze (TM) ports, so wishbone wait-state recognition is done by software polling. Some standard wishbone slave peripherals like GPIO and UART are included as well.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\nMulti HDL language implementation VHDL and Verilog (R)\nAssembler subroutines\nSimulation testbench and command file\nNotepad++ custom syntax highlighter for assembler\nSynthesizable GPIO example\nSynthesizable UART example, using Xilinx (R) UART macros together with a wishbone slave wrapper\nBaud rate calculation script\nImplementation files for low cost AVNET (R) Spartan(R)-3A Evaluation Kit using Xilinx ISE (R) 13.1\n\n \n\n\n \n \n \n\n===== \n Getting Started =====\n\n\nPrerequisites: Xilinx ISE (R) and ModelSim Xilinx Edition III (R)\nDownload wb4pb sources and be sure to keep directory structure!\nDownload PicoBlaze (TM) from Xilinx (R) (registration required)\nCopy kcpsm3.v and kcpsm3.vhd to rtl directory\nOpen picoblaze_wb_gpio_tb.do in a text editor and customize \"set wd ...\" and \"set isVHDL ...\" lines\nStart ModelSim (R) and execute DO-File (Menu->Tools->TCL->Execute Macro...)\n\n\n \n\n\n \n \n \n\n===== \n Synthesis Results =====\n\nxc3s400a-4ft256 device using Xilinx ISE (R) 13.1 with default settings\n\nGPIO example VHDLGPIO example Verilog (R)UART example VHDLUART example Verilog (R)\nmax. frequency97.220MHz102.082MHz101.647MHz100.553MHz\nclock nets1111\nLUTs202202309310\nFFs147147213213\nI/Os9955\nRAMs1111\nslice utilization3%3%5%5%" language: Verilog & VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: [] name: wb4pb status: FPGA proven svn-updated: Aug 28, 2013 updated: Apr 22, 2011 wishbone-compliant: 1 - category: Memory core created: Nov 7, 2008 description: "===== \n Description =====\n\nThis is a wrapper for an inferred single port RAM, that converts it into a Three-port RAM with one WISHBONE slave interface for each port.\n \nVery useful as a drop-in module to create configuration registers for any core.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Generics for data and address widths of internal RAM\n- Included inferred single port ram (but ready to use an instantiated SPRAM component, i.e.: generated by coregen)\n- Wait states are reduced to the very minimum (writes immediately acked)\n- Provides a way to lock access to only one port at a time (by keeping wb_cyc line high in the port of the locking master)\n- Priority switching to avoid deadlocks (when one port is freed, the next port's pending request will be serviced)\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 07/11/2008: Project created in OpenCores\n \n\n\n \n \n \n\n===== \n Interface =====\n\nThe interface includes the standard WISHBONE lines: wb_clk_i and wb_rst_i (active high asynchronous reset).\n\nApart from these two, there are three independent WISHBONE slave ports, each with the following lines (N goes from 1 to 3):\n- wbN_cyc_i\n- wbN_stb_i\n- wbN_we_i\n- wbN_adr_i\n- wbN_dat_i\n- wbN_dat_o\n- wbN_ack_o\n\nIMPORTANT: To achieve the best performance, memory writes are implemented with immediate acks. This means that no read is performed during a write, so wb_dat_o MUST be ignored when a write is acked.\n\nOPERATION:\n\nLet's define the situation as one in which there are three masters (A,B, and C) connected to this core, trying to do simultaneous operations on the spram, each one connected to one of the WB ports (A -> wb1, B -> wb2, and C -> wb3). \n\nOf course, if one port is not used, its cyc and stb lines MUST be tied low to prevent the core from deadlocking. Take note also that if one port is not used, the core won't see its performance affected, that is, it will work as if it were a two port wrapper, instead of three ports.\n\n\nNORMAL OPERATIONS:\n\nIn case there is no need to make atomic operations, a master connected to a port of this core can work as if there weren't any other masters connected to other ports.\nPlus, the core switches the port priority the moment a master (that was using the memory) drives low its cyc and stb lines.\n\nThat is, for example: master B does an operation (R/W), and it is acked by this core. Then, if master B drives low its cyc and stb lines, and in the next cycle master B and master C rise their cyc and stb lines simultaneously, master C will be the one serviced, not master B again. This way a greedy master won't take up the bus.\n\n\n\nATOMIC OPERATIONS (port locking):\n\nLet's suppose that master B wants to make a set of atomic operations consisting of one read, then a pause of 20 cycles, then a write, then another pause of 5 cycles and then another write. This master (B) needs to know that no other master connected to this core (A or C) does any read or write to the memory, while this set of atomic operations is being performed.\n\nIn order to make atomic operations, master B (which is connected to, for example, the 2nd WB port) would need to drive high the wb2_cyc and wb2_stb lines, to perform the first read of the set of atomic operations. After receiving the ack from this core, master B will drive low ONLY the line wb2_stb during the 20 pause cycles master B to prepare the next write it needs to do.\n\nThen, master B should drive high again the stb line and perform the write (of course rising also the \"we_i\" line and putting the right data on \"dat_i\" and \"adr_i\" lines), remember that the cyc line was already up, to lock the memory on to this port.\n\nAfter receiving the ack for this write, the master B of this example needs another 5 cycles of processing in which it won't make any other operations on the RAM, so after the second ack (the one corresponding to the second WB operation, the write) it will drive low ONLY the wb2_stb line, keeping cyc high, that way the memory bus is locked on to this port, and it won't service requests, again, from other ports.\n\nAfter the five cycles, master B makes its last operation of the example, another write, by driving high the stb line (and with the rigth we_i, dat_i and adr_i lines, obviously) and waiting to be acked by this core, meaning that the memory was written. After receiving this third, and last, ack master B will drive low its wb2_cyc and wb2_stb lines, because it has ended the atomic set of operations, so that master A and C can keep on using the memory.\n\nI short: Keeping the wbN_cyc line high with the wbN_stb line low (after being acked once) will signal to this core that the memory must be kept locked on to master N and no other request from other ports will be serviced until the cyc line is lowered again.\n\nA WISHBONE slave port N may be considered locked onto its master X when: \n\n1) this slave port N acks one time\n2) the wbN_cyc line is not driven low by master X.\n\nFrom this point on, the acked master may make any operations on this slave port, knowing for sure that no other master will be able to access the memory until the cyc line is driven low again. (the \"slave acks one time\" requirement is because up until that moment, the master can not be sure that there is another master already locking this slave)\n\nIn simple terms, any group of atomic operations must be preceded by a read, and the cyc line must not be driven low until the end.\n \n\n\n \n \n \n\n===== =====" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - galland name: wb_3p_spram_wrapper status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 23, 2009 wishbone-compliant: 1 - category: Memory core created: Nov 18, 2009 description: "===== \n Description =====\n\nThis project provides a bridge between asynchronous external memory interfaces found on many processors and a WishBone bus. It is being used on the de1_olpcl2294_system project." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qaztronic name: wb_async_mem_bridge status: Alpha svn-updated: Mar 29, 2011 updated: Dec 4, 2009 wishbone-compliant: 1 - category: System on Chip created: Apr 26, 2004 description: "===== \n To do =====\n\n- add verilog output\n \n\n\n \n \n \n\n===== \n Known errors =====\n\n- when data bus size is 8 bits the script generates wishbone sel signals which are of no use\n \n\n\n \n \n \n\n===== \n Features =====\n\n- GUI for easy startup\n- supports both shared bus and csorrbarswitch topology\n \n\n\n \n \n \n\n===== \n Status =====\n\n- design tested in HDL simulator and in FPGA (ALTERA C12)\n- current design only support VHDL output\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe intention is to provide an easy way to create and change a system based on the WISHBONE bus. The user shall be able to try different configurations to achieve an area/performance optimized design.\n\nWISHBONE builder is a script which generates a wishbone interconnect matrix in HDL. The user defines the functionallity of the wishbone bus in a text file or via a GUI. The tools then generates the HDL implementation.\n\nThe core supports both shared bus and crossbar switch implementations.\n\nTo run the WISHBONE builder you must have installed PERL. A windows executable can be found at http://www.activestate.com/. In Linux PERL is usually installed with the system. The GUI uses a PERL module called Tk. Tk can be found at CPAN, http://www.cpan.org/." language: VHDL or Verilog license: unknown maintainers: - unneback name: wb_builder status: Stable svn-updated: Mar 20, 2013 updated: Oct 3, 2014 wishbone-compliant: 1 - category: System on Chip created: Apr 15, 2003 description: "===== \n Description =====\n\nThis is a WISHBONE Interconnect ShareBus IP core.It can interconnect up to 8 Masters and 8 Slaves \n\nSome of the main features are: \n\nUp to 8 Masters \nUp to 8 Slaves \nOnly 1 priority level processed in a round robin way\n \n\n\n \n \n \n\n===== \n Features =====\n\n- feature1\n- feature2\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 4/19/2003 Initial Release" language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - johny name: wb_conbus status: Stable svn-updated: Mar 10, 2009 updated: Aug 3, 2012 wishbone-compliant: 1 - category: System on Chip created: Oct 23, 2001 description: "===== \n Description =====\n\nThis is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves \n\nSome of the main features are: \n- Up to 8 Masters \n- Up to 16 Slaves \n- 1, 2 or 4 priority levels \n- Fully configurable \n \n\n\n \n \n \n\n===== \n IMAGE: conmax.jpg =====\n\nFILE: conmax.jpg\nDESCRIPTION: Example SoC with the CONMAX IP Core\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- October 2002, Maintenance update: Fixed a typo in parameter passing and in the specification\n- May 2002. Several users of the core have reported that the core performs as specified. Project is now considered completed.\n- 10/19/2001 Initial Release.\n- I will post a message to cores@opencores.org each time I have an update \n \n\n\n \n \n \n\n===== \n Change log =====\n\n- 10/19/2001 Initial Reslease\n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: wb_conmax status: Stable svn-updated: Mar 10, 2009 updated: Feb 10, 2004 wishbone-compliant: 1 - category: System on Chip created: Sep 25, 2001 description: "===== \n Description =====\n\nThis is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces. \n\nSome of the main features are: \n- Up to 31 DMA Channels \n- 2, 4 or 8 priority levels \n- Linked List Descriptors support \n- Circular Buffer support \n- FIFO buffer support \n- Software & Hardware handshake support \n- Automatic Channel Registers Reload support \n- Fully configurable \n\nPlease see the spec for more details ! \n \n\n\n \n \n \n\n===== \n Status =====\n\n- 8/2/2001 Added another feature: Now you can backoff to the beginning of the current transfers (this is useful for things like Etherenet, where you might have to restart in case of collisions or errors). \n- New Directory Structure ! We have agreed on a common directory structure at OpenCores. \n- I will post a message to cores@opencores.org each time I have an update \n \n\n\n \n \n \n\n===== \n Change log =====\n\n- 8/2/2001 Added another feature, Directory Structure has changed\n- 6/6/2001 RU Second Release\n- 19/3/2001 RU Released Code\n- 16/3/2001 RU Initial web page \n \n\n\n \n \n This IP Core is provided by:\">\n\n===== this_ip_core_is_provided_by:\">\n This IP Core is provided by: =====\n\nThis IP Core is provided by:\">\n \n\n\nwww.ASICS.ws - Solutions for your ASIC/FPGA needs -" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rudi name: wb_dma status: Stable svn-updated: Mar 10, 2009 updated: May 22, 2007 wishbone-compliant: 1 - category: Other created: Sep 29, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: wb_fast_intercon status: Empty updated: Sep 30, 2014 wishbone-compliant: 0 - category: Memory core created: Jun 8, 2014 description: "===== \n Description =====\n\nA very generic implementation of a FIFO. Makes good use of VHDL transactors for data transfers." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: wb_fifo status: Beta svn-updated: Mar 27, 2015 updated: Feb 16, 2015 wishbone-compliant: 0 - category: Memory core created: Jun 3, 2008 description: "===== \n Description =====\n\nWishbone to Parallel FLASH interface with integral wait-state generator. This design has been used with the Intel StrataFlash Xilinx Spartan 3E Starter Kit. Provides an 8-bit data interface to the FLASH, and a 32-bit Wishbone Slave Interface with byte enables.\n\nThe StrataFlash on the S3E Starter Kit can be programmed using the PicoBlaze RS-232 StrataFlash\xE2\x84\xA2 Programmer downloadable from the following site:\n\nhttp://www.xilinx.com/products/boards/s3estarter/reference_designs.htm\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Compatible with Intel StrataFlash J3 on Xilinx Spartan 3E Starter Kit\n - Supports byte-mode operation.\n- 32-bit Wishbone Slave Interface\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested on Xilinx Spartan 3E Starter Kit" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hharte name: wb_flash status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 20, 2008 wishbone-compliant: 1 - category: Video controller created: Sep 26, 2014 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: wb_graphic status: Empty updated: Sep 28, 2014 wishbone-compliant: 0 - category: System controller created: Mar 13, 2009 description: "===== \n Overview =====\n\nLCD character display controller with Wishbone and memory mapped interfaces. \n\nIt is compatible with the following parts: Sitronix ST7066U, Samsung S6A0069X or KS0066U, Hitachi HD44780 and SMOS SED1278. \n\nIt's commonly used to drive several character displays integrated in popular Xilinx development boards such as Spartan 3E Starter Kit from Digilent." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jvillar name: wb_lcd status: FPGA proven svn-updated: Jun 14, 2009 updated: Mar 14, 2009 wishbone-compliant: 1 - category: Communication controller created: Mar 1, 2008 description: "===== \n Description =====\n\nWishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.\n\nNone of this has been tested (yet) with a third-party LPC Peripheral or Host.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Compliant to Intel(r) Low Pin Count (LPC) Interface Specification Revision 1.1\n- Wishbone Slave to LPC Host Module\n - Memory Read and Write (1-byte)\n - I/O Read and Write (1-byte)\n - Firmware Memory Read and Write (1-, 2- and 4-byte)\n - DMA support\n- Wishbone Master to LPC Peripheral Module\n - Memory Read and Write (1-byte)\n - I/O Read and Write (1-byte)\n - Firmware Memory Read and Write (1-, 2- and 4-byte)\n - DMA support\n- Serial IRQ Host and Slave Controllers\n - Supports \"Serialized IRQ Support for PCI Systems\" Rev 6.0 Specification.\n - Continuous and Quiet modes.\n - 32 interrupts supported.\n- Test bench and project file for Xilinx ISE 10.1 included.\n- Example applications (Uses the Enterpoint Raggedstone1 PCI Card) http://enterpoint.co.uk/moelbryn/raggedstone1.html\n - PCI to LPC Host Controller, with Interrupt support (uses pci32tlite core on OpenCores)\n - LPC to 7-segment display.\n- Fully static synchronous design with one clock domain \n- Technology independent Verilog \n- Fully synthesizable\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested in simulation\n- Tested in Spartan3 FPGA\n- LPC Host has only tested with LPC Peripheral bridge, not with actual LPC devices.\n- 2008-07-22: Fixed bug: Spec violation for multi-byte firmware accesses\n- Tested with LPC eVC written by Daniel Preda, which found all of the bugs in Tracker: http://www.opencores.org/people.cgi/info/danielpreda\n\n \n\n\n \n \n \n\n===== \n References =====\n\n- Intel LPC Bus Specificaton, Revision 1.1: http://www.intel.com/design/chipsets/industry/lpc.htm\n- Serialized IRQ Support for PCI Systems, Revision 6.0: http://dublintrees.com/download/serirq60.pdf\n- Implementing Industry Standard Architecture (ISA) with Intel(r) Express Chipsets (White Paper): http://www.intel.com/assets/pdf/whitepaper/318244.pdf\n- LPC Bus Information from Wikipedia: http://en.wikipedia.org/wiki/Low_Pin_Count\n- Raggedstone1 Spartan3 PCI Card details: http://enterpoint.co.uk/moelbryn/raggedstone1.html" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - hharte name: wb_lpc status: FPGA proven svn-updated: Mar 10, 2009 updated: Jan 31, 2012 wishbone-compliant: 1 - alternate-download: http://liberatedcontent.de/openhardware/wb_mcs51.v category: Other created: Mar 3, 2008 description: "===== \n Description =====\n\nInterface an 8051-compatible microcontroller with the Wishbone bus.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Multiplexed 8051 address/data bus to Wishbone Master\n- Very simple, very small.\n- Since 8051 has no way to add additional wait-states via an external pin, the Wishbone must be fast enough to complete the cycle in time for the 8051.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested with Silicon Labs C8051 Microcontroller and Xilinx Coolrunner2 CPLD.\n- Tested with Silicon Labs C8051 Microcontroller and Xilinx Spartan3 FPGA.\n- this core is used in the Altair32 Front Panel: www.altair32.com" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - hharte name: wb_mcs51 status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 25, 2008 wishbone-compliant: 1 - category: Other created: Jul 8, 2003 description: "===== \n Description =====\n\nReal Time Clock IP core with wishbone bus complaint. The RTC can transmit data to CPU as Binary Coded Decimal (BCD) values through wishbone bus. The data include the time by second, minute, hour, date, day, month, and year. It is 24-hour format. The RTC module can work with an external crystal that the frequency is not very fixed, such as 32.768kHz and so on. It also can generate two flexible interrupt requests: alarm and repetitive mode.\n \n\n\n \n \n \n\n===== \n IMAGE: structure.jpg =====\n\nFILE: structure.jpg\nDESCRIPTION: Structure of wb_rtc core\n\n \n\n\n \n \n \n\n===== \n IMAGE: ports.jpg =====\n\nFILE: ports.jpg\nDESCRIPTION: Ports of wb_rtc core\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- BCD number: second, minute, hour, date, day, month, and year;\n- Determine whether the year is leap year;\n- Year 2000 problem is removed;\n- Either analog crystal oscillator input or digital clock input, and clock input is not fixed;\n- Repetitive interrupt mode, Programmed to provide 6 different interval interrupt requests: once per second, once per minute, once per hour, once a day, once a week, once a month;\n- Alarm interrupt mode, Programmed to generate interrupt request signal when real time clock equals to the time stored beforehand in the register;\n- Written in verilog, and fully synthesisable.\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nVerilog RTL code and simulation is finished and available.\nIt was verified in an Altera APEX EP20K400E SOPC development board." language: Verilog license: unknown maintainers: - jimmy name: wb_rtc status: Planning svn-updated: Mar 10, 2009 updated: Sep 20, 2003 wishbone-compliant: 0 - category: Memory core created: Mar 16, 2009 description: "===== \n Overview =====\n\nThis IP provides a 8-bit or 16-bit bridge for a 32-bit WishBone interface. There is no buffering. The 32-bit transaction is delayed until the transaction is complete. An example using the wb_size_bridge is included that interfaces to an asynchronous memory. The asynchronous memory module has configurable setup times, hold times, and big/little endian support." language: Verilog license: LGPL2.1 licenselink: https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html maintainers: - qaztronic name: wb_size_bridge status: FPGA proven svn-updated: Mar 29, 2011 updated: Feb 4, 2010 wishbone-compliant: 1 - category: System on Chip created: Sep 25, 2001 description: "===== \n Description =====\n\nWhisboneTK is a set of IP cores designed to be compatible with the Wishbone bus\nspecification. The members of the tool-kit are general purpose building-blocks that (hopefuly) make designing Wishbone compatible\ndevices easier. The elements in the libarary are avaliable free for any kind of use .\nThe parts in the library use an extended signal-set than defined in the Wishbone interface.\nBy moving all technology-specific code to a different, underlying package, the toolkit is fairly easy to port to other technologies.\nCurrently Xilinx (XST) is the supported and tested platform though there's an Altera port included along with a generic behavioral description\nof all the technology-specific primitives that make sporting easy: Just make sure your implementation matches the behavioral model of\nthe primities and the upper layer of modules should just work.\n\n\n\nThe elements currently in the library are:\n\n Output register\n Input register\n Two-way bus arbiter\n Asyncronous (SRAM-like) slave interface\n Asyncronous master interface\n Bus resizer\n Single-port RAM\n\nThese elements are contained in the wb_tk package.\n\n\n\nThere are some procedures useful for testing Wishbone devices in the package \ntest.\n\n\n\nOther elements planned for the toolkit:\n\n FIFO buffer\nSimple DMA controller-->\nVarious DRAM (FP, EDO, SD) interfaces-->\n Timer\n UART\nSyncronous serial interface-->\n Dual-ported (shared) memory\n CACHE memory\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nCurrently in beta. Some of the cores are tested on real HW (x2s300e). Most cores are validated by simulation and all cores compile with XST 6.1." language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - tantos name: wb_tk status: Beta svn-updated: Mar 10, 2009 updated: Jun 4, 2008 wishbone-compliant: 1 - category: Other created: Feb 2, 2010 description: "===== \n Description =====\n\nA AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - qaztronic name: wb_to_amba status: FPGA proven svn-updated: Mar 29, 2011 updated: Aug 30, 2010 wishbone-compliant: 1 - category: Communication controller created: Oct 11, 2009 description: "===== \n Description =====\n\nImplements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt.\nPlease find there the documentation regarding the Uart core.\nThe interface is now compatible with a 8-bit WishBone bus.\n\nWith GHDL simulator simply run:\n./ghdl_uart.bat\n\nUsing any other simulator, before starting the simulation the following perl script must be run:\nuart_test_stim.pl > filename.txt\nwhere filename.txt is the name selected in generic \"stim_file\" inside wb8_uart_transactor.vhd.\n\nA correct simulation should exit with an assertion message \"simulation END\".\n\nThis IP is provided by IPdesign (www.ipdesign.eu)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: wb_uart status: Beta svn-updated: Oct 12, 2009 updated: Feb 14, 2010 wishbone-compliant: 1 - category: Video controller created: Sep 25, 2001 description: "===== \n Description =====\n\nWishbone Monitor Controller is a set of freely available VHDL cores. It contains a central building block containing the basic functionality. It can then be sorrounded by various helper functions to add functionality. The central core comprises of a sync generator, a pixel data generator, a memory interface and a CPU interface. It is specificly designed for slow 8-bit systems (although CPU interface size can be set) with no high needs about a display. It is also designed to be simple and small (cheap). The target is the whole design to be well fit in an Altera ACEX 1k30 device which is available for around 10USD. \n \n\n\n \n \n \n\n===== \n Individual module decriptions =====\n\nBuilding blocks\n\n Central core\n Palette RAM module\n Accelerator\n Mouse sprite module\n\nSampe configurations\n\n VGA chip\n Accelerated VGA core\n\n \n\n\n \n \n \n\n===== \n Features =====\n\nFor a fast breafing here are the main design goals and features of the various modules: \n\n- Highly customizable sync generation with polarity control \n- Capable of driving EGA/VGA/Hercules/CGA monitors \n- Multi-scan support for low resolution modes \n- Internal memory for multi-scan, for even less memory accesses \n- FIFO de-coupled memory interface and pixel output circuit \n- Wisbone pixel memory interface \n- 16-bit pixel memory support (later parametrizable) \n- Programmable color depth (1,2,4,8 bits per pixel) \n- ~80Mhz pixel clock (wish) \n- Standard parametrizable Wishbone CPU bus interface \n- Syncron internal structure \n- Fully synthesizable (using Leonardo Spectrum) \n- Palette support (3x5 bits plus key bit in each entry) \n- Accelerator functions for common display operations \n- Mouse cursor support if it fits to the chip (wish) \n \n\n\n \n \n \n\n===== \n Status =====\n\n- Central core implemented \n- Palette and Accelerator implemented \n- Cores compile under ActiveHDL and Leonardo Spectrum \n- Cores simulate well (some more validation still needed) \n- All functionality fits into a 1k30 chip \n- Synthesized central core works as expected but max. clock rate is ~60MHz \n- When all function synthesized max. clock rate is ~35MHz :-((( \n \n\n\n \n \n \n\n===== \n ToDo =====\n\n- More simulation to proove all core functionality \n- Port to other (Xilinx Spartan-II) FPGA architectures \n- Optimize design to encrease clock speed \n- Implement Mouse sprite block \n- More sample applications (complete designs) \n- Sample programs \n- Parametrizable pixel memory interface \n- Generic version for fixed configuration (even much smaller) \n- LCD support (??) \n- high-color support (??) \n- Develop a target board and try the core in real" language: VHDL license: GPL2 licenselink: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html maintainers: - tantos name: wb_vga status: Beta svn-updated: Mar 10, 2009 updated: Oct 15, 2001 wishbone-compliant: 1 - category: Processor created: Mar 4, 2004 description: "===== \n notes =====\n\nWhile the greatest percentage of the logic for this processor has been verified, there are still a copule of areas of concern.\n1) Interrupt testing should be better\n2) hazard testing should be better.\n3) There is at present not a written verification plan. \n\nGuy Hutchison (see TV80 project) has synthesized an early version of the core in a 130nm TSMC process. He determined the design to contain about 20k gates and run at about 240 Mhz. While the speed is somewhat less than \"target\", optomizations of the logic should increase this somewhat. \n\nI have synthesized the present version in Altera tools. (Stratus II) Initial resuts indicate 90 Mhz operation. I hope to be able to improve that significantly with some \nwork on the decoding logic.\n\nThis machine executes a byte instruction on each clock tick.\n\nI have noticed a significant number of downloads of the code. I do not consider present level of verification sufficient to risk use in an expensive ASIC. I would like to run a well considered (and well written) \"hazards\" test. If anyone is interested enough in the core to volunteer help with this area please let me know. \n\n10/2/2007 bugs reported by Stephen Warren and Howard Harte have been fixed and the data base has been updated. We are working on a better hazard test and a complete verification plan. \n \n\n\n \n \n \n\n===== =====\n\n\n \n\n===== \n status =====\n\nDesign document complete and in CVS\nRTL complete and built\nTestbench complete\ninitial verification phase (complete instruction test) PASSED\n \n\n\n \n \n \n\n===== \n Description =====\n\nThe purpose of the Wishbone Z80 development is to provide a \xE2\x80\x9Clow-end engine\xE2\x80\x9D (written in verilog) that could logically interface with many of the low-end verilog peripherals available to the community, while providing sufficient \xE2\x80\x9Chorsepower\xE2\x80\x9D to be used effectively with the more interesting \xE2\x80\x9Chigh end\xE2\x80\x9D peripherals. \n\nThe deign is conceived to operate efficiently with internal static RAM. Thus, a two stage pipeline is implemented to allow instruction execution at the access rate of a 32 kbyte RAM. (This could be well over 300 Mhz. depending on implementation technology.)" language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - bporcella - brewsterporcella name: wb_z80 status: Stable svn-updated: Mar 10, 2009 updated: Jun 25, 2012 wishbone-compliant: 1 - category: System controller created: Jun 22, 2008 description: "===== \n Description =====\n\nThis core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller.\n\nThe external microcontroller provides a simple 8bit interface to control some functions within the FPGA. These functions are communicating using a wishbone compatible bus within the FPGA.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 8 bit external interface to a simple parallel port of a regular microcontroller\n- two cycle external bus transfers: first address, then data\n- interrupt request flag\n- bidirectional external data port\n- wishbone compatible master interface to connect internal cores\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n2008-06-23: Specification document available" language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: [] name: wbc_parallel_master status: Alpha svn-updated: Mar 10, 2009 updated: Jun 26, 2008 wishbone-compliant: 0 - category: Other created: Dec 2, 2002 description: "===== \n Description =====\n\nThis is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 16bit Motorola DragonBall/68K Interface\n- 16bit full featured RevB.3 Wishbone Classic Master interface\n- programmable address-bus size\n- static synchronous design\n- fully synthesisable\n- 6LUTs in a Spartan-II, 32LCELLs in an ACEX\n \n\n\n \n \n \n\n===== \n Status =====\n\nDesign is finished and available in Verilog for download from OpenCores CVS." language: Verilog license: custom licensetext: "This source file may be used and distributed without\nrestriction provided that this copyright statement is not\nremoved from the file and that any derivative work contains\nthe original copyright notice and the associated disclaimer.\n\n THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\nFOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\nBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\nOF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n" maintainers: - rherveille name: wbif_68k status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 14, 2004 wishbone-compliant: 1 - category: DSP core created: Dec 13, 2011 description: "===== \n Description =====\n\nWDSP project includes three System on Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR filter core is based on the transpose realization form, the IIR filter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix 2^2 Single Delay Feedback (R2^2SDF) architecture. The three cores are compatible with the Wishbone SoC bus and they were described using generic and structural VHDL. In system hardware verification was performed by using MinSoC synthesized on an Altera FPGA, the tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.\n\nhttp://arxiv.org/abs/1402.6005" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - parrado - valdecamilo name: wdsp status: FPGA proven svn-updated: Mar 17, 2014 updated: Mar 17, 2014 wishbone-compliant: 1 - category: Communication controller created: Dec 31, 2013 description: "===== \n Description =====\n\nCommunication controller (transmitter and receiver) that operates on the Wiegand Protocol. Parity checks needed by different Wiegand-based communication protocols are done using sw drivers." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jeaander name: wiegand_ctl status: Alpha svn-updated: Mar 11, 2015 updated: Jan 2, 2015 wishbone-compliant: 1 - category: System on Chip created: Aug 6, 2007 description: "===== \n WISHBONE Protocol to AHB Protocol Bridge. =====\n\n\n \n\n===== \n Features =====\n\n- AHB 2.0 compliant\n- Wishbone B.3 compliant\n- WISHBONE Burst NOT SUPPORTED\n- Fully synthesisable\n- Synchronous\n- Verilog RTL\n- Includes a Verilog Testbench with 9 Testcases\n \n\n\n \n \n \n\n===== \n Status =====\n\n- RTL : Complete\n- Testbench : Complete\n- Document : Complete" language: Verilog license: unknown maintainers: - toomuch name: wisbone_2_ahb status: FPGA proven svn-updated: Mar 10, 2009 updated: Feb 17, 2015 wishbone-compliant: 1 - category: Processor created: Dec 20, 2007 description: "===== \n Description =====\n\nVHDL reads a file of instructions to perform Wishbone access, as if it's a wishbone master.\n\nUsed in testing a Wishbone peripheral with out having to instantiate and program a 'CPU' function\n\nThe aim is to have a text file with commands in it, which is the only bit that needs to be modified for different tests. \n\nThis test file is read in to the units, which runs the test.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- tested out with Modelsim 6.2g and Xilinx ISE 9.2 sp4\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nFirst bits of VHDL put into CVS.\n\nHave in package commands \n\nW32 and R32 for 32 bit reads and writes.\nBKW32 and BKR32 for block read and write.\nRMW32 for read modify write.\n\nTop level is wbtb_1m_1s.vhd\n\nCommands can be added to wb_master.vhd\n\nnext stage is do add a multi master capability, and to respond to bus errors and time outs.\n\nBTW: Please feel free to feed back what and how you think this should go. I can't promise to take all on board, but I'm flying blind here and making this up as I go along from scratch, with what I'd want. \n\nFeed back welcome." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - amulcock name: wishbone_bfm status: Design done svn-updated: Mar 10, 2009 updated: Feb 21, 2008 wishbone-compliant: 1 - category: System on Chip created: Jan 27, 2008 description: "===== \n Description =====\n\nAre you using Wishbone, do you need some simple 'slaves' to test your bus with ?\n\nWell, the Wishbone spec, appendix B3, has VHDL examples of Wishbone outports, and memories. \n\nThis is the code from B3 ! saves one copying the PDF each time. \n \n\n\n \n \n \n\n===== \n Features =====\n\n- Can be simulated and can be synthesised.\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nSimulated in XST 9.2 sp 4\nSynthesised to Spartan FPGA." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - amulcock name: wishbone_out_port status: Stable svn-updated: Mar 10, 2009 updated: Jan 29, 2008 wishbone-compliant: 1 - category: Memory core created: Sep 2, 2013 description: "===== \n Description =====\n\nThis module uses an interface to SPI serial FLASH memory devices to allow reading/writing/erasing of the FLASH. It includes a state machine that coordinates many of the required commands automatically, to make the process of reading and writing SPI FLASH appear as though a simple RAM is being used. Moreover, the state machine has an initialization mode which can read bytes out of the selected SPI FLASH device and present them on an 8-bit parallel output port. This initialization mode can be set up so that the module takes action immediately after reset, reading the SPI FLASH and initializing various registers in the FPGA. This is quite useful for a device that needs to be reconfigurable to behave in different ways upon power up, without actually resynthesizing the basic design.\n\nThis project was tested using the ST Micro M25P64 device. Also, the AT25DF641 data sheet was consulted. It should work with many different devices, but so far it has only been tested with the M25P64 device which is used on a Lattice Semiconductor ECP3 \"Versa\" FPGA development board. It turns out that the M25P64 device has 128 sectors of 64kbytes each, and only about the first 13 or so were being used for configuring the FPGA... So the most of the space in the device is actually available for use!\n\nThere are two SPI interfaces the VHDL file \"spi_pack.vhd\" The first one is a basic interface that can be used with any SPI device really, including things which are not FLASH. The second interface, \"spi_flash_sys_init\" is the fancy one that provides the memory mapping and system initialization sequencing.\n\nThere is a testbench which can be used to exercise the example FPGA design, showing how the initialization commands are sent as characters to the ASCII based \"async_syscon\" unit to program values from the SPI FLASH into the FPGA registers.\n\nI even wrote a simple SPI FLASH simulator to use in the testbench!\n\nThis project attempts to provide a super easy to use interface to a SPI FLASH device by mapping the contents as RAM. However, there are some caveats to remember:\n\n1. The SPI FLASH device can only work with bytes that are provided in ascending order. Therefore, the \"RAM mapped\" device should be read or written using addresses that increment by one each time.\n2. The SPI FLASH write enable (WREN) and page programming take a certain number of clock cycles to send. This makes the very first access longer than the subsequent ones. Reading bytes takes 18 system clock cycles per byte due to the way the SPI clock is generated. Therefore, each \"RAM mapped\" SPI FLASH access cycle has an acknowledge signal which indicates when the access is completed, and the cycles can be longer or shorter, depending on what is happening with the SPI FLASH. For example, the very first write cycle includes the WREN command, then the Page Program command, then the address is sent, and then the first data byte. This means that the first write cycle takes many clocks to finish. But subsequent bytes written only take 18 system clocks.\n3. There is a timer in the state machine, which is used to decide when to terminate the command session to the SPI device. So, for example, if read cycles keep coming, the timer is continuously reset. However, when reads are no longer issued for a given number of milliseconds, then the state machine terminates the read command. The next read cycle will then take longer because a new read command must be initiated, and the address must be sent again. The number of milliseconds used for the timeout is adjustable by setting a VHDL generic value.\n4. Page writes are only good within the boundaries of a single page, which is 256 bytes. You can start writing at any address within the SPI Flash address space, but as the address crosses the page boundary, it will \"wrap around\" to the beginning of the page. So when programming the device, do it in blocks of 256 bytes or less, with time in between each to allow for the programming to complete.\n5. Sector erase operations must be done through the registers, and they can take a long time, like maybe up to a second!\n\nSounds complicated, right? Well, this project *does* make it somewhat easier, since the state machine sequences through the needed commands for you automatically, so your project doesn't have to. Hopefully it will prove useful to others, as I have certainly enjoyed making it.\n\nThe design was tested at a system clock frequency of 50 MHz. It might work faster, but some SPI FLASH devices are limited in their interface speed anyway. So, try it out. Let me know if it works for you.\n\nThere is a good \"comments\" section in the code to describe the registers and what they do. Unfortunately, there is currently no other documentation provided." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jclaytons name: wishbone_spi_flash_interface status: Beta svn-updated: Sep 7, 2013 updated: Sep 7, 2013 wishbone-compliant: 0 - category: System on Chip created: May 27, 2013 description: "===== \n Description =====\n\nThis project implements the Wishbone Transaction-level Model (TLM) and Bus Functional Model (BFM) in VHDL. This enables simple communications between sub-components of an SoC system, where sub-components can perform high-level transactions to another sub-component, by using simple procedure-call statements. This greatly simplifies system integration, because sub-blocks communicate only via high-level transactions. The high-level transactor models encapsulate the lower-level BFM implementation, making the design easier to manage." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - joMojo name: wishbone_tlm_bfm status: Empty updated: Feb 19, 2014 wishbone-compliant: 1 - category: Communication controller created: May 26, 2013 description: "===== \n Description =====\n\nthis core work whit uart.\nit is used to communicate as a wishbone master, it also contains slaves.\nthese slaves are made to be a bridge between wishbone bus and I/O modules.\nthe slaves handle the wishbone signal , addresses etc. \nit can be modded to work for an 8 bit processor.\n\ninstruction set based." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - themassau name: wishbone_uart_controller status: Beta svn-updated: May 28, 2013 updated: May 27, 2013 wishbone-compliant: 0 - category: Library created: Mar 18, 2011 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - woldgreen name: woldgreen status: Empty updated: Mar 18, 2011 wishbone-compliant: 0 - category: Testing / Verification created: Dec 9, 2009 description: "===== \n Description =====\n\nFor make stimulus of testbench some times need work with files from VHDL. I think that will be very good if some different stimulus will be in one place." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - asjohnas name: workwithfiles status: Stable svn-updated: Jan 14, 2010 updated: Jan 14, 2010 wishbone-compliant: 0 - category: Communication controller created: Jun 28, 2014 description: "===== \n Concept =====\n\n\n \n\n\n \n \n \n\n===== \n Overview =====\n\nIf your projects are like ours, you always need the capability to set configuration bits for internal components, or externally monitor the status of other components. We have implemented this in many different ways across dozens of projects. We hope Wrimm is the last time we re-develop this same functionality.\n\n\n\n\n\nEvery new design needs a different set of registers. Frequently improving an existing design requires adding or changing a register which also requires some level of re-development of the register logic.\n\n\n\n\n\nThe goal of Wrimm is a fully tested logic block that doesn't change from design to design or during design revision. Everything necessary to add and configure general purpose registers is contained in constant declarations in a VHDL package file.\n\n\n\n\n\nAlong the way we also incorporated some other Wishbone functionality we frequently find useful.\n\n\n \n\n\n \n \n \n\n===== \n Capabilities =====\n\n\n\tWishbone Support - All the registers and other functions are readable and writeable via Wishbone compatible masters.\n\tParametric Wishbone Bus - Wishbone address and data bus widths are configurable with a constant setting.\n\tGlueless Interface - Wishbone masters and slaves connect to Wrimm with the standard Wishbone Interface. All required glue logic is automatically generated inside Wrimm.\n\tParametric Register Configuration - The bit size and address locations for all the following register types are configurable in the project package file. Register fields of different types may even share the same address (in different bit locations).\n\t\tSetting Registers - Setting registers offer bit vector outputs to provide configuration to non-Wishbone modules.\n\tStatus Registers - Status registers offer bit vector inputs to collect status information from non-Wishbone modules and provide that data via Wishbone reads.\n\tTrigger Registers - Trigger registers are single bit registers used to launch other non-Wishbone on-chip processes. The triggers are then cleared by those functions.\n\tWishbone Record Type Interfaces - The multi-signal wishbone interface is represented in two custom record types for a shorter, cleaner interface.\n\tMulti Wishbone Master Support - Any number of masters can be connected. Round robbin arbitration is provided for all masters.\n\tTBD- Multi Wishbone Slave Support - Any number of wishbone slaves may be attached to the Wrimm component. Partial address decoding support is provided. Data, Ack, Rty, and Err signals are automatically muxed together to respond to the master with the grant.\n\tTBD- Wishbone Reset Support - Automatically drive Rst when requests go unanswered.\n\tAdaptive Testbench - Test bench also uses constant data from the package file to enable testing of the project specific configuration.\n\t100% Synthesizeable VHDL - All custom configuration is done in VHDL no other scripting language or intermediate compilation is required.\n\n\n \n\n\n \n \n \n\n===== \n Documentation =====\n\nAll documentation outside this brief description is contained in WrimmManual.pdf.\n\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nWrimm provides Wishbone interconnect functionality, multi-master arbitration, multi-slave partial address deccoding and bus multiplexing. Wrimm also incoporates configurable register bits for controlling and monitoring non-Wishbone functions." language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - barryw name: wrimm status: FPGA proven svn-updated: Jul 28, 2014 updated: Jul 27, 2014 wishbone-compliant: 1 - category: Other created: Oct 28, 2013 description: "===== \n Description =====\n\nHave you ever wanted to add some color to your project? Then this might be your answer. The WS2812 RGB LED \"pixels\" and WS2811 driver ICs are available for an encouragingly low cost from various sites on the internet, and they come in strips which can be cut or joined to the desired length. Since the Red/Green/Blue (RGB) LEDs inside the WS2812 part are driven by the serial driver IC which is also inside the part, only three wires are needed, and your project can set each LED color independently of the others.\n \nThe connections to the LED strip include 3 wires: +VCC, GND, and data. It turns out that these LEDs will work over a pretty wide supply voltage range. The ones I got said 4-7VDC, but I've found that they work pretty well using +3.3V as the supply voltage!\n \nThe format of the serial data stream used to drive the LEDs is given in the comments inside the VHDL code, and it can also be found by browsing the internet. For those who don't read Chinese (myself included) there is now a data sheet available in English! The color settings are 8-bits for each color, for a total of 2^24 combinations.\n \nThe VHDL module in this project was recently used in a Lattice Semiconductor FPGA. However, it does not include architecture specific macros, so it should be easy to use on any given FPGA or CPLD. It is parameterized so that the user can determine how many LEDs to drive.\n \nThe color data is provided to the module by an input data bus, using an address to select which LED and which color is being loaded.\n \nMy VHDL coding style uses the \"unsigned\" type instead of the \"std_logic_vector\" type. It is easy to translate between the two using functions in \"convert_pack.vhd\", or you can go through and modify the code to use std_logic_vector instead." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jclaytons name: ws2812 status: Beta svn-updated: Nov 6, 2013 updated: Nov 1, 2013 wishbone-compliant: 0 - category: Communication controller created: Oct 4, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - jeaander name: xbus status: Empty updated: Oct 5, 2013 wishbone-compliant: 0 - category: Coprocessor created: Aug 1, 2009 description: "===== \n Description =====\n\nThe Xgate Co-processor Module, Xgate, is a 16 bit programmable RISC processor that is managed by a host CPU to reduce the host load in handling interrupts. Because the Xgate is user programmable there is a great deal of user control in how to preprocess data from peripheral modules. The module may be configured as a simple DMA controller to organize data such that the host only deals with whole messages and not individual words or bytes. The Xgate may also deal with higher levels of messaging protocols than the peripheral hardware recognizes. Encryption algorithms are also supported by the instruction set.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\xE2\x80\xA2\tInstruction set compatible with Freescale XGATE co-processor\n\xE2\x80\xA2\tHandles up to 127 interrupt inputs\n\xE2\x80\xA2\tEight software triggerable interrupt channels.\n\xE2\x80\xA2\tEight semaphore registers to coordinate host/Xgate shared memory.\n\xE2\x80\xA2\tStatic synchronous design\n\xE2\x80\xA2\tFully synthesizable\n\n \n\n\n \n \n \n\n===== \n Status =====\n\nVerilog Code: 85%\nDocumentation: 60%\n\nPlease see the \"News\" tab for more detailed information or the README file in the \"trunk\" SVN directory." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - rehayes name: xgate status: Alpha svn-updated: Jan 27, 2013 updated: May 22, 2012 wishbone-compliant: 1 - category: Communication controller created: Nov 15, 2012 description: "===== \n Description =====\n\nThis is a fork of the xge_mac and was released by the Computer Architecture Group (http://cag.uni-hd.de) of the University of Heidelberg.\n\nMain changes in this fork:\n-Unwanted FIFOs removed\n-Latency reduced due to the removal of the FIFOs and a new CRC implementation\n-Interface very similar to the one of the Xilinx MAC\n\nThis core is in production use." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - cleberCAG name: xge_ll_mac status: Stable svn-updated: Dec 1, 2012 updated: Dec 1, 2012 wishbone-compliant: 0 - category: Communication controller created: May 19, 2008 description: "===== \n Description =====\n\nThe 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n1. Interfaces\n - XGMII Interface (64-bit single clock edge)\n - POS-L3 like Interface for core logic side\n - Wishbone Interface for control\n2. Inter-Frame GAP\n - Deficit Idle Count per Clause 46\n3. Pause Frames\n - Received Pause Frames filtering\n - Receive Indication\n4. LAN mode operation\n5. Link Status\n - Local Fault Detection\n - Remote Fault Detection/Indication\n6. Latency\n - Low-latency flow-through mode (120ns TX, 160ns RX)\n\n \n\n\n \n \n \n\n===== \n Release Notes =====\n\n1. Some issues reported with synthesis of FIFO's in Xilinx. Recommend using XIL define.\n \n\n\n \n \n \n\n===== \n Status =====\n\n- (05/31/2008) Verilog code completed\n- (06/06/2008) SystemC and Verilog simulations completed\n- (03/06/2009) Validated in Altera FPGA running traffic against other MAC\n- (03/06/2009) Validated interfacing to external 10GE PHY using XAUI links\n- (12/13/2009) Changed packet interface to big endian\n- (12/13/2009) Added SERDES examples to tb_xge_mac.v\n- (2/7/2012) Updates for Xilinx synthesis\n- (2/15/2012) Core user reported passing traffic in Xilinx FPGA\n- (11/23/2012) Design improvements for timing\n- (11/23/2012) Added XIL define option for FIFO synthesis with Xilinx\n- (11/23/2012) Added a prototype System Verilog testbench (not for general use)\n- (11/25/2012) Added basic packet statistics. Timing improvements. Reduced FIFO size.\n\n \n\n\n \n \n \n\n===== \n Future Developments =====\n\n- RMON Statistics\n- Store-and-forward mode" language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - antanguay - protik name: xge_mac status: FPGA proven svn-updated: Jan 26, 2013 updated: Apr 20, 2013 wishbone-compliant: 1 - category: Arithmetic core created: Sep 4, 2013 description: "===== \n Description =====\n\nPlease write a description of the project here. It is used as a MetaTag (search engines looks at this)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - bigsascha3 - constantina_elena name: xilinx_virtex_fp_library status: FPGA proven svn-updated: Feb 28, 2014 updated: Sep 19, 2013 wishbone-compliant: 0 - category: Other created: Mar 4, 2006 description: "===== \n Benefits of data compression =====\n\nThe use of lossless data compression can bring about a number of increasingly important benefits to an electronic system. The term \xE2\x80\x98lossless\xE2\x80\x99 means that the original data can be exactly recreated after a decompression operation, and should not be confused with audio and video compression systems (such as JPEG and MPEG) which are lossy and hence only recreate an approximation of the original data. \nThe most obvious benefit of data compression is a reduction in the volume of data which must be stored. This is important where the storage media itself is costly (such as memory) or other parameters, such as power consumption, weight or physical volume, are critical to product feasibility. Using data compression \nreduces the total storage requirement, thus effecting a cost saving. \n\nThere are also two other positive effects that data compression brings. The first of these is a reduction in the bandwidth required to transmit a given amount of data \xE2\x80\x93less data must be transmitted when in compressed form, and hence less bandwidth is required. This can effect a cost saving in cabling operations, where a lower bandwidth link will be sufficient to meet demand. The second effect is that given a fixed bandwidth, the total time required to transmit compressed data is less than for uncompressed data. This can lead to a performance benefit, as the bandwidth of a link appears greater when transmitting compressed data and hence more data can be transmitted in a given amount of time. \n \n\n\n \n \n \n\n===== \n X-MatchPROvw design architecture =====\n\nThe X-MatchPROvw compressor/decompressor processor is a fully contained unit having a simple architecture and uncomplicated interface.\n\nThe X-MatchPROvw design is a dictionary style compressor based around a dictionary implemented in the form of a content addressable memory (CAM). The length of the physical CAM varies with values ranging from 16 to 1024 tuples (4-byte locations) trading complexity for compression. Typically, the device complexity increases by a factor of 1.5 each time the dictionary doubles. The physical dictionary size is, then, variable to be able to adapt algorithm complexity to the resources available in the selected FPGA. The logical length of the dictionary always starts at zero (empty) and grows as new data needs to be accomodated. The logical width of the dictionary also adapts to the data input ranging from 2-bytes up to 4-bytes to improve compression. \n\nThe dictionary adaptively stores the most recent phrases that have occurred in the data stream. Compression is achieved by replacing repeated phrases with references to the dictionary (these are codewords witch are sorter than the phrase itself). A number ot techniques such as partial matching and internal run length coding are used to improve compression.\n\nThe coding section is active during compression. This generates the required codewords and forms successive codewords into fixed 32-bit width words for writing to external medium. The decoding section is responsible for the reverse process \xE2\x80\x93data is read from the external medium and generates the required dictionary references to allow the decompressed data to be recreated. The process is fully lossless and the compression process is automatically verified using CRC codes. \n \n\n\n \n \n \n\n===== \n Features and Applications =====\n\nFeatures\n\xE2\x80\xA2 New version targets Xilinx V4/V5 devices at 100 MHz and 140 MHz respectevely. Throughput of 400 Mbytes/second and 560 Mbytes/second in these devices.\n\xE2\x80\xA2 High-speed lossless data compressor supports compression and decompression in a single FPGA. \n\xE2\x80\xA2 Altera APEX20KE prototype implementation available on PCI board. \n\xE2\x80\xA2 Throughput up to 200 Mbytes/second compression/decompression with low latency clocking at 50 MHz on a APEX FPGA. Higher on Stratix or Virtex-4 devices.\n\xE2\x80\xA2 Full-duplex operation enables simultaneous compression/decompression for a combined performance of 400 Mbytes/s. \n\xE2\x80\xA2 Full-duplex architecture enables self-checking test mode using CRC (Cyclic Redundancy Check) codes. \n\xE2\x80\xA2 32-bit high-performance coprocessor-style interface. \n\xE2\x80\xA2 Fully contained 32-bit architecture does not require any external components and supports operation on blocked data. \n\xE2\x80\xA2 Easy migration to ASIC technology enables 3-5 times increase in performance. \n\xE2\x80\xA2 Compression ratio comparable to HiFn LZS and IBM ALDC using comparable dictionary sizes. \n\nApplications \n\xE2\x80\xA2 Computer systems. \n\xE2\x80\xA2 Networking products. \n\xE2\x80\xA2 High performance storage devices. \n\xE2\x80\xA2 Data logging equipment. \n\xE2\x80\xA2 Remote sensing applications. \n\nTo learn more contact us at j.l.nunez-yanez@bris.ac.uk.\n\nThe opencores version is generic and can target different FPGA and ASIC technologies. A optimized version for Xilinx Virtex-7/Zynq devices in the form of a PCORE can be obtained at seis.bris.ac.uk/~eejlny" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - eejlny name: xmatchpro status: FPGA proven svn-updated: Sep 19, 2009 updated: Sep 15, 2014 wishbone-compliant: 0 - category: Crypto core created: Apr 7, 2006 description: "===== \n Description =====\n\nThis is a Verilog implementation of the XTEA block cipher. It works on two 32-bit blocks of data at a time with a 128-bit key.\n\nA proper OpenCores specification for this unit will be written at some point. Wishbone compliance is also on the TODO list.\n\nThis implementation was adapted from the public domain C release of the algorithm from David Wheeler and Roger Needham by David Johnson. It is licensed under the GNU Lesser General Public License.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- a very small, efficient implementation\n- fast\n- secure\n- what more do you need?\n \n\n\n \n \n \n\n===== \n Current Stable Release =====\n\nThe current stable release is version 1.0.\n\nThis release has seperate encipher/decipher units. A test-bench is available and included in the download. Version 1.0 is not licensed under the LGPL - it is public domain.\n\nEach unit accepts data in data_in1 and data_in2 and a key in key_in. The all_done wire is raised when the results of the operation are ready to be read from data_out1 and data_out2. They need to be reset before each use.\n\nThis release has been FPGA-proven on an Altera Stratix EPS1S10F672C6-ES running at 25.175MHz. Higher clock speeds have not been tested.\n\nPlease report back if you get the design up-and-running (especially if you get it running as an ASIC) or if you have it running at a higher clock speed.\n\nNote: the download page doesn't appear to be working at the moment, but you can grab the release from CVS.\n \n\n\n \n \n \n\n===== \n Current SVN Snapshot =====\n\nOriginally the project was split into seperate encipher/decipher units, but these have now been combined into a single unit. The test-bench has not yet been updated for the new combined unit.\n\nThe unit accepts data in data_in1 and data_in2, a key in key_in and the mode in mode (1 for encipher, 0 for decipher). The all_done wire is raised when the results of the operation are ready to be read from data_out1 and data_out2. It needs to be reset before each use.\n\nThis combined unit, as of yet, has not been tested." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - dj1471 - drewboud name: xtea status: FPGA proven svn-updated: Mar 10, 2009 updated: Jul 21, 2010 wishbone-compliant: 0 - category: Crypto core created: Jul 25, 2013 description: "===== \n Description =====\n\nVHDL implementation of the XTEA block cipher (iterative architecture)." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - entactogenic name: xteacore status: Stable svn-updated: Jul 27, 2013 updated: Jul 27, 2013 wishbone-compliant: 0 - category: System on Chip created: Dec 31, 2014 description: "===== \n Description =====\n\nA simple 16-bit microprocessor together with a simple bus system. It utilises the Xilinx dual port ram features to be able to fetch instructions and use data memory at the same time. It is defined using RISC principles, featuring a small instruction set and overlapping execution. It is not completely pipelined. A first estimate gives a CPI of 2.2. Using a small memory a clock speed of 160 MHz is achievable on a Spartan-6 device with speed grade 2. Using larger memory will slow down the system due to net delays. The goal is to always release a simulator, an assembler and the core at the same time. The reason for this is that the instruction set will certainly change due to the development, implementation and measurement of the system software.\n\nMy own goals for this system are:\n\n* Obtaining experience with building a microprocessor\n* Have a target platform to develop a small Lisp system\n* Have the possibility to develop and hook up IO devices without being bothered with a modern complex processor\n* Offer a platform to other computer enthusiasts, comparable in complexity with the ZX Spectrum or the Commodore 64\n\nExperimental refers to the fact that this SoC is used to experiment with VHDL, microprocessor, microprocessor architecture, and unstable to the fact that the instruction set will change in the future, based upon program measurements.\n \n\n\n \n \n \n\n===== \n History =====\n\nWhy yet another microprocessor (system) core?\n\nThis project grew out of two interests, microprocessors and Lisp (both Common Lisp and Scheme).\n\nI got interested in microprocessors in 1980, in Lisp around 2004. That was also the time I started experimenting with simulating microprocessors using software. A first design was completed from 2006 to 2007 when I simulated a self-designed 12-bit microprocessor at the signal level using the equivalent of MSI level components. Part of the design included a micro-program assembler and an assembler.\n\nFrom 2008 to 2009 I was busy with implementing Scheme in Perl, learning from SICP. I started and stopped different projects for building microprocessors. From 2010 to 2012 I went back to school to get my master's degree in electronic engineering. Here I learnt VHDL. In this time I also acquired an Atlys board for doing my thesis. Around the same the company where I was, restructured, and I took the time to build another Lisp interpreter, but this time on top of a C engine. This provided me with some guiding lines on the kind of microprocessor I needed to build. This led to the definition of the ISA and the building of a simulator in Common Lisp. Hardware development started in July 2013.\n\nThe first VHDL simulation of the processor ran on Xilinx WebPack in October 2013. However, I was dissatisfied with the performance. I wanted to improve this by means of partial overlapping of instruction decoding and execution. The new implementation ran on 15 December 2014 and was mostly validated on 27 December. However, at that date a CALL and RET instruction were still missing, together with an interrupt scheme." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - lcdsgmtr name: xucpu status: Design done svn-updated: Apr 22, 2015 updated: Jan 25, 2015 wishbone-compliant: 0 - category: Processor created: May 27, 2013 description: "===== \n Description =====\n\nZ80/Z180 compatible processor softcore. Based on Y80 project described in the book 'Microprocessor Design Using Verilog HDL' of Monte Dalryple from Systemyde. If you want to understand internals of CPU then this book may greately help you to do it.\n\nThis CPU supports commonly used Z80 undocumented instructions: operations with halfs of index registers and SLI/SLL (Shift Left Logical). Optionally it supports emulation of R register.\n\nAdditionally CPU is Z180 compatible. Supported all IO, MLT (implemented via standard Verilog multiplication) and TST instructions.\n\nMoreover, it has all non-ADL instructions from Zilog eZ80 CPU:\nIND2, IND2R, INDM, INDMR, INDRX,\nINI2, INI2R, INIM, INIMR, INIRX,\nLD (HL),rr\nLD (ii+d),rr\nLD rr,(HL)\nLD rr,(ii+d)\nLEA rr,ii+d\nOUTD2, OTD2R, OTDRX\nOUTI2, OTI2R, OTIRX\nPEA ii+d\n\nii - IX, IY\nrr - BC, DE, HL, IX, IY\n\nCompiled for Altera Cyclone III FPGA. It consumes 2557 logical cells." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - bsa name: y80e status: Stable svn-updated: May 28, 2013 updated: May 29, 2013 wishbone-compliant: 0 - category: Arithmetic core created: Mar 2, 2014 description: "===== \n Description =====\n\nCORDIC is the acronym for COordinate Rotation DIgital Computer and allows a hardware efficient calculation of various functions like\n - atan, sin, cos\n - atanh, sinh, cosh,\n - division, multiplication. \nHardware efficient means, that only shifting, additions and substractions in combination with table-lookup is required. This makes it suitable for a realization in digital hardware. Good introductions can be found in [1][2][3][4].\n\n\n\nThe following six CORDIC modes are supported: \n- trigonometric rotation\n- trigonometric vectoring\n- linear rotation\n- linear vectoring\n- hyperbolic rotation\n- hyperbolic vectoring\n\nFurthermore, the CORDIC algorithm is implemented for iterative processing which means, that the IP-core is\nstarted with a set of input data and after a specific amount of clock cycles, the result is\navailable. No parallel data can be processed.\n\nIn addition to an IP-core written in VHDL, a bit-accurate C-model is provided. This C-model can be compiled as mex for a usage with Octave or Matlab. Therefore, this C-model allows a bit-accurate analysis of the CORDIC performance on a higher level.\n\n\n\n\n\n\n\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- C-model implementation is done \n- RTL model implementation is done \n- RTL model is verified against C-model \n\n\n \n\n\n \n \n \n\n===== \n Open issues and future steps =====\n\nThe next steps are \n\n - Add YAC to a FPGA based System-on-Chip to prove FPGA feasibility \n - Circuit optimizations \n - Numerical optimizations \n \nand the future plans are \n\n - Hyperbolic range extension \n - Floating point CORDIC \n\n \n\n\n \n \n \n\n===== \n Bibliography =====\n\n[1] Andraka, Ray; A survey of CORDIC algorithms for FPGA based computers, 1989 \n[2] Hu, Yu Hen; CORDIC-Based VLSI Architectures for Digital Signal Processing, 1992 \n[3] CORDIC on wikibook: http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC \n[4] CORDIC on wikipedia:http://en.wikipedia.org/wiki/CORDIC \n[5] David, Herbert; Meyr, Heinricht; CORDIC Algorithms and Architectures \n http://www.eecs.berkeley.edu/newton/Classes/EE290sp99/lectures/ee290aSp996_1/cordic_chap24.pdf" language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - feddischson name: yac status: Design done svn-updated: Mar 30, 2014 updated: Mar 30, 2014 wishbone-compliant: 0 - category: Processor created: Apr 22, 2005 description: "===== \n Description =====\n\nYACC (Yet Another CPU CPU) is MIPS I (TM) subset cpu written in Verilog-2001 HDL. YACC has 5 pipeline and shows 110 DMIPS in stratix2 with synthesized allowable clock of 165MHz. It is independent design of plasma, although YACC uses gcc-elf-mips tools provided by Steve Rhords, author of plasma (Most mips written in VHDL).\nThe core was developed by using my Simulator, with post layout gate simulation, and tested by actual FPGAs, using Xilinx spartan3 starter kit and Cyclone by Altera,running 800 digits of pi calculation ,(255,223) Reed Solomon Error Correction ,and Interactive calculator written by C language.\n \n\n\n \n \n \n\n===== \n Disclaimer =====\n\nMIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. MIPS Technologies, Inc. does not endorse and is not associated with this project. Tak.Sugawara is not affiliated in any way with MIPS Technologies, Inc.\n\n \n\n\n \n \n \n\n===== \n Legal =====\n\nI have no idea if implementing this core will or will not violate\npatents, copyrights or cause any other type of lawsuits.\n\nI provide this core \"as is\", without any warranties. If you decide to\nbuild this core, you are responsible for any legal resolutions, such\nas patents and copyrights, and perhaps others ....\n\nTHIS SOURCE FILE(S) IS/ARE PROVIDED \"AS IS\" AND WITHOUT ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT\nLIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND\nFITNESS FOR A PARTICULAR PURPOSE.\n \n\n\n \n \n \n\n===== \n Background =====\n\nWhen I was developing VHDL to Verilog translator , I found plasma core in opencores. It is excellent work to learn a lot. After I translated plasma written by VHDL to Verilog HDL almost automatically using my Translator, I stated to design my own CPU per following target spec.\n\n-works with free C compiler ->use plasma resources \n-pretend to be fast (Dhrystone benchmark test requires only 16KB memory! Actually ..) \n-5 stage pipeline \n-use dual port memory in FPGA \n-works with Altera/Xilinx FPGAs \n-with minimum logic cells in FPGA" language: Verilog license: custom licensetext: "I have no idea if implementing this core will or will not violate \npatents, copyrights or cause any other type of lawsuits. \n\nI provide this core \"as is\", without any warranties. If you decide to \nbuild this core, you are responsible for any legal resolutions, such \nas patents and copyrights, and perhaps others .... \n\nTHIS SOURCE FILE(S) IS/ARE PROVIDED \"AS IS\" AND WITHOUT ANY \nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT \nLIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND \nFITNESS FOR A PARTICULAR PURPOSE.\n" maintainers: [] name: yacc status: FPGA proven svn-updated: Mar 10, 2009 updated: Apr 25, 2005 wishbone-compliant: 0 - category: Memory core created: Aug 1, 2008 description: "===== \n Description =====\n\nSUPERSEDED BY HPDMC.Please do not ask me about this core! It is old and totally unsupported. HPDMC support, however, is available from the Milkymist-devel mailing list." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - lekernel name: yadmc status: Stable svn-updated: Aug 7, 2010 updated: Aug 7, 2010 wishbone-compliant: 0 - category: Communication controller created: Jun 10, 2009 description: "===== \n Overview =====\n\nYANU (Yet Another Niosii Uart) has been built from scratch with the efficiency in mind in term of CPU load. A complete uCLinux TTY driver has been developed.\nIts main feature is that it has a TX and and RX FIFO buffers with a predictive \"event to interrupt\" generation.\nThis will lead to a lower CPU usage needs in high efficiency point to point communication links at high baud rates.\nIt has a fractional prescaler so that almost any baud rate can be generated from any input clock frequency.\nIt detects all the common asynchronous errors (Parity,Framing,Overrun).\nIt is programmable in terms of hardware handshake, number of bits and stop bits; it can generate break conditions, etc...\nIt has an Avalon compliant bus interface and it has been tested successfully in Altera FPGAs (average logic block usage is 330 logic cells in CycloneIII family)." language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - renato_andreola name: yanu status: FPGA proven svn-updated: Jun 15, 2009 updated: Oct 17, 2009 wishbone-compliant: 0 - category: Video controller created: Mar 20, 2009 description: "===== \n Description =====\n\nThis core is a simple and small VGA controller.\n\n\n\n\n\n\nIt drives vga monitors with an 800x600 resolution\nand 72Hz vertical refresh rate (50MHz pixel clock)\nIt displays chars on the screen (each char is 8x16 pixels)\nIt has a customizable charset (you can use a simple text editor in order to \"visually\" customize it)\nIt can display a color \"waveform\"\nIt can display a color grid and \"cross cursor\"\n\n\n\n\n\n\nClick the image in order to see a full size screenshot: \n\n\n\n\nYAVGA ported to Papilio board by Gadget Factory\n\n\n\n\n\n\nVGA Connector Example\n\n\n\n\n \n\n\n \n \n \">\n\n===== \">\n =====\n\n\">" language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - sandroamt name: yavga status: FPGA proven svn-updated: May 19, 2009 updated: Apr 14, 2012 wishbone-compliant: 0 - category: Processor created: Dec 12, 2001 description: "===== \n IMAGE: ys_logo.jpg =====\n\nFILE: ys_logo.jpg\nDESCRIPTION: Yellow Star Logo\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nIt is capable of executing 32bit instructions based on the MIPS R3000 microprocessor instruction set and has been tested running large blocks of compiled C code.\nFully functional and compatible interrupt system. Can handle all exceptions cleanly and correctly.\nTwo 2Kbyte (Data and Instruction) direct mapped caches with coherency.\nMemory management unit with 64 Entry TLB fully compatible to original design.\nDesigned in Powerview package but can be distributed in hierarchical schematic EDIF\nWarning: The manual stated instructions SWL, SWR, LWL and LWR which are not implemented. And there are known bugs in the code.\nFor more information go to http://brej.org/yellow_star/\nThe processor was created using schematics and there is NO RTL VHDL or Verilog.\n \n\n\n \n \n \n\n===== \n Features =====\n\n- 32 entry 32bit Register bank created out of Ram blocks to save space\n- 5 Stage pipeline\n- Two 2Kb caches\n- 64 Entry CAM TLB\n- Exact exception handling\n- One coprocessor\n \n\n\n \n \n \n\n===== \n Status =====\n\n- Tested running all instructions that are implemented.\n- Tested and running correctly at 50MHz\n- Memory menagement and caching buggy\n- Looking for good schematic entry people to take control of the project\n- Looking for people to convert the project files to other platforms\n \n\n\n \n \n \n\n===== \n Legal =====\n\nFree for commercial and non-commercial use as long as the author and warning notices are maintained. \n\nThis software is provided by Charlie Brej \"as is\" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage.\n\nMIPS(R) and R3000(R) are registered trademarks of MIPS Technologies, Inc. in the United States and other countries. OpenCores and Charles Brej are not affiliated in any way with MIPS Technologies, Inc." homepage: http://brej.org/yellow_star/ language: Verilog license: unknown maintainers: - brejc8 name: yellowstar status: Stable svn-updated: Mar 10, 2009 updated: Jul 8, 2013 wishbone-compliant: 0 - category: Processor created: Nov 29, 2014 description: "===== \n Description =====\n\nA Verilog implementation of the Infocom Z-Machine V3. The spec the Z3 follows is http://inform-fiction.org/zmachine/standards/z1point0/index.html. Specifically version 3, the so called \"Standard\" games. These were released between 1982 and 1987 and covers most Infocom games. Z3 passes the \"CZECH - Comprehensive Z-machine Emulation CHecker\" by Amir Karger. And is known to run at least Zork I, Hitchhiker's Guide to the Galaxy, Planetfall and Curses (by Graham Nelson).\n\nThe following YouTube video shows it in action: http://www.youtube.com/watch?v=HuQZq6DQQDY\n\nTo provide the input/output a terminal is implemented in a BIOS (in Z-machine code) which exists in the ROM above 120Kb. The IO related opcodes (like @print) vector into the BIOS which provides the terminal. A small number of extra op codes were added so the BIOS could interface with an LCD touchscreen and access the top 64Kb of RAM (which shadows the ROM).\n\nSave/Restore isn't currently supported (as my hardware hasn't any storage) and is the only notable omission." language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - charcole name: z3 status: Stable svn-updated: Nov 30, 2014 updated: Nov 30, 2014 wishbone-compliant: 0 - category: Processor created: Sep 27, 2010 description: "===== \n Description =====\n\nMicroprocessor targeting embedded industrial control systems. Uses a z80 core available at opencores as T80. It is in early development stages. It is currently being developed with a Altera Cyclone II FPGA Starter Board (DE1). The idea is to have a system that will communicate to a PLC and a PC via serial interface. This allows the ability to expand peripherials on a PLC while giving the user PC control from a visual enviroment using custom software." language: VHDL license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - tylerapohl name: z80control status: Alpha svn-updated: Oct 2, 2010 updated: Dec 1, 2012 wishbone-compliant: 0 - category: System on Chip created: Apr 16, 2008 description: "===== \n Z80 System on Chip =====\n\nSystem on chip, based on T80 core.\n\nThis project is a SOC designed for Altera DE1 development board and the Diligent Spartan 3E, and provide access to leds, switches, buttons, IO pins, SRAM, VGA, LCD and keyboard using Z80 assembly language.\nComes with a reference ROM application that show how to access all resources on the board. Spartan 3E port provides easy access to the LCD (memory mapped, 32 bytes of ram).\n\nThere are tools included in the project files to convert fonts (psf) to MIF and COE, and convert files containing hex codes in VHDL ROM files, what makes it very easy to generate new roms for the system (requires cygwin on windows or linux/unix shell).\n\nThere is a home page for this project here:\nhttps://sites.google.com/site/z80soc\n\n\nMore information about development here: http://opencores.org/pnews.cgi/list/z80soc\n \n\n\n \n \n \n\n===== \n Features =====\n\nAll board resources are accessible from Z80 Assembly programs and also using C language.\n\nV0.7.1\n- Main change is support for C with release of a basic C library interface with the board resources\n- Bugfixes in the video design and support for 80x60\n\nV0.7\n- Video layout can now be up tp 80x40\n- Characters are stored im RAM and can be redefined by the user\n\nFeatures:\n\nDE1:\n- Memory\n - 24 Kb RAM (external SRAM) for main memory\n - 03 Kb RAM for video memory (display up to 80x40)\n - 02 Kb RAM for characters (256 chars), can be redefined by user\n - 16 Kb ROM \n- VGA video out in text mode configurable up to 80x40\n- PS/2 keyboard input\n- Seven segment display\n- 8 Green leds\n- 8 Red leds\n- 8 Switches\n- 4 Push buttons\n- 36 IO pins (gpio0)\n- 36 IO pins (gpio1)\n\nSpartan 3E:\n- Memory\n - 24 Kb RAM for main memory\n - 03 Kb RAM for video memory (display up to 80x40)\n - 02 Kb RAM for characters (256 chars), can be redefined by user\n - 16 Kb ROM\n - 32 Bytes RAM for LCD video memory\n- VGA video out in text mode configurable up to 80x40\n- PS/2 keyboard input\n- LCD display \n- 8 Green leds\n- 4 Switches\n- 5 Push buttons\n- Rotary Knob\n\n \n\n\n \n \n \n\n===== \n Status =====\n\n- All features listed are now functional\n\n- Future improvements under way:\n - (done) Video 80x40\n - Serial communication\n - Monitor program\n\n \n\n\n \n \n \n\n===== \n Revison History =====\n\nFor a detailed list of changes and features, see file RevisionHistory.txt and README file.\n\n2010/02/26 - V0.7\nModified RAM layout to accomodate new features\nCharacters definition are now in RAM and can be redefined by the user\nVideo screen can now be configured up tp 40 rows by 80 columns\nCharacters can have double pixels (useful when width is less than 40 chars)\nMemory cores was redefined, RAM is now 24K\n\n2008/05/24 V0.6\nModified RAM layout to support new and future improvements. \nAdded ports 0x90, 0x91, 0x92 for vram write\nChanged ROM to support 14 bit addresses (16 Kb)\n\n2008/05/14\nAdded support for the Rotary knob on Spartan 3E.\nModified the ROM to move LCD text using the Rotary knob.\n\n2008/05/12\nFixed bug in memory access for S3E. ROM now is almost the same as DE1.\n\n2008/05/05\nSpartan 3E port released, with support for the LCD display.\n\n2008/05/01\nAdded Caps lock support. Upper and lower case characters are now supported for keyboard input.\n\n2008-04-19 \nAdded complete character set (video out only)\nChanged ROM program\n\n2008-04-16\nRelease of Z80SoC-0.5-DE1-Beta" homepage: https://sites.google.com/site/z80soc/ language: VHDL license: unknown maintainers: - rrred name: z80soc status: Stable svn-updated: Nov 24, 2010 updated: Nov 23, 2010 wishbone-compliant: 0 - category: Memory core created: Oct 17, 2008 description: "===== \n Description =====\n\nThis is a ZBT SRAM controller which is Wishbone rev B.3 compatible (classic + burst r/w operations). \n\nPLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.\n\nIt has been simulated and verified on a Xilinx Virtex-5 FPGA board of type ML-506.\n\nThis core is Wishbone compliant, using registered feedback cycles. \n\nThe only quirk is that, in burst operations, the \"wb_tga_i\" input must be '0' during the last (or single) 4 words burst (the last four clock cycles, being the fourth the one in which wb_cti = \"111\" indicates the WB end of burst).\n\nIn short: keep \"wb_tga_i\" low unless you want to read 4 more words in another burst immediately following the current one.\n\nThis is necessary in order to make the perfect overlap between ZBT read/write burst cycles and Wishbone's registered feedback cycles.\n\nIt is fully functional, but any bug reports are very welcome.\n\nIn the next image a typical multiple burst operation is shown (it's the same for read/write, so wb_we_i, wb_dat_i, wb_dat_o are omitted for clarity), where 12 words are read from memory, which means 3 bursts of 4 words each.\n\n1.- In the first cycle (the first one where wb_cti_i=\"010\") signals wb_cyc_i, wb_stb_i, wb_adr_i, wb_we_i and wb_dat_i (for writes) are set.\n\n2.- As we are going to read/write 3 bursts (of 4 words each), the wb_tga_i signal must be at '1' during the first two bursts.\n\n3.- Don't change any signals until wb_ack_o rises.\n\n4.- When wb_ack_o = '1' then increment wb_adr_i every cycle.\n\n5.- (This is the only step not in the WISHBONE specs.) After the first two bursts are done, lower the wb_tga_i signal in order to signal the ZBT SRAM Controller that the last burst starts now.\n\n6.- In the last cycle wb_cti_i must be \"111\" to signal a Wishbone end of burst and, after that, wb_cyc_i and wb_stb_i must be lowered (or stay risen in order to initiate a new transaction).\n\nThe fifth step is the only one not in the WB specs. for registered feedback cycles. The rest are normal operation as defined in the specifications.\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- This core differs from others at OpenCores in that it makes the best overlap between Wishbone registered feedback burst cycles and the ZBT SRAM burst R/W cycles, so that the fastest access (a continuous burst) can be achieved.\n\n- Also Wishbone classic cycles can be used (for single word R/W) although the core wasn't optimized for them (i.e.: for a read, it takes three wait cycles to output a single word).\n \n\n\n \n \n \n\n===== \n Status =====\n\n- 17/10/2008: I'll upload the source and testbench in a few days (after cleaning it up a bit ;)\n- 30/10/2008: Source code uploaded (pending to do a nice Wishbone documentation)\n\n\nThis core has been developed under a project of the Spanish Ministry of Science.\n\n \n\n\n \n \n \n\n===== \n FILE: ZBTSRAM61NLP_NVP25636A_51218A.pdf =====\n\nFILE: ZBTSRAM61NLP_NVP25636A_51218A.pdf\nDESCRIPTION: Datasheet for ISSI IS61NLP ZBT SRAM (used in Xilinx ML506 board)\n\n \n\n\n \n \n \n\n===== =====" language: VHDL license: CC BY-NC-SA 3.0 licenselink: http://creativecommons.org/licenses/by-nc-sa/3.0/ maintainers: - galland name: zbt_sram_controller status: FPGA proven svn-updated: Mar 10, 2009 updated: Sep 4, 2009 wishbone-compliant: 1 - category: Processor created: Jul 6, 2011 description: "===== \n Description =====\n\nzCore is designed at PWRSemi, a startup try to develop clean-room PowerPC processor for consumer market. Now The unfinished product is open-sourced and licensed under GPLv2.\n\nFor source download, please visit: https://groups.yahoo.com/neo/groups/openzcore/info" homepage: https://groups.yahoo.com/neo/groups/openzcore/info language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - kissfang name: zcore status: Empty updated: Oct 23, 2014 wishbone-compliant: 0 - alternate-download: https://github.com/ama142/ZedboardOLED-v1.0-IP/archive/master.zip category: Other created: Aug 22, 2014 description: "===== \n Description =====\n\nThe ZedboardOLED IP core provides a user friendly interface to the 128x32 organic LED display available on the Zedboard development board, a driver is supplied with the package, enabling a standalone usage for the display. The design can be easily modified to target other embedded platforms, provided with the package, a step-by-step quick start guide for using the IP.\n \nFeatures\n1 Plug and play using Vivado design suite.\n2 Hierarchical open-source design, it can be easily altered to fit other systems\xE2\x80\x99 requirements.\n3 Internal display buffer.\n4 English characters bit maps are cached inside the controller.\n5 Implemented driver for alphanumeric display .\n \nThis work was done as part of teaching materials for the ECEN 449 class offered at Texas A&M University/Qatar.\nWritten by Ali Aljaani/Texas A&M University at Qatar.\nhttps://github.com/ama142/ZedboardOLED-v1.0-IP" homepage: https://github.com/ama142/ZedboardOLED-v1.0-IP language: Verilog license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - ama1421 name: zedboardoled status: Stable updated: Aug 23, 2014 wishbone-compliant: 0 - category: Processor created: Jul 3, 2008 description: "===== \n Description =====\n\nThe Zet SoC PC platform and processor is an open implementation of the so widely used x86 architecture. This project is being developed using four different FPGA boards: Xilinx ML-403, Altera DE0, Altera DE1 and Altera DE2-115 boards. Currently it's in a very early stage of development and only the 16 bit part is supported. The official website for the project is: zet.aluzina.org.\n\nSome features of the Zet SoC PC system include:\n\n16 bit Zet processor equivalent to an Intel 80186, running at 25 Mhz (Wishbone compatible)\nWishbone ZBT SRAM memory controller addressing 1 Mb of low memory\nWishbone flash memory controller for BIOS storage (ROM BIOS and VIDEO BIOS)\nVideo Graphics Adapter in text mode and 640x480,640x350,320x200 16 colors and 320x200 256 colors in chain 4 representation\n8253 simple timer, sending interrupts each 18.2 Hz via IRQ 0\n8042 keyboard controller sending PC/XT scancodes via IRQ 1\nUART support as COM1, using IRQ 4\nVery simple interrupt controller.\nFlash memory controller for floppy disk storage\nCompact Flash card controller for hard disk emulation with full read/write support\nSD card controller for hard disk emulation with full read/write support\nGPL implementation of a PC BIOS with several services implemented: \ninterrupts 8h, 9h, 10h, 11h, 12h, 13h, 16h, 18h, 19h, 1Ah, 1Ch\n\nUseful links to the project page:\n\nMain project page\nSome pictures of the system\nDiscussion forums\nInstallation guides for the Xilinx ML403 and Altera DE1\nSource code of the Zet system v1.3.0 (in tar.bz2 format)\nSource code of the Zet system v1.3.0 (in zip format)\nGIT development tree: git://github.com/marmolejo/zet.git\n\n \n\n\n \n \n \n\n===== \n News =====\n\n\n4-Nov-2013. Version 1.3.0 released! We have a new board, the Altera DE2 and the video memory has been placed on SDRAM, making the DE0 able to run Windows. You can see the complete change in the forums post.\n\n10-Nov-2010. Version 1.2.0 released!! A lot of new changes added. Two new FPGA boards now supported: Altera DE0 and Altera DE2-115. PS2 mouse support, new optimized BIOS with shadow RAM, new Zet opcodes added, system timer and speaker, new UART core and a lot of bug fixes!!\n\n1-Feb-2010. It's time to play games like Dune 2, Gods or Lemmings!! Three VGA graphical modes have been added: 640x350, 320x200 with 16 colors and 320x200 with 256 colors in chained four representation. Some other major improvements have been added: increased x8 SD card access speed, high performance memory controller, wishbone switch and asynchronous bridges added." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - zeus name: zet86 status: FPGA proven svn-updated: Apr 30, 2009 updated: Nov 4, 2013 wishbone-compliant: 1 - category: Arithmetic core created: Mar 1, 2013 description: "===== \n Intro =====\n\nZopfli Compression Algorithm is a new zlib (gzip, deflate) compatible compressor.\n\nThe output compresses by Zopfli is typically around 5% better (smaller) than zlib (at maximum compression) and better than any other zlib-compatible compressor we have found. \n\nBecause software implementation of this algorithm takes ~100x slower then zlib, need creation of hardware implementation Zopfli compressor coprocessor.\n\nIt is a compression-only implementation; existing tools can decompress the data. Zopfli is bit-stream compatible with compression used in gzip, zip, png, etc." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: [] name: zopfli status: Empty updated: May 23, 2014 wishbone-compliant: 0 - category: System on Chip created: Jun 23, 2010 description: "===== \n Status =====\n\nThis project is in the early planning stage. I am collecting documentation for both busses and beginning to understand them, and refining the specifications. I'm collecting tools for design and test and preparing a development environment on my computer. I'm currently taking a VHDL course at university, and thus will plan to have both Verilog and VHDL versions of this bridge. Progress on this design will hopefully pick up this summer 2012.\n\n\nI intend to use as many freely available tools as possible, and will have some learning curve to be productive with them. I'm fairly familiar with simulating in Simvision, but I'd like to be doing this project with Icarus Verilog and GTKWave or Dinotrace instead, which I have never used before... I'm also interested in Verilator, but sounds like I'd need to learn SystemC for testbench stuff in that, and I'd also like to see things run in gplcver.\n\n\nI've decided to make the RTL and any Makefiles, scripts, etc. in this project to be LGPL 2.1 or later. I'd pondered making documentation for this project under GFDL, but after discussions in various forums, I'm now planning for documentation (specs, test plans, etc) to be under LGPL 2.1 or later as well. While I'm told I can separate the two portions of this project into different licenses, it could forbid deriving any documentation from RTL etc. While I don't at the moment plan to derive docs from RTL or Makefiles, I might as well make it easy to do that if I change my mind, so the whole shebang will now be LGPL 2.1 or later.\n\n\nI've started working on a specification document in OpenOffice. I'm hoping to do a decent document before I get lost in RTL coding and find myself hacking around more than should be, even as I don't expect this to be a hugely complex project. Surprusingly I've had a couple people ask about this project, unfortunately I'm still trying to find time to work on a spec. I've not yet written any RTL, I'd really like to do a spec first, and that will apparently take a while to get through. I'd love to have this done and up, but for now there's not yet anything worth looking at. I am getting a little better understanding of Wishbone's burst cycle styles and the PCB adapters I need for my FPGA on a PCI card to test in an Amiga Zorro slot. \n\n\nSurprisingly the 124 pins PCI bus (yes I knew there are key \"pins\" that maybe shouldn't count) does not have enough signal pins to make up a 100pin Zorro slot. I believe the 25x2 header on my FPGA board should be able to complement the PCI edge to fill in the missing places. Unfortunately those pins are shared with the AvBus P4 connector, which may or may not conflict with the memory and communications modules I'd like to put there. Regardless I'll need to add quickswitches as it looks like the 25x2 is unbuffered to the FPGA pins. I'll probably put some additional things on the 25x2 part of the Zorro adapter for IDE, SCSI, maybe a couple other things to maximize what I can possibly use there.\n \n\n\n \n \n \n\n===== \n Source Code =====\n\nTo check out the SVN trunk for this project:\n[code]svn co http://opencores.org/ocsvn/zorro_to_wishbone_bridge/zorro_to_wishbone_bridge/trunk [/code]\n\nIn Eclipse, using Subversive Plugin:\nURL = http://opencores.org/ocsvn/zorro_to_wishbone_bridge/zorro_to_wishbone_bridge\nfill in your opencores.org login info\nchoose trunk or whatever to check out to your new project.\n\n \n\n\n \n \n \n\n===== \n Description =====\n\nThis project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at the same time on the same bus. I suppose this will really end up being two bridges, one for each direction. \n\n\nI am learning Verilog RTL for SoC/ASIC design and testbench simulation at work, and I think this will be an interesting \"other than my day job\" project to gain more experience with Verilog coding, tools, FPGA boards and FPGA tools. I also think that the Amiga in an FPGA community will benefit from gaining access to the numerous Wishbone peripheral cores here at opencores.org. \n\n\nThis project will be based on Zorro bus documentation as found in\n\n the Commodore Amiga A3000T Service Manual\n the Commodore-Amiga Inc. Zorro III Bus Specification rev 1.10\n the Commodore Amiga A500/A2000 Technical Reference Manual\n the Commodore-Amiga Inc. Amiga Hardware Reference Manual 3rd Edition\n and other service manuals that seem relevant in my collection.\n\n\n\nThis project will bridge to/from Wishbone Rev.B4, taking advantage of as many B4 features as makes sense for the old ZorroII/ZorroIII protocols.\n\n\nFor those interested in using this to fit a Wishbone peripheral into a Zorro host, you will need to obtain an Autoconfig Manufacturer ID if you do not already have one. (Please, please, do not hijack IDs belonging to someone else. Lets do this right, even if so many are no longer active) Contact Olaf Barthel to obtain an official Manufacturer ID. (I need to ask how he would prefer to be contacted for this, but he can be found on utilitybase now and then when the site is working, but use NoScript or something like it is recommended to avoid the site vandals). For those interested in connecting Zorro peripherals to a Wishbone host, you will not need an Autoconfig ID set, as the bridge intends to be a transparent interface to the Zorro bus protocols, not to be a \"known peripheral\" itself.\n\n\nWhy not just have an Autoconfig ID set for the bridge itself? Well, what the OS drivers really need to know is what peripherals are out there, not how they are connected. One designer might use this bridge to connect a Wishbone IDE controller. Another may connect a Wishbone Ethernet MAC. Another may connect a Wishbone DDR memory controller. And another may connect a combination of things. Your ID set tells the system what all peripherals are on your board, via some level of the hardware device tree. Knowing which board this is lets the firmware/OS determine what peripherals are there, where they are in address space, and then it can connect appropriate chip/device drivers. I would hope that any such products will use a board/chip style driver system as demonstrated by Picasso96 graphics card API. This would allow a single driver to be used for common peripharal IPs, regardless of who's board they are on, or what other things are configured with it on the other side of each particular bridge. I don't know the general Amiga expansion API well enough to say if this is already the case or no tin general, or just in certain cases. It may or may not be the way things are already for your particular driver needs.\n\n\nThere are three possible uses for this bridge:\n\n\n as a Zorro slave peripheral card plugged into an Amiga motherboard Zorro slot\n as a Zorro bus master peripheral card plugged into an Amiga motherboard Zorro slot\n as a Zorro system controller on some motherboard which is in control of that motherboard's various Zorro slots (ie. it watches all busmaster acknowledge signals from all slots, sends busmaster grant signals to all slots, determines which acknowledge to send and when, etc. which are beyond a peripheral busmaster card's responsibilities) This is the mode which will be interesting to people wanting to add Zorro slots to the open-sourced MiniMig Amiga in an FPGA project as one example, as the system needs more control capabilities than a busmaster peripheral does. This is also the mode of interest if anyone wishes to create a replacement for Commodore's SuperBuster system bus controller chip.\n\n\n\nI plan to implement this bridge in three main phases, following the three usage modes as they seem to go in a nice order of complexity and build on previous modes:\n\n\n Phase 1:\n Implement Zorro II / Zorro III slave peripheral mode to Wishbone master bus. This allows connecting a Wishbone slave peripheral to a Zorro host system. (Zorro slaves may be able to DMA into the host system under direction from the host system driver software, but will not be able to request control of the bus)\n \n Phase 1a will be ZorroII host/master to Wishbone peripheral/slave\n Phase 1b will be ZorroIII host/master to Wishbone peripheral/slave\n \n \n\n\n Phase 2:\n Implement Zorro II / Zorro III busmaster peripheral mode to Wishbone slave bus. This allows connecting a Wishbone master bus/peripheral to a Zorro slave. This should allow two uses:\n \n Wishbone master peripheral on a Zorro busmastering peripheral plugin card, inserted into a Zorro host system.\n \n Phase 2a ZorroII host to Wishbone master peripheral\n Phase 2b ZorroIII host to Wishbone master peripheral\n \n Wishbone host system can use one, possibly multiple Zorro slave peripheral plugin cards, but no Zorro busmastering peripheral plugin cards. (busmaster capable Zorro cards should work fine as slaves, and may be able to DMA into the host system under direction from the host system driver software, but will not be able to request control of the bus due to lack of Zorro bus arbitration logic)\n \n Phase 2c Wishbone host to ZorroII master peripheral\n Phase 2d Wishbone host to ZorroIII master peripheral\n \n \n \n\n\nPhase 3:Implement Zorro II / Zorro III system bus controller mode, which adds in Zorro bus arbitration logic. This will allow a Wishbone host system full use of all Zorro slave and busmaster peripheral plugin cards to request control of the bus and DMA into the host system. It's possible that this may be little more than pairing Phase 2 with an existing OpenCores or other suitable arbiter. I think it should be desirable to reuse as much existing IP as possible. (with compatible licensing of course)\n\n\n\n\nTesting of this core will utilize an Avnet Xilinx\xC2\xAE Spartan\xC2\xAE-3 Evaluation Kit, which is a PCI card format eval/development system including a Xilinx Spartan 3 XC3S1500 FPGA device.\n\n A small adapter board will allow the 100pin Zorro edge connector to fit onto this FPGA board's PCI edge connector when testing slave and busmaster peripheral modes in an Amiga 3000 desktop and/or A4000T computer. Host Amiga computer will use a SuperBuster rev 11 system bus controller chip to control its Zorro bus. I need to verify that the PCI edgecard on my Spartan3 board can be treated this way, or if the onboard levelshifting groups prohibit direct Zorro slot compatibility.\n Another adapter board will be made to provide a connection to an Amiga 4000 desktop computer's Zorro backplane daughterboard, possibly also the Amiga 3000 desktop computer's equivalent if supporting both is reasonable. This easily provides for a number of Zorro slots while reducing PCB board design on my part. Testing in this mode will likely include aoOCS and porting the MiniMig, DragonBall/68K Wishbone interface, and ao68000 or ae68 cores to my evaluation board. This combination should give me a Wishbone Minimig core attached to a Wishbone CPU, everything in verilog, where the traditionally Minimig-paired TG68 is a VHDL non-Wishbone CPU. A single HDL language should make life easier on me, as will existing Wishbone CPU and interface to Minimig's 68000 bus. Again I need to verify that the level shifting groupings on the Spartan3 board allow direct Zorro bus connection.\n Any adapter PCBs will be open-sourced as part of this project, and will be in Eagle schematic/board file format." language: Verilog license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - amigabill - Eriond - yannv name: zorro_to_wishbone_bridge status: Planning svn-updated: Jan 11, 2012 updated: Mar 9, 2012 wishbone-compliant: 1 - category: Processor created: Jan 2, 2008 description: "===== \n The worlds smallest 32 bit CPU with GCC toolchain =====\n\nRead about some of the professional uses of the ZPU: http://www.zylin.com/zpuexpertise.html\n\nThe ZPU is a small, portable CPU core with a GCC toolchain and eCos RTOS support. \n\nThe ZPU has a FreeBSD license for the HDL and GPL for the rest. This allows deployments to implement any version of the ZPU they want without running into commercial problems, but if improvements are done to the architecture as such, then they need to be contributed back. \n\nOne strength of the ZPU is that it is tiny and therefore easy to implement from scratch to suit specialized needs and optimizations.\n\nThe ZPU is under git version control(opencores will probably get git source control eventually), meanwhile more information, complete source and more examples can be found at http://opensource.zylin.com/zpu.htm\n\nPer Jan 1. 2008, Zylin has the Copyright for the ZPU, i.e. Zylin is free to decide that the ZPU shall have a BSD license for HDL + GPL for the rest.\n\nSincerley,\n\n\xC3\x98yvind Harboe\nGeneral Manager\nhttp://www.zylin.com\n\n \n\n\n \n \n \n\n===== \n Features =====\n\n- Small size: 442 LUT @ 95 MHz after P&R w/32 bit datapath Xilinx XC3S400 \n- Verilog and VHDL implementations available\n- Wishbone\n- Code size 80% of ARM Thumb\n- GCC toolchain(GDB, newlib, libstdc++)\n- FreeRTOS support\n- eCos embedded operating system support\n \n\n\n \n \n \n\n===== \n Hello world example =====\n\n1. download the latest svn snapshot http://www.opencores.org/download,zpu\n\n2. tar -xzvf zpu_latest.tar.gz\n\n3. In zpu/readme.txt you find information on how to run a\nhello world ModelSim example. \n\n4. Run the simulation in ModelSim, this outputs a log.txt which prints\n\"Hello world\".\n\n5. Modify hello.c, rebuild and run in ModelSim(also described in readme.txt)\n\nOther smoketests:\n\nLook in the example/simzpu_small.do simulation file and use zpu_small_core.vhd as the top level file in your synthesis software. You'll then need to pull in zpu_config.vhd, hello_world.vhd, and zpupkg.vhd. You now have a standalone ZPU that can be used to smoketest synthesis and do some crude resource measurements relatively easily in just about any synthesis software. Adjust zpu_config.vhd to use DontCareValue='X' and maxAddrBitBRAM to fit the RAM you want to assign to the ZPU for your synthesis test.\n\nNormally such synthesis GUI/IDE's should allow you to pick some FPGA part and choose some default pins for the top level ZPU. This will allow you to run some smoketest on synthesis and get a feel for timing constraints, size, etc. after place and route.\n\nThis will either \"just work\" as the hello_world.vhd uses inference to implement BRAM's, or you will have to implement a dual port RAM according to the FPGA architecture and synthesis software requirements. You may run into some small hickups with certain synthesis software, such as Synplify where you need to tweak the ZPU code to complete synthesis.\n\nIf you modify the ZPU, it is possible to run a verification procedure against larger applications to check that the modifications do not introduce subtle bugs.\n \n\n\n \n \n \n\n===== \n Download =====\n\nThe ZPU source is kept in a git repository rather than CVS(OpenCores.org does not yet support git).\n\nhttp://opensource.zylin.com/zpudownload.html\n\n\nThe OpenCores CVS server contains a snapshot of the source code before it was moved to git." homepage: https://github.com/zylin/zpu language: VHDL license: custom licensetext: "The license for HDL implementations is FreeBSD to be\nfriendly towards commercial projects and other open source\nprojects, however the architecture, documentation and tools will be GPL.\n\nThis means that all updates to the architecture must be shared, but actual\nimplementations(which are small and can be very project speific) can\nbe friendly towards commercial considerations.\n\nPatches to update files w/correct licensing info will be most appreciated!\n\nThe ZPU and all the files are per 1/1-2008 Copyright Zylin AS, i.e.\nZylin is free to decide upon the BSD license for HDL implementation\nand GPL for architecture, tools and documentation.\n" maintainers: - oharboe name: zpu status: FPGA proven svn-updated: Sep 8, 2009 updated: Sep 14, 2009 wishbone-compliant: 1 - alternate-download: http://www.alvie.com/zpuino/download.html category: System on Chip created: Apr 8, 2011 description: "===== \n Description =====\n\nZPUino is a SoC (System-on-a-Chip) based on Zylin's ZPU 32-bit processor core.\n\nHardware-wise, ZPUino currently integrates the following devices:\n\n * ZPU Premium Core, a modified ZPU core\n * One UART\n * Two SPI interfaces\n * Two 16-bit timers\n * One TSC (Time Stamp Counter)\n * 128-bit GPIO interface\n * Interrupt Controller\n * Two SigmaDelta outputs\n * Peripheral Pin Select (optional)\n\nSoftware-wise, it supports the following features:\n\n * 4Kb Bootloader, which includes required emulation code for ZPU.\n * Bootstraps code from program flash (shadows into FPGA blockram)\n * Serial programming of program flash.\n\nWhere does it run ?\n\nFirst implementation was done on Spartan3E 500 (-4), on a S3E Starter Kit, with a M25P16 SPI flash ROM and 32Kbytes RAM.\n\nRight now it runs on other boards, see Reference for more information.\n\nRunning speed: up to 100MHz, 96MHz recommended\n\nMore information and downloads at http://www.alvie.com/zpuino/" homepage: http://www.alvie.com/zpuino/ language: VHDL license: BSD licenselink: https://en.wikipedia.org/wiki/BSD_licenses maintainers: - alvieboy name: zpuino status: FPGA proven updated: Apr 9, 2011 wishbone-compliant: 0 - category: System on Chip created: Feb 5, 2015 description: "===== \n Description =====\n\nztachip is a framework for software + HDL development on a SOC-FPGA device. SOC-FPGA are chipsets that incorporate a fabric of re-configurable hardware logic combined with a standard multi-core processor.\n\nIt is possible to realize many orders of magnitudes in performance increase if one can leverage the re-configurable capabilities of these chipsets by optimizing the data processing and data flow for a particular application need.\n\nUnfortunately programming for these chipsets are particular challenging since it requires a familiarity of both hardware(HDL) and software design flow.\n\nztachip solution involves the following concepts:\nReduce data latency impact by de-coupling/overlaying data-transfer and data-processing.\n\nMinimize data usage and transfer by substituting traditional caching at each processing unit with a global data engine and global caching. Data transfers are done in concurrent with data processing tasks.\n\nMinimize processing delay impact through the use of hard-multithreading.\n\nProvides simple interface for software to interact with special custom hardware blocks.\n\nSimilar to a GPU architecture, ztachip is composed of a large array of processing units called pcore. Since ztachip design does not need data caching at each core, these pcores are very simple and light.\n\nPrograms are written in standard C with few extensions/restrictions.\n\nImplementations show 100x acceleration for matrix multiplication when compared with program running on ARM host processor.\n\nztachip is free to use and distribute for both commercial and non-commercial applications under the Apache License v2.0 term. (which is mostly equivalent to LGPL)\n\nFor download and more information, please visit our website at ztachip.sourceforge.net" homepage: http://ztachip.sourceforge.net/ language: VHDL license: LGPL licenselink: https://www.gnu.org/copyleft/lesser.html maintainers: - vuongdnguyen name: ztachip status: Alpha updated: Feb 5, 2015 wishbone-compliant: 0 - category: Video controller created: Apr 23, 2012 description: "===== \n Description =====\n\nThis is an implementation of the Sinclair ULA chip, found in ZX Spectrum microcomputers. The project offers various implementations: both FPGA friendly (with separate input and output data buses), and CPLD ready, to be used as a replacement for the many chips that comprise the ULA found in some clones.\n\nThis project is mostly based upon the work of Chris Smith. Chris designed a ZX Spectrum clon, the \"Harlequin\". A PCB has been developed by Don \"Superfo\", which uses discrete logic to implement the ULA, as Chris did. The CPLD version of this implementation is aimed to serve as replacement for that clone.\n\nThe ULA implementation follows, where possible, the original ULA timmings, as stated in \"The ZX Spectrum ULA: how to design a microcomputer\", written by Chris Smith and published by ZX Design and Media, ISBN 978-0-9565071-0-5\n\nThere are implementations with some enhancements such as Timex hicolour support and ULA+ support.\n \n\n\n \n \n \n\n===== \n Features =====\n\n\nCPLD (XC95144/288XL) version, with shared data bus, designed for the Harlequin clone.\nFPGA (separate input and data buses, mostly synchronous, but I cannot aassure that) version, intented for soft SoC.\nTo test the FPGA version, several clones have been built around this ULA core. See directory branches/xilinx. These clones are ready to be used in the Spartan 3 Starter Board, both 200K and 1000K gate versions.\nAll timmings according to Chris Smith's specs. Yet to be tested against a real Z80 for timming accuracy (tv80 core seems not to have exact timmings, but this could be my fault, not tv80's)\nDigital IRGB output, PAL timmings. Same signals as found in the 128K heatsink RGB DIN connector, that is, bright component separated from main components.\n8 bit digital RGB output for ULA+ mode. Output signal indicate whether ULA is in normal or plus mode.\nEAR, MIC and SPK pins\nFPGA version adds the 8-pin row connector for keyboard matrix. See xilinx/ directory for design examples.\nTimex Hicolor mode supported in the FPGA version of the core.\nULA+ implemented in the FPGA version of the core.\n\n \n\n\n \n \n \n\n===== \n Videos =====\n\nVarious ULA timming tests.\n\n\n\n\nTesting a ZX Spectrum clone running at 7MHz CPU clock speed. Part I.\n\n\n\n\nTesting a ZX Spectrum clone running at 7MHz CPU clock speed. Part II.\n\n\n\n\nTesting the Timex hicolor mode on a ZX Spectrum ULA enhanced clone.\n\n\n\n\nTesting the Timex hicolor and ULA+ mode with a slideshow.\n\n\n \n\n\n \n \n \n\n===== \n Images =====\n\n\nSpartan 3 Starter Board connections for running this clone. RGB signal has separate bright (I) component, so you will need to mix the bright signal before entering the TV/monitor. Usually this is performed by a RGB cable compatible with the 128K heatsink Spectrum, so you will need a female DIN-8 socket and wire it accordingly with your cable (UK or Investronica).\nKeyboard connections are not needed with PS2 enabled clones.\n\n\n\n\n\n\nZX Spectrum design in a Digilent Spartan 3 Starter Board. Real matrix keyboard version.\n\n\n\n\n\n\nZX Spectrum clone built around an earler version of the ULA design. This shows the working screen of the first program from the Horizons demo tape (spanish version), the one that teaches the hardware of the Spectrum. Can you name the differences between the elements depicted on screen and the actual hardware that's running them? :D\n\n\n\n\n\n\n\n\n\nThe Overscan demo running in the clone. This is the PS2 enabled keyboard clone version. The PS2 keyboard uses the spanish mapping. English mapping will be ready very soon.\n\n\n\n\n\n\nAquaplane, showing a perfect full screen horizon)\n\n\n\n\n\n\nShock Megademo, part 2. This part is very sensitive to interrupt, ULA and Z80 timmings, so it's a perfect test.\n\n\n\n\n\n\nDark Star. This game features a graphic drawn in the border area. For this to be showed correctly, both interrupt timmings and ULA timmings have to be perfect.\n\n\n\n\n\n\nHicolor Timex demo screen. The \"Videos\" section features this demo. A new enhanced ULA description which supports this mode has been uploaded to the fpga_version directory. NOTE: only the hicolor mode is supported. The hires mode or the dual screen mode of the Timex TC2048/2068 is not supported.\n\n\n\n\n\n\nThe Gioconda, displayed in the ULA+ & Time HiColor enabled clone. This picture belongs to the new slideshow \"Famous pictures\" that you can find at the \"software/ulaplus_demos\" directory in the SVN repository.\n\n\n\n\n\nIf you want to build one of these clones, but you doesn't have a fancy FPGA trainer board, Joseba Epalza Ramos, from INGEPAL, has sucessfully adapted a Spectrum clone to work entirely within the FPGA in the OLS (no external SRAM required). Of course, this means that this clone cannot have a 16K ROM and at least 16K of RAM, which is the minimum specification for a Spectrum, but there were ROM versions of various games available at the time. Some of these versions were made to fit an 8K ROM chip (cheaper than a 16K ROM). Thus, Joseba's clone features a ROM game (Space Raiders, from Psion Software Ltd) embedded in 8K of block RAM, leaving the rest (16K) to build the first 16K of RAM, including of course, the video RAM.\n\n\n\n\n\n\nThe clone, showing B/W video: just mix the three RGB signals with weight resistors to get a grayscale signal, which in turn is mixed to the sync signal to get a monocrome video signal you can use to feed the AV INPUT of any TV or video capture device.\n\n\n\n\n\n\nThe same clone, now using a proper RGB output.\n\n\n\n\n\n\nCloseup of the wiring needed to adapt the digital IRGB signals to analog RGB signals. This scheme is the same as shown at the Paul Farrow site\n\n\n\n\n\n\nConnection diagram for this clone\n\n\n\n\nA ZX Spectrum clone built on top of the Gameduino shield by Don \"Superfo\". Don has added a piggy-back board that connects to the Gameduino.\n\n\n\n\n\n\nBottom view of above design. The Gameduino has footprints to solder either a 512KB SRAM memory, or a 32MB SDRAM. This design uses the SRAM approach.\n\n\n\n\n\n\nThe piggy-back board includes an EAR signal conditioner, so loading from iPhone or MP3 players is not an issue :)\n\n\n\n\n\n\nThe core is almost the same as used for the ULAplus+Timex Hicolor supported core. Both are available at the project's repository.\n\n\n\n\n\nA schematic for the piggy-back board is also available." language: Verilog license: GPL licenselink: https://www.gnu.org/licenses/gpl.html maintainers: - mcleod_ideafix name: zx_ula status: FPGA proven svn-updated: Jan 6, 2013 updated: Jan 6, 2013 wishbone-compliant: 0