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Architecture pia_arch of work.pia6821

Defined in VHDL/pia6821.vhd

Author: John E. Kent
Version: 0.2 from 2010-08-09


Detailed description

Implements a 6821 like PIA with 2 x 8 bit parallel I/O ports with programmable data direction registers and 2 x 2 bit control signals.


Libraries and global use clauses

library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all

Processes

pia_read ( addr, cs, irqa1, irqa2, irqb1, irqb2, porta_ddr, portb_ddr, porta_data, portb_data, porta_ctrl, portb_ctrl, pa, pb )
pia_write ( clk, rst, addr, cs, rw, data_in, porta_ctrl, portb_ctrl, porta_data, portb_data, porta_ctrl, portb_ctrl, porta_ddr, portb_ddr )
Write I/O ports
porta_direction ( porta_data, porta_ddr )
direction control port a
ca1_input ( clk, rst, ca1, ca1_del, ca1_rise, ca1_fall, ca1_edge, irqa1, porta_ctrl, porta_read )
CA1 Edge detect
ca2_input ( clk, rst, ca2, ca2_del, ca2_rise, ca2_fall, ca2_edge, irqa2, porta_ctrl, porta_read )
CA2 Edge detect
ca2_output ( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
CA2 output control
ca2_direction ( porta_ctrl, ca2, ca2_out )
CA2 direction control
portb_direction ( portb_data, portb_ddr )
direction control port b
cb1_input ( clk, rst, cb1, cb1_del, cb1_rise, cb1_fall, cb1_edge, irqb1, portb_ctrl, portb_read )
CB1 Edge detect
cb2_input ( clk, rst, cb2, cb2_del, cb2_rise, cb2_fall, cb2_edge, irqb2, portb_ctrl, portb_read )
CB2 Edge detect
cb2_output ( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
CB2 output control
cb2_direction ( portb_ctrl, cb2, cb2_out )
CB2 direction control
pia_irq ( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
IRQ control

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