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Entity work.XSASDRAMCntl

Defined in System09_base/xsasdramcntl.vhd

Author: Dave Vanden Bout
Version: 1.1.0 from 05/17/2005


Detailed description

Customizes the generic SDRAM controller module for the XSA Board.

Architectures

arch

Instantiated in...

work.my_system09 (rtl)

Libraries and global use clauses

library IEEE
use IEEE.numeric_std.all
use IEEE.std_logic_1164.all
library UNISIM
use UNISIM.VComponents.all
use WORK.common.all
use WORK.sdram.all

Generics

FREQ natural := 100_000
CLK_DIV real := 2.0
PIPE_EN boolean := false
MAX_NOP natural := 10000
MULTIPLE_ACTIVE_ROWS boolean := false
DATA_WIDTH natural := 16
NROWS natural := 8192
NCOLS natural := 512
HADDR_WIDTH natural := 24
SADDR_WIDTH natural := 13

Ports

clk instd_logic
host side
bufclk outstd_logic
host side
clk1x outstd_logic
host side
clk2x outstd_logic
host side
lock outstd_logic
host side
rst instd_logic
host side
rd instd_logic
host side
wr instd_logic
host side
earlyOpBegun outstd_logic
host side
opBegun outstd_logic
host side
rdPending outstd_logic
host side
done outstd_logic
host side
rdDone outstd_logic
host side
hAddr instd_logic_vector(HADDR_WIDTH-1 downto 0)
host side
hDIn instd_logic_vector(DATA_WIDTH-1 downto 0)
host side
hDOut outstd_logic_vector(DATA_WIDTH-1 downto 0)
host side
status outstd_logic_vector(3 downto 0)
host side
sclkfb instd_logic
SDRAM side
sclk outstd_logic
SDRAM side
cke outstd_logic
SDRAM side
cs_n outstd_logic
SDRAM side
ras_n outstd_logic
SDRAM side
cas_n outstd_logic
SDRAM side
we_n outstd_logic
SDRAM side
ba outstd_logic_vector(1 downto 0)
SDRAM side
sAddr outstd_logic_vector(SADDR_WIDTH-1 downto 0)
SDRAM side
sData inoutstd_logic_vector(DATA_WIDTH-1 downto 0)
SDRAM side
dqmh outstd_logic
SDRAM side
dqml outstd_logic
SDRAM side

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