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Synthesizable Enhance Parallel Port
Defined in VHDL/epp.vhd
Author: John E. Kent
Version: 0.2 from 2010-08-09
library ieee | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_unsigned.all | |
library unisim | |
use unisim.vcomponents.all |
clk | in | std_logic | |
CPU Interface Signals | |||
rst | in | std_logic | |
CPU Interface Signals | |||
cs | in | std_logic | |
CPU Interface Signals | |||
rw | in | std_logic | |
CPU Interface Signals | |||
addr | in | std_logic_vector(2 downto 0) | |
CPU Interface Signals | |||
data_in | in | std_logic_vector(7 downto 0) | |
CPU Interface Signals | |||
data_out | out | std_logic_vector(7 downto 0) | |
CPU Interface Signals | |||
irq | out | std_logic | |
CPU Interface Signals | |||
hold | out | std_logic | |
CPU Interface Signals | |||
epp_stat | in | std_logic_vector(7 downto 3) | |
Parallel Port Interface Signals | |||
epp_ctrl | out | std_logic_vector(3 downto 0) | |
Parallel Port Interface Signals | |||
epp_data | out | std_logic_vector(7 downto 0) | |
Parallel Port Interface Signals |