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Entity work.trace

Synthesizable Hardware Trace Capture

Defined in VHDL/trace.vhd

Author: John E. Kent
Version: 0.2 from 2010-08-09

Architectures

trace_arch


Libraries and global use clauses

library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all

Generics

BUFF_SIZE integer := 9
DATA_WIDTH integer := 8

Ports

clk instd_logic
rst instd_logic
cs_r instd_logic
cs_b instd_logic
rw instd_logic
addr instd_logic_vector((2*DATA_WIDTH)-1 downto 0)
data_in instd_logic_vector(DATA_WIDTH-1 downto 0)
data_out outstd_logic_vector(DATA_WIDTH-1 downto 0)
irq outstd_logic
cpu_vma instd_logic
cpu_data_in instd_logic_vector(DATA_WIDTH-1 downto 0)

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