Entity work.trace
Synthesizable Hardware Trace Capture
Defined in VHDL/trace.vhd
Author: John E. Kent
Version: 0.2 from 2010-08-09
Architectures
Libraries and global use clauses
library ieee |
use ieee.std_logic_1164.all |
use ieee.std_logic_unsigned.all |
Generics
BUFF_SIZE |
integer |
:= 9 |
DATA_WIDTH |
integer |
:= 8 |
Ports
clk |
in | std_logic |
rst |
in | std_logic |
cs_r |
in | std_logic |
cs_b |
in | std_logic |
rw |
in | std_logic |
addr |
in | std_logic_vector((2*DATA_WIDTH)-1 downto 0) |
data_in |
in | std_logic_vector(DATA_WIDTH-1 downto 0) |
data_out |
out | std_logic_vector(DATA_WIDTH-1 downto 0) |
irq |
out | std_logic |
cpu_vma |
in | std_logic |
cpu_data_in |
in | std_logic_vector(DATA_WIDTH-1 downto 0) |
Generated on 1 Jan 2018 19:48:42 with VHDocL
V0.2.6