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Defined in VHDL/ACIA_RX.vhd
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| type | RxStateType | is | ( RxStart_State, RxData_state, RxParity_state, RxStop_state ) |
| acia_rx_clock_edge ( RxRst, Clk ) | ||||
| acia_rx_data_edge ( RxRst, Clk ) | ||||
| acia_rx_start_stop ( RxRst, Clk ) | ||||
| acia_rx_clock_divide ( RxRst, Clk ) | ||||
| acia_rx_baud_clock_select ( BdFmt, RxClk, RxClkCnt ) | ||||
| acia_rx_baud_clock_edge ( RxRst, Clk ) | ||||
| acia_rx_receive ( RxRst, Clk ) | ||||
| acia_rx_read ( RxRst, Clk, RxReady ) |