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Defined in VHDL/ACIA_TX.vhd
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| type | TxStateType | is | ( Tx1Stop_State, TxStart_State, TxData_State, TxParity_State, Tx2Stop_State ) |
| acia_tx_clock_edge ( TxRst, Clk ) | ||||
| acia_tx_clock_divide ( TxRst, Clk ) | ||||
| acia_tx_baud_clock_select ( BdFmt, TxClk, TxClkCnt ) | ||||
| acia_tx_baud_clock_edge ( TxRst, Clk ) | ||||
| acia_tx_write ( TxRst, Clk ) | ||||
| acia_tx_transmit ( TxRst, Clk ) |