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Defined in VHDL/pia_timer.vhd
Author: John E. Kent
Version: 1.2 from 30th May 2010
Implements 2 x 8 bit parallel I/O ports with 8 bit presetable counter.
Port A Data = output connected to presettable counter input
Port B Data = input connected to counter output
Used with Digilent Spartan 3E starter board to implement a single step trace function.
| library ieee | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all |
| pia_read ( addr, cs, irqa1, irqa2, irqb1, irqb2, porta_ddr, portb_ddr, porta_data, portb_data, porta_ctrl, portb_ctrl, pa, pb ) | ||||
| pia_write ( clk, rst, addr, cs, rw, data_in, porta_ctrl, portb_ctrl, porta_data, portb_data, porta_ctrl, portb_ctrl, porta_ddr, portb_ddr ) | ||||
| Write I/O ports | ||||
| ca1_input ( clk, rst, ca1, ca1_del, ca1_rise, ca1_fall, ca1_edge, irqa1, porta_ctrl, porta_read ) | ||||
| CA1 Edge detect | ||||
| ca2_input ( clk, rst, ca2, ca2_del, ca2_rise, ca2_fall, ca2_edge, irqa2, porta_ctrl, porta_read ) | ||||
| CA2 Edge detect | ||||
| ca2_output ( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out ) | ||||
| CA2 output control | ||||
| cb1_input ( clk, rst, cb1, cb1_del, cb1_rise, cb1_fall, cb1_edge, irqb1, portb_ctrl, portb_read ) | ||||
| CB1 Edge detect | ||||
| cb2_input ( clk, rst, cb2, cb2_del, cb2_rise, cb2_fall, cb2_edge, irqb2, portb_ctrl, portb_read ) | ||||
| CB2 Edge detect | ||||
| cb2_output ( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out ) | ||||
| CB2 output control | ||||
| pia_irq ( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl ) | ||||
| IRQ control | ||||
| pia_counter ( clk, timer, porta_data, ca2_out, cb2_out) | ||||
| 2 x 74193 binary down counter | ||||
| On the reference 6809 board, RTI takes one more clock cycle than System09. So subtract 1 from the porta_data preset value. | ||||
| 11th July 2006 John Kent: RTI in CPU09 has been extended by one bus cycle so remove the subtract by one offset on porta_data | ||||