Home -- Hierarchy -- Packages -- Entities -- Instantiations -- Sources |
Synthesizable Parallel Interface Adapter with Timer
Defined in VHDL/pia_timer.vhd
Author: John E. Kent
Version: 1.2 from 30th May 2010
library ieee | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_unsigned.all | |
library unisim | |
use unisim.vcomponents.all |
clk | in | std_logic |
rst | in | std_logic |
cs | in | std_logic |
rw | in | std_logic |
addr | in | std_logic_vector(1 downto 0) |
data_in | in | std_logic_vector(7 downto 0) |
data_out | out | std_logic_vector(7 downto 0) |
irqa | out | std_logic |
irqb | out | std_logic |