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Implements a SPI Master Controller
Defined in VHDL/spi-master.vhd
This core implements a SPI master interface. Transfer size is 4, 8, 12 or 16 bits. The SPI clock is 0 when idle, sampled on the rising edge of the SPI clock. The SPI clock is derived from the bus clock input divided by 2, 4, 8 or 16.
library ieee | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_unsigned.all |
type | state_type | is | (s_idle, s_running) | |
State type of the SPI transfer state machine |
cpu_write (clk, reset) | ||||
cpu_read (shift_reg, addr, state, deselect, start) | ||||
Provide data for the CPU to read | ||||
spi_proc (clk, reset) | ||||
SPI transfer state machine | ||||
spi_clock_gen (clk, reset) | ||||
Generate SPI clock | ||||
spi_mosi_mux (shift_reg, transfer_length) |