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Entity work.timer

Synthesizable 8 bit Timer

Defined in VHDL/timer.vhd

Author: John E. Kent
Version: 2.1 from 2010-06-17

Architectures

rtl

Instantiated in...

work.my_system09 (rtl)

Libraries and global use clauses

library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all

Ports

clk instd_logic
rst instd_logic
cs instd_logic
addr instd_logic
rw instd_logic
data_in instd_logic_vector(7 downto 0)
data_out outstd_logic_vector(7 downto 0)
irq outstd_logic

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