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Architecture for ACIA_Clock
Defined in VHDL/ACIA_Clock.vhd
Author: John E. Kent
Version: 1.0 from 30th May 2010
Implements a baud rate clock divider for a 6850 compatible Asynchronous Communications Interface Adapter .
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_arith.all | |
| use ieee.std_logic_unsigned.all | |
| library work | |
| use work.bit_funcs.all |
| FULL_CYCLE | integer | := (SYS_CLK_FREQ / ACIA_CLK_FREQ) |
| HALF_CYCLE | integer | := (FULL_CYCLE / 2) |
| my_acia_clock ( clk ) |