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Synthesizable Baud Rate Clock Divider
Defined in VHDL/ACIA_Clock.vhd
Author: John E. Kent
Version: 1.0 from 30th May 2010
ACIA_Clock is a baud rate clock divider for a 6850 compatible ACIA core.
library ieee | |
use ieee.numeric_std.all | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_arith.all | |
use ieee.std_logic_unsigned.all | |
library work | |
use work.bit_funcs.all |
SYS_CLK_FREQ | integer |
ACIA_CLK_FREQ | integer |
clk | in | Std_Logic |
acia_clk | out | Std_Logic |