Home    --    Hierarchy    --    Packages    --    Entities    --    Instantiations    --    Sources

Entity work.acia_clock

Synthesizable Baud Rate Clock Divider

Defined in VHDL/ACIA_Clock.vhd

Author: John E. Kent
Version: 1.0 from 30th May 2010


Detailed description

ACIA_Clock is a baud rate clock divider for a 6850 compatible ACIA core.

Architectures

rtl

Instantiated in...

work.my_system09 (rtl)

Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
library work
use work.bit_funcs.all

Generics

SYS_CLK_FREQ integer
ACIA_CLK_FREQ integer

Ports

clk inStd_Logic
acia_clk outStd_Logic

Generated on 1 Jan 2018 19:48:42 with VHDocL V0.2.6