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Defined in VHDL/trap.vhd
Author: John E. Kent
Version: 0.2 from 2010-08-09
Implements a 8 bit address and data hardware breakpoint comparator which generates an interrupt output on qualified match conditions.
library ieee | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_unsigned.all |
trap_write ( clk, rst, cs, rw, addr, data_in, comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl, qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl ) | ||||
trap_read ( addr, comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl, qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl, match_flag ) | ||||
trap data output mux | ||||
trap_match ( Clk, rst, cs, rw, addr, vma, match_flag, data_in, comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl, qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl) | ||||
Trap hardware |