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Defined in System09_base/sdramcntl.vhd
| library IEEE | |
| use IEEE.numeric_std.all | |
| use IEEE.std_logic_1164.all | |
| use IEEE.std_logic_unsigned.all | |
| library UNISIM | |
| use WORK.common.all |
| type | cntlState | is | ( INITWAIT, INITPCHG, INITSETMODE, INITRFSH, RW, ACTIVATE, REFRESHROW, SELFREFRESH ) | |
| states of the SDRAM controller state machine | ||||
| subtype | sdramCmd | is | unsigned(5 downto 0) | |
| subtype | sdramMode | is | std_logic_vector(12 downto 0) | |
| type | activeRowType | is | array(0 to NUM_ACTIVE_ROWS-1) of std_logic_vector(row'range) | |
| OUTPUT | std_logic | := '1' |
| INPUT | std_logic | := '0' |
| NOP | std_logic | := '0' |
| READ | std_logic | := '1' |
| WRITE | std_logic | := '1' |
| Tinit | natural | := 200 |
| Tras | natural | := 45 |
| Trcd | natural | := 20 |
| Tref | natural | := 64_000_000 |
| Trfc | natural | := 66 |
| Trp | natural | := 20 |
| Twr | natural | := 15 |
| Txsr | natural | := 75 |
| NORM | natural | := 1_000_000 |
| INIT_CYCLES | natural | := 1+((Tinit*FREQ)/1000) |
| RAS_CYCLES | natural | := 1+((Tras*FREQ)/NORM) |
| RCD_CYCLES | natural | := 1+((Trcd*FREQ)/NORM) |
| REF_CYCLES | natural | := 1+(((Tref/NROWS)*FREQ)/NORM) |
| RFC_CYCLES | natural | := 1+((Trfc*FREQ)/NORM) |
| RP_CYCLES | natural | := 1+((Trp*FREQ)/NORM) |
| WR_CYCLES | natural | := 1+((Twr*FREQ)/NORM) |
| XSR_CYCLES | natural | := 1+((Txsr*FREQ)/NORM) |
| MODE_CYCLES | natural | := 2 |
| CAS_CYCLES | natural | := 3 |
| RFSH_OPS | natural | := 8 |
| NOP_CMD | sdramCmd | := "011100" |
| ACTIVE_CMD | sdramCmd | := "001100" |
| READ_CMD | sdramCmd | := "010100" |
| WRITE_CMD | sdramCmd | := "010000" |
| PCHG_CMD | sdramCmd | := "001011" |
| MODE_CMD | sdramCmd | := "000011" |
| RFSH_CMD | sdramCmd | := "000111" |
| MODE | sdramMode | := "000" & "0" & "00" & "011" & "0" & "000" |
| ROW_LEN | natural | := log2(NROWS) |
| COL_LEN | natural | := log2(NCOLS) |
| NUM_ACTIVE_ROWS | integer | := int_select(MULTIPLE_ACTIVE_ROWS = false, 1, 2**ba'length) |
| CMDBIT_POS | natural | := 10 |
| AUTO_PCHG_ON | std_logic | := '1' |
| AUTO_PCHG_OFF | std_logic | := '0' |
| ONE_BANK | std_logic | := '0' |
| ALL_BANKS | std_logic | := '1' |
| combinatorial (rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r, opBegun_x, activeFlag_r, activeRow_r, rdPipeline_r, wrPipeline_r, hDOutOppPhase_r, nopCntr_r, lock, rfshCntr_r, timer_r, rasTimer_r, wrTimer_r, refTimer_r, cmd_r, cke_r, activeBank_r, ba_r ) | ||||
| compute the next state and outputs | ||||
| update (rst, clk) | ||||
| update registers on the appropriate clock edge | ||||