Author: John E. Kent
Version: 1.19 from 25th February 2008
| type | state_type | is |
( reset_state, vect_lo_state, vect_hi_state, fetch_state, decode1_state, decode2_state, decode3_state, imm16_state, indexed_state, index8_state, index16_state, index16_2_state, pcrel8_state, pcrel16_state, pcrel16_2_state, indexaddr_state, indexaddr2_state, postincr1_state, postincr2_state, indirect_state, indirect2_state, indirect3_state, extended_state, single_op_read_state, single_op_exec_state, single_op_write_state, dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state, dual_op_write8_state, dual_op_write16_state, sync_state, halt_state, error_state, andcc_state, orcc_state, tfr_state, exg_state, exg1_state, lea_state, mul_state, mulea_state, muld_state, mul0_state, mul1_state, mul2_state, mul3_state, mul4_state, mul5_state, mul6_state, mul7_state, lbranch_state, sbranch_state, jsr_state, jmp_state, push_return_hi_state, push_return_lo_state, pull_return_hi_state, pull_return_lo_state, int_nmiirq_state, int_firq_state, int_entire_state, int_fast_state, int_pcl_state, int_pch_state, int_upl_state, int_uph_state, int_iyl_state, int_iyh_state, int_ixl_state, int_ixh_state, int_dp_state, int_accb_state, int_acca_state, int_cc_state, int_cwai_state, int_maski_state, int_maskif_state, rti_cc_state, rti_entire_state, rti_acca_state, rti_accb_state, rti_dp_state, rti_ixl_state, rti_ixh_state, rti_iyl_state, rti_iyh_state, rti_upl_state, rti_uph_state, rti_pcl_state, rti_pch_state, pshs_state, pshs_pcl_state, pshs_pch_state, pshs_upl_state, pshs_uph_state, pshs_iyl_state, pshs_iyh_state, pshs_ixl_state, pshs_ixh_state, pshs_dp_state, pshs_acca_state, pshs_accb_state, pshs_cc_state, puls_state, puls_cc_state, puls_acca_state, puls_accb_state, puls_dp_state, puls_ixl_state, puls_ixh_state, puls_iyl_state, puls_iyh_state, puls_upl_state, puls_uph_state, puls_pcl_state, puls_pch_state, pshu_state, pshu_pcl_state, pshu_pch_state, pshu_spl_state, pshu_sph_state, pshu_iyl_state, pshu_iyh_state, pshu_ixl_state, pshu_ixh_state, pshu_dp_state, pshu_acca_state, pshu_accb_state, pshu_cc_state, pulu_state, pulu_cc_state, pulu_acca_state, pulu_accb_state, pulu_dp_state, pulu_ixl_state, pulu_ixh_state, pulu_iyl_state, pulu_iyh_state, pulu_spl_state, pulu_sph_state, pulu_pcl_state, pulu_pch_state ) |
| type | stack_type | is |
array(2 downto 0) of state_type |
| type | st_type | is |
(idle_st, push_st, pull_st ) |
| type | addr_type | is |
(idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad ) |
| type | dout_type | is |
(cc_dout, acca_dout, accb_dout, dp_dout, ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout, up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout, pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout ) |
| type | op_type | is |
(reset_op, fetch_op, latch_op ) |
| type | pre_type | is |
(reset_pre, fetch_pre, latch_pre ) |
| type | cc_type | is |
(reset_cc, load_cc, pull_cc, latch_cc ) |
| type | acca_type | is |
(reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca ) |
| type | accb_type | is |
(reset_accb, load_accb, pull_accb, latch_accb ) |
| type | dp_type | is |
(reset_dp, load_dp, pull_dp, latch_dp ) |
| type | ix_type | is |
(reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix ) |
| type | iy_type | is |
(reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy ) |
| type | sp_type | is |
(reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp ) |
| type | up_type | is |
(reset_up, latch_up, load_up, pull_hi_up, pull_lo_up ) |
| type | pc_type | is |
(reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc ) |
| type | md_type | is |
(reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md ) |
| type | ea_type | is |
(reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea ) |
| type | iv_type | is |
(latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv) |
| type | nmi_type | is |
(reset_nmi, set_nmi, latch_nmi ) |
| type | left_type | is |
(cc_left, acca_left, accb_left, dp_left, ix_left, iy_left, up_left, sp_left, accd_left, md_left, pc_left, ea_left ) |
| type | right_type | is |
(ea_right, zero_right, one_right, two_right, acca_right, accb_right, accd_right, md_right, md_sign5_right, md_sign8_right ) |
| type | alu_type | is |
(alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, alu_and, alu_ora, alu_eor, alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com, alu_lsr16, alu_lsl16, alu_ror8, alu_rol8, alu_mul, alu_asr8, alu_asl8, alu_lsr8, alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx, alu_seif, alu_sei, alu_see, alu_cle, alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa ) |
| state_stack_proc ( clk, state_stack ) |
| pc_reg ( clk ) |
| Program Counter Control |
| pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in ) |
| ea_reg ( clk ) |
| Effective Address Control |
| ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp ) |
| acca_reg ( clk ) |
| Accumulator A |
| accb_reg ( clk ) |
| Accumulator B |
| ix_reg ( clk ) |
| X Index register |
| iy_reg ( clk ) |
| Y Index register |
| sp_reg ( clk ) |
| S stack pointer |
| up_reg ( clk ) |
| U stack pointer |
| md_reg ( clk ) |
| Memory Data |
| cc_reg ( clk ) |
| Condition Codes |
| cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in ) |
| dp_reg ( clk ) |
| Direct Page register |
| dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in ) |
| iv_mux ( clk ) |
| interrupt vector |
| iv_mux: process( clk, iv_ctrl, hold, iv ) |
| op_reg ( clk ) |
| op code register |
| op_reg: process( clk, op_ctrl, hold, op_code, data_in ) |
| pre_reg ( clk ) |
| pre byte op code register |
| pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in ) |
| change_state ( clk ) |
| state machine |
| change_state: process( clk, rst, state, hold, next_state ) |
| nmi_reg ( clk ) |
| output |
| Nmi register |
| nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack ) |
| nmi_handler ( rst, clk ) |
| Detect Edge of NMI interrupt |
| nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable ) |
| addr_mux ( addr_ctrl, pc, ea, up, sp, iv ) |
| Address output multiplexer |
| dout_mux ( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc ) |
| Data Bus output |
| left_mux ( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md ) |
| Left Mux |
| right_mux ( right_ctrl, md, acca, accb, ea ) |
| Right Mux |
| alu ( alu_ctrl, cc, left, right, out_alu, cc_out ) |
| Arithmetic Logic Unit |
| unnamed ( state, saved_state, op_code, pre_code, cc, ea, md, iv, irq, firq, nmi_req, nmi_ack, halt ) |
| state sequencer |